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    • 30. 发明授权
    • Fail safe digital code rate generator
    • 故障安全数字码率发生器
    • US4053879A
    • 1977-10-11
    • US588567
    • 1975-06-20
    • Robert Anderson
    • Robert Anderson
    • B61L3/00G06F7/68G08C19/26G08C19/28
    • G08C19/26G06F7/68
    • A digital code rate generator comprises a digital number generator driven by a clock running at an appropriate frequency. Preferably the digital number generator is arranged to simultaneously generate digital representations for a plurality of different numbers. These different digital representations are provided to a selector which passes one of said digital representations to an accumulator. The accumulator continually sums the digital representations provided to it by the selector. An output of the accumulator is connected to an overflow detector which is distinctively operated when the sum of the digital representations provided to the accumulator exceeds the capacity of the accumulator. By selecting the frequency of the clock and the particular digital representation which passes the selector, the rate of operation of the overflow detector can be controlled. The output of the overflow detector thus comprises any one of a number of selectable digitally generated code rates.In another embodiment of the invention the output of the overflow detector is connected to an NAND gate whose other input is provided by the output of a divider, whose input is connected to the clock. The divider is so arranged that its output constitutes the signal carrier in a signaling system. The output of the NAND gate thus comprises a coded carrier which is turned on and off at the code rate generated by the digital code rate generator.
    • 数字码率发生器包括由以适当频率运行的时钟驱动的数字数字发生器。 优选地,数字数字发生器被布置成同时生成多个不同数字的数字表示。 这些不同的数字表示被提供给选择器,其将所述数字表示之一传递给累加器。 累加器连续地对由选择器提供给它的数字表示求和。 累加器的输出连接到溢出检测器,当提供给累加器的数字表示的总和超过累加器的容量时,溢出检测器被区分地操作。 通过选择时钟的频率和通过选择器的特定数字表示,可以控制溢出检测器的操作速率。 因此,溢出检测器的输出包括多个可选择的数字生成代码率中的任何一个。