专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明授权

US09666573B1 Methods of forming integrated circuitry 有权
公开(公告)号：US09666573B1
公开(公告)日：2017-05-30
申请号：US15335259
申请日：2016-10-26
申请人： Micron Technology, Inc.
发明人： Mitsunari Sukekawa
IPC分类号： H01L21/00 , H01L25/00 , H01L23/00 , H01L21/768 , H01L25/065
CPC分类号： H01L25/50 , H01L21/76898 , H01L23/481 , H01L24/02 , H01L24/03 , H01L24/05 , H01L24/08 , H01L24/13 , H01L24/73 , H01L24/80 , H01L24/92 , H01L24/94 , H01L25/0657 , H01L2224/0231 , H01L2224/02372 , H01L2224/0239 , H01L2224/024 , H01L2224/04 , H01L2224/05124 , H01L2224/05139 , H01L2224/05147 , H01L2224/05164 , H01L2224/05166 , H01L2224/05169 , H01L2224/05176 , H01L2224/05184 , H01L2224/05546 , H01L2224/05556 , H01L2224/05557 , H01L2224/05578 , H01L2224/05647 , H01L2224/05687 , H01L2224/05688 , H01L2224/08145 , H01L2224/13017 , H01L2224/13025 , H01L2224/131 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/73251 , H01L2224/80013 , H01L2224/80203 , H01L2224/80801 , H01L2224/80895 , H01L2224/80896 , H01L2224/80906 , H01L2224/80907 , H01L2224/92 , H01L2224/9211 , H01L2224/9222 , H01L2224/94 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/20105 , H01L2924/20106 , H01L2924/20107 , H01L2924/20108 , H01L2924/20109 , H01L2924/05442 , H01L2924/00014 , H01L2224/08 , H01L2224/80 , H01L2924/00012 , H01L2924/047 , H01L2924/049 , H01L2924/045 , H01L2924/01022 , H01L2924/01074 , H01L2924/01027 , H01L2924/01028 , H01L2924/01078 , H01L2924/05042 , H01L2924/014 , H01L2224/03 , H01L21/304 , H01L2224/11 , H01L2224/13
摘要： Some embodiments include a method of forming integrated circuitry. A first assembly is formed to have a first dielectric material, a first conductive pad and a conductive structure. The first assembly has a first surface which includes a surface of the first dielectric material, a surface of the first conductive pad and a surface of the conductive structure. A second assembly is formed to have a second dielectric material and a second conductive pad. The second assembly has a second surface which includes a surface of the second dielectric material and a surface of the second conductive pad. The first surface is placed directly against the second surface. The surface of the first dielectric material is bonded with the surface of the second dielectric material, and the surface of the first conductive pad is bonded with the surface of the second conductive pad.

32. 发明申请

US20170141079A1 SEMICONDUCTOR PACKAGE AND METHOD OF FORMING THE SAME 有权
公开(公告)号：US20170141079A1
公开(公告)日：2017-05-18
申请号：US14939253
申请日：2015-11-12
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
发明人： CHIN-FU KAO , TSEI-CHUNG FU , JING-CHENG LIN
IPC分类号： H01L25/065 , H01L25/00
CPC分类号： H01L25/0657 , H01L21/76898 , H01L24/05 , H01L24/08 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/73 , H01L24/80 , H01L24/81 , H01L24/83 , H01L24/92 , H01L25/50 , H01L2224/04 , H01L2224/0401 , H01L2224/05557 , H01L2224/05638 , H01L2224/05647 , H01L2224/05687 , H01L2224/0569 , H01L2224/08145 , H01L2224/1161 , H01L2224/11616 , H01L2224/11831 , H01L2224/13009 , H01L2224/13019 , H01L2224/13124 , H01L2224/13147 , H01L2224/13184 , H01L2224/1601 , H01L2224/16012 , H01L2224/16145 , H01L2224/16146 , H01L2224/2919 , H01L2224/32145 , H01L2224/73201 , H01L2224/73204 , H01L2224/80075 , H01L2224/80203 , H01L2224/80896 , H01L2224/8101 , H01L2224/81011 , H01L2224/81012 , H01L2224/81022 , H01L2224/81075 , H01L2224/81203 , H01L2224/81895 , H01L2224/83075 , H01L2224/83104 , H01L2224/83191 , H01L2224/83203 , H01L2224/9211 , H01L2224/94 , H01L2225/06513 , H01L2225/06544 , H01L2225/06565 , H01L2924/1434 , H01L2924/3511 , H01L2224/81 , H01L2924/01014 , H01L2924/05442 , H01L2924/05042 , H01L2924/00014 , H01L2924/07025 , H01L2224/83 , H01L2224/80 , H01L2924/00012 , H01L2224/08 , H01L2224/16 , H01L2924/01029 , H01L2924/00
摘要： The present disclosure provides a semiconductor package, including a first device having a first joining surface, a first conductive component at least partially protruding from the first joining surface, a second device having a second joining surface facing the first joining surface, and a second conductive component at least exposing from the second joining surface. The first conductive component and the second conductive component form a joint having a first beak. The first beak points to either the first joining surface or the second joining surface.

33. 发明授权

US09640509B1 Advanced metal-to-metal direct bonding 有权
公开(公告)号：US09640509B1
公开(公告)日：2017-05-02
申请号：US15280524
申请日：2016-09-29
申请人： International Business Machines Corporation
发明人： Chih-Chao Yang
IPC分类号： H01L23/00
CPC分类号： H01L24/26 , H01L24/03 , H01L24/05 , H01L24/08 , H01L24/27 , H01L24/32 , H01L24/80 , H01L24/94 , H01L25/50 , H01L2224/0341 , H01L2224/0345 , H01L2224/03452 , H01L2224/0346 , H01L2224/0361 , H01L2224/03616 , H01L2224/039 , H01L2224/04 , H01L2224/05026 , H01L2224/05073 , H01L2224/05082 , H01L2224/05157 , H01L2224/05166 , H01L2224/05176 , H01L2224/05181 , H01L2224/05184 , H01L2224/05187 , H01L2224/05557 , H01L2224/05571 , H01L2224/05572 , H01L2224/05624 , H01L2224/05647 , H01L2224/05657 , H01L2224/05673 , H01L2224/05676 , H01L2224/05681 , H01L2224/05684 , H01L2224/08145 , H01L2224/08147 , H01L2224/08148 , H01L2224/80075 , H01L2224/80201 , H01L2224/80365 , H01L2224/80385 , H01L2224/80895 , H01L2224/80948 , H01L2224/94 , H01L2224/08 , H01L2224/80 , H01L2924/00014 , H01L2924/00012 , H01L2924/04953 , H01L2924/01022 , H01L2924/0498 , H01L2924/01044 , H01L2924/01073 , H01L2924/0509 , H01L2924/0496 , H01L2924/01074
摘要： A first semiconductor structure having a first metallic structure that has a convex outermost surface and a second semiconductor structure having a second metallic structure that has a concave outermost surface are first provided. The first and second metallic structures are provided utilizing liner systems that have an opposite galvanic reaction to the metal or metal alloy that constitutes the first and second metallic structures such that during a planarization process the metal liners have a different removal rate than the metal or metal alloy that constitutes the first and second metallic structures. The first semiconductor structure and the second semiconductor structure are then bonded together such that the convex outermost surface of the first metallic structure is in direct contact with the concave outermost surface of the second metallic structure.

34. 发明申请

US20140242755A1 MAKING AN INTEGTATED CIRCUIT MODULE WITH DUAL LEADFRAMES 审中-公开
标题翻译：制作具有双重LEADFRAMES的整数电路模块
公开(公告)号：US20140242755A1
公开(公告)日：2014-08-28
申请号：US14267565
申请日：2014-05-01
申请人： Texas Instruments Incorporated
发明人： Lee Han Meng@Eugene Lee , Anis Fauzi bin Abdul Aziz , Susan Goh Geok Ling , Ng Swee Tiang
IPC分类号： H01L23/00 , H01L21/56 , H01L21/82
CPC分类号： H01L23/49575 , H01L21/56 , H01L21/565 , H01L21/82 , H01L23/3107 , H01L23/49537 , H01L23/49551 , H01L24/08 , H01L24/13 , H01L24/16 , H01L24/73 , H01L24/80 , H01L24/81 , H01L24/92 , H01L24/97 , H01L2224/0401 , H01L2224/08245 , H01L2224/131 , H01L2224/16245 , H01L2224/73251 , H01L2224/80904 , H01L2224/8121 , H01L2224/81815 , H01L2224/92222 , H01L2224/97 , H01L2924/181 , H01L2924/014 , H01L2924/00014 , H01L2224/81 , H01L2224/80 , H01L2224/16 , H01L2224/08 , H01L2924/00
摘要： A method of making an integrated circuit module starts with a top leadframe strip comprising a plurality of integrally connected top leadframes. A plurality of flipchip dies are mounted on the top leadframe strip with solder bumps of each flipchip bonded to predetermined pad portions on each of the top leadframes. The top leadframe strip is attached to a bottom leadframe strip. The bottom leadframe strip has a plurality of integrally connected bottom leadframes each having a central die attach pad (DAP) portion and a peripheral frame portion. A back face of each flipchip die contacts the DAP portion of each bottom leadframe. Lead portions of each top leadframe are attached to the peripheral frame portion of each bottom leadframe. The top leadframe strip is attached to the bottom leadframe strip with a back face of each flipchip die contacting the DAP portion of each bottom leadframe and with lead portions of each top leadframe attached to the peripheral frame portion of each bottom leadframe.
摘要翻译：制造集成电路模块的方法从包括多个整体连接的顶部引线框架的顶部引线框条开始。多个倒装芯片模具安装在顶部引线框架条上，每个倒装芯片的焊料凸块接合到每个顶部引线框架上的预定焊盘部分。顶部引线框条连接到底部引线框条。底部引线框带具有多个整体连接的底部引线框架，每个底部引线框架具有中央管芯附接焊盘（DAP）部分和外围框架部分。每个倒装芯片模具的背面接触每个底部引线框架的DAP部分。每个顶部引线框架的引线部分附接到每个底部引线框架的外围框架部分。顶部引线框条附接到底部引线框条，每个倒装芯片模具的背面接触每个底部引线框架的DAP部分，并且每个顶部引线框架的引线部分连接到每个底部引线框架的外围框架部分。

35. 发明申请

US20120217644A1 Semiconductor Device and Method of Forming Conductive THV and RDL on Opposite Sides of Semiconductor Die for RDL-to-RDL Bonding 有权
标题翻译：半导体器件和在RDL到RDL接合的半导体晶片的相对侧上形成导电THV和RDL的方法
公开(公告)号：US20120217644A1
公开(公告)日：2012-08-30
申请号：US13034133
申请日：2011-02-24
申请人： Reza A. Pagaila
发明人： Reza A. Pagaila
IPC分类号： H01L25/07 , H01L23/48 , H01L21/98
CPC分类号： H01L23/481 , H01L21/568 , H01L23/3121 , H01L24/03 , H01L24/05 , H01L24/80 , H01L24/96 , H01L25/0657 , H01L2224/0231 , H01L2224/02371 , H01L2224/03002 , H01L2224/0346 , H01L2224/03901 , H01L2224/0401 , H01L2224/04042 , H01L2224/04105 , H01L2224/05548 , H01L2224/05554 , H01L2224/05562 , H01L2224/05573 , H01L2224/0558 , H01L2224/05611 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/08 , H01L2224/08145 , H01L2224/08235 , H01L2224/16225 , H01L2224/24 , H01L2224/24011 , H01L2224/24051 , H01L2224/24145 , H01L2224/32145 , H01L2224/48091 , H01L2224/73265 , H01L2224/80203 , H01L2224/80895 , H01L2224/82 , H01L2224/821 , H01L2224/83 , H01L2224/83191 , H01L2224/83203 , H01L2224/96 , H01L2225/06524 , H01L2225/06548 , H01L2225/06565 , H01L2225/06568 , H01L2924/00014 , H01L2924/01029 , H01L2924/01322 , H01L2924/07811 , H01L2924/12041 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/15311 , H01L2924/181 , H01L2924/00015 , H01L2224/03 , H01L2224/80 , H01L2924/00 , H01L2224/05552 , H01L2924/00012
摘要： A semiconductor device has a plurality of semiconductor die mounted to a carrier. An encapsulant is deposited over the carrier around a peripheral region of the semiconductor die. A plurality of vias is formed through the encapsulant. A first conductive layer is conformally applied over a sidewall of the vias to form conductive vias. A second conductive layer is formed over a first surface of the semiconductor die between the conductive vias and contact pads of the semiconductor die. The first and second conductive layers can be formed during the same manufacturing process. A third conductive layer is formed over a second surface of the semiconductor die opposite the first surface of the semiconductor die. The third conductive layer is electrically connected to the conductive vias. A plurality of semiconductor die is stacked and electrically connected through the conductive vias and second and third conductive layers.
摘要翻译：半导体器件具有安装到载体上的多个半导体管芯。密封剂沉积在载体周围的半导体管芯的周边区域上。通过密封剂形成多个通孔。第一导电层保形地施加在通孔的侧壁上以形成导电通孔。在半导体管芯的导电通孔和接触焊盘之间的半导体管芯的第一表面上形成第二导电层。第一和第二导电层可以在相同的制造过程中形成。在半导体管芯的与半导体管芯的第一表面相对的第二表面上形成第三导电层。第三导电层电连接到导电通孔。多个半导体管芯通过导电通孔和第二和第三导电层堆叠并电连接。

36. 发明申请

WO2015183184A1 COMPACT SUBSTRATE AND METHOD FOR MAKING THE SAME 审中-公开
标题翻译：紧凑基板及其制造方法
公开(公告)号：WO2015183184A1
公开(公告)日：2015-12-03
申请号：PCT/SG2014/000238
申请日：2014-05-30
申请人： DAO, Nguyen Phu Cuong
发明人： DAO, Nguyen Phu Cuong
IPC分类号： H05K3/46 , H05K1/11 , H05K3/00 , H05K3/10 , H05K3/20 , H05K3/28
CPC分类号： H05K1/115 , H01L21/486 , H01L21/6835 , H01L23/49822 , H01L23/49827 , H01L24/08 , H01L24/16 , H01L24/73 , H01L24/80 , H01L24/81 , H01L24/92 , H01L2221/68345 , H01L2224/08238 , H01L2224/13023 , H01L2224/16111 , H01L2224/16237 , H01L2224/73201 , H01L2224/80903 , H01L2224/81011 , H01L2224/81024 , H01L2224/81385 , H01L2224/81815 , H01L2224/9211 , H05K3/0014 , H05K3/0032 , H05K3/205 , H05K3/4602 , H05K3/4682 , H05K2201/09436 , H05K2201/09545 , H05K2201/09827 , H05K2203/0108 , H01L2924/00014 , H01L2924/00012 , H01L2224/80 , H01L2224/81 , H01L2224/08 , H01L2224/16
摘要： The present invention relates to a compact substrate and a method for making the same. The compact substrate comprises at least one or a combination of a coreless structure, a double via structure and a compact double sided laser drilled (DSLD) via structure. The coreless structure has a first circuit comprising a plurality of first metal pads (151) and first metal lines (152). A first solder resist layer (16) is formed to cover parts of the first circuit and expose parts of the first metal pads (151) and parts of the first metal lines (152). Some Photo-Imageable Dielectric (PID) material can also be used to form the first solder resist layer (16). A second circuit comprising second metal pads (181) and second metal lines (182) are formed on the first solder resist layer (16). The second metal pads (181) cover the exposed first metal pads (151) and exposed first metal lines (152). The double via structure comprises a core substrate (19) having a first surface (191) and a second surface (192). Blind via holes (201) are formed on the first surface (191) of the core substrate (19). At least one through via holes (202) are formed on the base of the blind Via holes. The through via holes (202) are smaller in diameter as compared to that of the blind via holes (201). The through via holes (202) are located within the base of the blind via holes (201): The combination of the blind via holes (201) and the through via holes (202) forms the double via holes that penetrate through the core substrate (19). A compact double sided laser drilled (DSLD) via structure comprises a core substrate (19) having a first surface (191) and a second surface (192). DSLD via holes are formed and penetrate through the core substrate (19). Having the shape of two cones combined heads on, the DSLD via hole has its largest opening at its both ends and has its smallest opening somewhere near its middle portion.
摘要翻译：本发明涉及一种紧凑型基板及其制造方法。紧凑型基板包括无芯结构，双通孔结构和紧凑型双面激光钻孔（DSLD）通孔结构中的至少一种或组合。无芯结构具有包括多个第一金属焊盘（151）和第一金属线（152）的第一电路。形成第一阻焊层（16）以覆盖第一电路的部分并暴露第一金属焊盘（151）的部分和第一金属线（152）的部分。一些可光成像电介质（PID）材料也可用于形成第一阻焊层（16）。在第一阻焊层（16）上形成包括第二金属焊盘（181）和第二金属线（182）的第二电路。第二金属焊盘（181）覆盖暴露的第一金属焊盘（151）和暴露的第一金属线（152）。双通道结构包括具有第一表面（191）和第二表面（192）的芯基板（19）。在芯基板（19）的第一表面（191）上形成有盲通孔（201）。至少一个通孔（202）形成在盲孔通孔的底部上。通孔（202）的直径比盲孔（201）的直径小。通孔（202）位于盲孔（201）的基部内。盲孔（201）和通孔（202）的组合形成穿过芯基板的双通孔（19）。紧凑的双面激光钻孔（DSLD）通孔结构包括具有第一表面（191）和第二表面（192）的芯基板（19）。 DSLD通孔形成并穿透芯基板（19）。 DSLD通孔具有两个锥体的形状，其两端具有最大的开口，并且在其中间部分附近具有最小的开口。

37. 发明申请

WO2013066455A3 FLATTENED SUBSTRATE SURFACE FOR SUBSTRATE BONDING 审中-公开
标题翻译：用于基板结合的平坦化基板表面
公开(公告)号：WO2013066455A3
公开(公告)日：2014-05-08
申请号：PCT/US2012049414
申请日：2012-08-03
申请人： IBM , COONEY EDWARD C , DUNN JAMES S , MARTIN DALE W , MUSANTE CHARLES F , RAINEY BETHANN , SHI LEATHEN , SPROGIS EDMUND J , TSANG CORNELIA K
发明人： COONEY EDWARD C , DUNN JAMES S , MARTIN DALE W , MUSANTE CHARLES F , RAINEY BETHANN , SHI LEATHEN , SPROGIS EDMUND J , TSANG CORNELIA K
IPC分类号： H01L23/48 , H01L21/58
CPC分类号： H01L23/4825 , H01L21/6835 , H01L21/76819 , H01L22/32 , H01L22/34 , H01L23/5223 , H01L23/5283 , H01L24/02 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/08 , H01L24/13 , H01L24/16 , H01L24/80 , H01L24/81 , H01L29/1054 , H01L2221/68327 , H01L2221/6834 , H01L2221/68363 , H01L2221/68381 , H01L2224/0361 , H01L2224/0401 , H01L2224/05166 , H01L2224/05187 , H01L2224/05567 , H01L2224/05624 , H01L2224/05687 , H01L2224/06181 , H01L2224/08225 , H01L2224/131 , H01L2224/73251 , H01L2224/80011 , H01L2224/80013 , H01L2224/80075 , H01L2224/80203 , H01L2224/804 , H01L2224/80487 , H01L2224/80896 , H01L2224/80907 , H01L2224/80948 , H01L2224/81203 , H01L2224/81801 , H01L2224/81815 , H01L2924/00014 , H01L2924/12042 , H01L2924/1305 , H01L2924/1306 , H01L2924/13062 , H01L2924/15788 , H01L2924/014 , H01L2224/08 , H01L2224/16 , H01L2924/05432 , H01L2924/053 , H01L2924/01031 , H01L2924/01033 , H01L2924/04941 , H01L2924/00 , H01L2224/05552
摘要： Methods for bonding substrate surfaces, bonded substrate assemblies, and design structures for a bonded substrate assembly. Device structures (18, 19, 20, 21) of a product chip (25) are formed using a first surface (15) of a device substrate (10). A wiring layer (26) of an interconnect structure for the device structures is formed on the product chip. The wiring layer is planarized. A temporary handle wafer (52) is removably bonded to the planarized wiring layer. In response to removably bonding the temporary handle wafer to the planarized first wiring layer, a second surface (54) of the device substrate, which is opposite to the first surface, is bonded to a final handle substrate (56). The temporary handle wafer is then removed from the assembly.
摘要翻译：用于粘合基板表面，粘合基板组件以及用于键合衬底组件的设计结构的方法。使用器件衬底（10）的第一表面（15）形成产品芯片（25）的器件结构（18,19,20,21）。在产品芯片上形成用于器件结构的互连结构的布线层（26）。布线层被平坦化。临时处理晶片（52）可移除地结合到平坦化的布线层。响应于将临时手柄晶片可移除地结合到平坦化的第一布线层，与第一表面相对的器件基板的第二表面（54）被结合到最终的手柄基板（56）。然后将临时手柄晶片从组件中取出。

38. 发明申请

WO2013066455A2 FLATTENED SUBSTRATE SURFACE FOR SUBSTRATE BONDING 审中-公开
标题翻译：用于基板结合的平坦化基板表面
公开(公告)号：WO2013066455A2
公开(公告)日：2013-05-10
申请号：PCT/US2012/049414
申请日：2012-08-03
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , COONEY, Edward, C. , DUNN, James, S. , MARTIN, Dale, W. , MUSANTE, Charles, F. , RAINEY, BethAnn , SHI, Leathen , SPROGIS, Edmund, J. , TSANG, Cornelia, K.
发明人： COONEY, Edward, C. , DUNN, James, S. , MARTIN, Dale, W. , MUSANTE, Charles, F. , RAINEY, BethAnn , SHI, Leathen , SPROGIS, Edmund, J. , TSANG, Cornelia, K.
IPC分类号： H01L23/48 , H01L21/58
CPC分类号： H01L23/4825 , H01L21/6835 , H01L21/76819 , H01L22/32 , H01L22/34 , H01L23/5223 , H01L23/5283 , H01L24/02 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/08 , H01L24/13 , H01L24/16 , H01L24/80 , H01L24/81 , H01L29/1054 , H01L2221/68327 , H01L2221/6834 , H01L2221/68363 , H01L2221/68381 , H01L2224/0361 , H01L2224/0401 , H01L2224/05166 , H01L2224/05187 , H01L2224/05567 , H01L2224/05624 , H01L2224/05687 , H01L2224/06181 , H01L2224/08225 , H01L2224/131 , H01L2224/73251 , H01L2224/80011 , H01L2224/80013 , H01L2224/80075 , H01L2224/80203 , H01L2224/804 , H01L2224/80487 , H01L2224/80896 , H01L2224/80907 , H01L2224/80948 , H01L2224/81203 , H01L2224/81801 , H01L2224/81815 , H01L2924/00014 , H01L2924/12042 , H01L2924/1305 , H01L2924/1306 , H01L2924/13062 , H01L2924/15788 , H01L2924/014 , H01L2224/08 , H01L2224/16 , H01L2924/05432 , H01L2924/053 , H01L2924/01031 , H01L2924/01033 , H01L2924/04941 , H01L2924/00 , H01L2224/05552
摘要： Methods for bonding substrate surfaces, bonded substrate assemblies, and design structures for a bonded substrate assembly. Device structures (18, 19, 20, 21) of a product chip (25) are formed using a first surface (15) of a device substrate (10). A wiring layer (26) of an interconnect structure for the device structures is formed on the product chip. The wiring layer is planarized. A temporary handle wafer (52) is removably bonded to the planarized wiring layer. In response to removably bonding the temporary handle wafer to the planarized first wiring layer, a second surface (54) of the device substrate, which is opposite to the first surface, is bonded to a final handle substrate (56). The temporary handle wafer is then removed from the assembly.
摘要翻译：用于粘结衬底表面，键合衬底组件和用于键合衬底组件的设计结构的方法。使用器件衬底（10）的第一表面（15）形成产品芯片（25）的器件结构（18,19,20,21）。在产品芯片上形成用于器件结构的互连结构的布线层（26）。布线层被平坦化。临时处理晶片（52）可移除地结合到平坦化的布线层。响应于将临时手柄晶片可移除地结合到平坦化的第一布线层，与第一表面相对的器件基板的第二表面（54）被结合到最终的手柄基板（56）。然后将临时手柄晶片从组件中取出。

39. 发明授权

EP3007226B1 USING MEMS FABRICATION INCORPORATING INTO LED DEVICE MOUNTING AND ASSEMBLY 有权
公开(公告)号：EP3007226B1
公开(公告)日：2018-12-05
申请号：EP15188280.0
申请日：2015-10-05
申请人： Epistar Corporation
发明人： He, Guan-Ru , Yeh, Jui-Hung , Huang, Kevin T. Y. , Chen, Chih-Chung
IPC分类号： H01L25/075
CPC分类号： H01L33/62 , H01L21/6835 , H01L21/6836 , H01L24/29 , H01L24/40 , H01L24/48 , H01L24/64 , H01L24/66 , H01L24/69 , H01L24/73 , H01L24/80 , H01L24/83 , H01L24/84 , H01L24/85 , H01L24/89 , H01L24/92 , H01L24/94 , H01L25/0753 , H01L27/153 , H01L33/36 , H01L33/486 , H01L2221/68304 , H01L2221/68327 , H01L2221/6834 , H01L2221/68359 , H01L2221/68372 , H01L2221/68381 , H01L2224/29194 , H01L2224/32 , H01L2224/40245 , H01L2224/48091 , H01L2224/48245 , H01L2224/64 , H01L2224/73251 , H01L2224/80 , H01L2224/80006 , H01L2224/8085 , H01L2224/80862 , H01L2224/80874 , H01L2224/84439 , H01L2224/84444 , H01L2224/84447 , H01L2224/84455 , H01L2224/85439 , H01L2224/85444 , H01L2224/85447 , H01L2224/85455 , H01L2224/89 , H01L2224/9222 , H01L2224/94 , H01L2924/00014 , H01L2924/12041 , H01L2933/0016 , H01L2933/0066 , H01L2224/45099 , H01L2224/69 , H01L2224/83 , H01L2224/08 , H01L2224/85 , H01L2224/84 , H01L2924/00012 , H01L2224/37099
摘要： LED chip packaging assembly that facilitates an integrated method for mounting LED chips as a group to be pre-wired to be electrically connected to each other through a pattern of extendable metal wiring lines is provided. LED chips which are electrically connected to each other through extendable metal wiring lines, replace pick and place mounting and the wire bonding processes of the LED chips, respectively. Wafer level MEMS technology is utilized to form parallel wiring lines suspended and connected to various contact pads. Bonding wires connecting the LED chips are made into horizontally arranged extendable metal wiring lines which can be in a spring shape, and allowing for expanding and contracting of the distance between the connected LED chips. A tape is further provided to be bonded to the LED chips, and extended in size to enlarge distance between the LED chips to exceed the one or more prearranged distances.

40. 发明公开

EP3259709A1 BANDFÖRMIGES SUBSTRAT ZUR HERSTELLUNG VON CHIPKARTENMODULEN 审中-公开
标题翻译：用于制造芯片卡模块的带结构基板
公开(公告)号：EP3259709A1
公开(公告)日：2017-12-27
申请号：EP16704842.0
申请日：2016-02-17
申请人： Heraeus Deutschland GmbH & Co. KG
发明人： DITZEL, Eckhard , GEHLERT, Bernd , KRÜGER, Frank
IPC分类号： G06K19/077 , C25D5/12 , H01L23/538 , H01L23/00 , H01R13/03
CPC分类号： G06K19/07722 , C25D3/12 , C25D3/46 , C25D3/562 , C25D5/12 , C25D7/0614 , G06K19/07743 , H01L21/4821 , H01L23/49534 , H01L23/49565 , H01L23/49582 , H01L23/49855 , H01L24/08 , H01L24/48 , H01L24/80 , H01L24/85 , H01L24/97 , H01L2224/08225 , H01L2224/48227 , H01L2224/73251 , H01L2224/80439 , H01L2224/80455 , H01L2224/80904 , H01L2224/85439 , H01L2224/85455 , H01L2224/97 , H01L2924/00014 , H01L2924/01046 , H01L2224/08 , H01L2224/48 , H01L2224/45099 , H01L2224/80 , H01L2224/85
摘要： The invention relates to a strip-type substrate (10) consisting of a foil (15) comprising a number of substrate units (11) for producing chip card modules, the substrate (10) having an inner face (13) for at least partial direct or indirect contacting of a semiconductor chip and an outer face (12) lying opposite the inner face (13). According to the invention, the foil (15) consists of steel, in particular high-grade steel, and a first layer (21) of nickel or a nickel alloy is provided on at least some sections of the outer face (12).

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式