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41. 发明申请

US20080143453A1 OSCILLATOR CIRCUIT, PLL CIRCUIT, SEMICONDUCTOR CHIP, AND TEST APPARATUS 有权
标题翻译：振荡器电路，PLL电路，半导体芯片和测试装置
公开(公告)号：US20080143453A1
公开(公告)日：2008-06-19
申请号：US11609950
申请日：2006-12-13
申请人： Kiyotaka Ichiyama , Masahiro Ishida
发明人： Kiyotaka Ichiyama , Masahiro Ishida
IPC分类号： H03B5/08
CPC分类号： H03L7/08 , H03L7/0891
摘要： An oscillator circuit that generates an oscillation signal is provided. The oscillator circuit includes: a voltage controlled oscillator that outputs the oscillation signal with a frequency corresponding to a provided control voltage; and a jitter demodulator that extracts a phase fluctuation component of the oscillation signal outputted by the voltage controlled oscillator and modulates the control voltage according to the phase fluctuation component. The oscillator circuit may further include a low pass filter that removes a frequency component larger than a predetermined cutoff frequency of the control frequency inputted to the voltage controlled oscillator and provides the same to the voltage controlled oscillator.
摘要翻译：提供产生振荡信号的振荡电路。所述振荡器电路包括：压控振荡器，其以对应于所提供的控制电压的频率输出所述振荡信号; 以及抖动解调器，其提取由压控振荡器输出的振荡信号的相位波动分量，并根据相位波动分量调制控制电压。振荡器电路还可以包括低通滤波器，其去除大于输入到压控振荡器的控制频率的预定截止频率的频率分量，并将其提供给压控振荡器。

42. 发明申请

US20080089457A1 Jitter injection apparatus, jitter injection method, test apparatus, and communication chip 有权
标题翻译：抖动注入装置，抖动注入法，测试装置和通信芯片
公开(公告)号：US20080089457A1
公开(公告)日：2008-04-17
申请号：US11581778
申请日：2006-10-16
申请人： Masahiro Ishida
发明人： Masahiro Ishida
IPC分类号： H04L7/00
CPC分类号： H04L1/244
摘要： There is provided a jitter injection apparatus that generates an output signal having an injected jitter. The jitter injection apparatus includes a first oscillator that generates a first periodic signal, a second oscillator that generates a second periodic signal having a period different from that of the first periodic signal, and a switching section that switches which of the first periodic signal and the second periodic signal is output at every predetermined timing and outputs the switched periodic signal as the output signal.
摘要翻译：提供了一种产生具有注入抖动的输出信号的抖动注入装置。抖动注入装置包括产生第一周期信号的第一振荡器，产生具有与第一周期信号的周期不同的周期的第二周期信号的第二振荡器，以及切换部，其切换第一周期信号和在每个预定定时输出第二周期信号，并输出开关周期信号作为输出信号。

43. 发明授权

US07317309B2 Wideband signal analyzing apparatus, wideband period jitter analyzing apparatus, and wideband skew analyzing apparatus 有权
标题翻译：宽带信号分析装置，宽带周期抖动分析装置以及宽带歪斜分析装置
公开(公告)号：US07317309B2
公开(公告)日：2008-01-08
申请号：US10862904
申请日：2004-06-07
申请人： Takahiro Yamaguchi , Masahiro Ishida , Mani Soma
发明人： Takahiro Yamaguchi , Masahiro Ishida , Mani Soma
IPC分类号： G01R23/00 , G01R13/00 , G10L21/00
CPC分类号： G01R23/16 , G01R29/26 , G01R31/31709
摘要： A wideband signal analyzing apparatus for analyzing an input signal includes frequency-shifting means for generating a plurality of intermediate frequency signals by shifting a frequency of the input signal as much as respectively different frequency-shifting amounts, so that if a frequency band of the input signal is divided into a plurality of frequency bands, each of the frequency bands can be shifted to a predetermined intermediate band, spectrum measuring means for outputting a complex spectrum of each of the intermediate frequency signals, and spectrum reconstructing means for merging the complex spectra.
摘要翻译：用于分析输入信号的宽带信号分析装置包括频移装置，用于通过将输入信号的频率分别移动到分别不同的频移量来产生多个中频信号，使得如果输入的频带信号被分成多个频带，每个频带可以移动到预定的中间频带，用于输出每个中频信号的复谱的频谱测量装置和用于合并复谱的频谱重建装置。

44. 发明授权

US07313496B2 Test apparatus and test method for testing a device under test 有权
标题翻译：用于测试被测设备的测试设备和测试方法
公开(公告)号：US07313496B2
公开(公告)日：2007-12-25
申请号：US11056330
申请日：2005-02-11
申请人： Masahiro Ishida , Takahiro Yamaguchi , Mani Soma
发明人： Masahiro Ishida , Takahiro Yamaguchi , Mani Soma
IPC分类号： G01D3/00 , G01R27/28
CPC分类号： G01R31/31709 , G01R31/2882 , G01R31/31716
摘要： A testing apparatus for testing a device under test (DUT) includes a performance board; a main frame for generating a test signal for testing the DUT and determining pass/fail of the DUT based on an output signal output by the DUT; a pin electronics between the main frame and the performance board and performs sending and receiving signals between the main frame and the DUT; a deterministic jitter injecting unit for receiving the output signal without passing through the pin electronics and inputting a loop signal, which is the received output signal into which a deterministic jitter is injected, to an input pin of the DUT without passing through the pin electronics; and a switching unit for determining whether the input pin of the DUT is provided with the test signal output by the pin electronics or the loop signal output by the deterministic jitter injecting unit.
摘要翻译：用于测试被测设备（DUT）的测试设备包括一个性能板; 用于产生用于测试DUT的测试信号和根据DUT输出的输出信号确定DUT的通过/失败的主框架; 在主框架和执行板之间的引脚电子设备，并在主框架和DUT之间执行发送和接收信号; 确定性抖动注入单元，用于在不通过引脚电子装置的情况下接收输出信号，并将作为所注入的确定性抖动的接收输出信号的环路信号输入到DUT的输入引脚，而不通过引脚电子器件; 以及用于确定DUT的输入引脚是否具有由引脚电子器件输出的测试信号或由确定性抖动注入单元输出的环路信号的开关单元。

45. 发明授权

US07225378B2 Generating test patterns used in testing semiconductor integrated circuit 失效
标题翻译：生成用于测试半导体集成电路的测试图案
公开(公告)号：US07225378B2
公开(公告)日：2007-05-29
申请号：US11238822
申请日：2005-09-28
申请人： Masahiro Ishida , Takahiro Yamaguchi
发明人： Masahiro Ishida , Takahiro Yamaguchi
IPC分类号： G06F11/00 , G06F17/50
CPC分类号： G01R31/2882 , G01R31/31813 , G01R31/3183 , G01R31/318328 , G01R31/31917 , G06F11/263
摘要： A test pattern sequence to test a delay fault or an open fault which accompanies a delay occurring in an IC is easily and rapidly generated. A list of locations such as logic gates and signal lines within the circuit where a fault is likely to occur is prepared. One of the faults is selected and an initialization test pattern v1 which establishes an initial value for activating the fault at the location of a fault is determined by an implication operation. A propagation test pattern v2 which causes a stuck-at fault to be propagated to a following gate is determined by another implication operation. A sequence formed by v1 and v2 is registered with a test pattern list and the described operations are repeated until there remains no unprocessed fault in the fault list.
摘要翻译：用于测试伴随IC发生延迟的延迟故障或开路故障的测试模式序列容易且快速地产生。准备了可能发生故障的电路内诸如逻辑门和信号线之类的位置列表。选择其中一个故障，并通过暗示操作确定在故障位置确定激活故障的初始值的初始化测试模式v 1。通过另一个含义操作来确定导致卡住故障传播到跟随门的传播测试图案v 2。由v 1和v 2形成的序列用测试图案列表注册，并且重复所描述的操作，直到故障列表中没有未处理的故障。

46. 发明授权

US07225377B2 Generating test patterns used in testing semiconductor integrated circuit 失效
公开(公告)号：US07225377B2
公开(公告)日：2007-05-29
申请号：US11239414
申请日：2005-09-28
申请人： Masahiro Ishida , Takahiro Yamaguchi
发明人： Masahiro Ishida , Takahiro Yamaguchi
IPC分类号： G06F11/00 , G06F17/50
CPC分类号： G01R31/2882 , G01R31/31813 , G01R31/3183 , G01R31/318328 , G01R31/31917 , G06F11/263
摘要： Selected test pattern sequences to be used in transient power supply current testing to detect path delay faults in an IC are easily and rapidly generated. A stored fault list of path delay faults is prepared. A train of transition signal values is calculated by simulation of transitions occurring in the IC when a test pattern sequence is applied to the IC, and respective path delay fault in the stored fault list is determined whether it is a detectable fault that is capable of being detected by the transient power supply current testing by using the transition signal values. Those detectable faults that exist in the stored fault list are deleted from the stored fault list and those test pattern sequences that are used to detect the detectable faults existing in the stored fault list are registered in a test pattern sequence list as the selected test pattern sequence.

47. 发明申请

US20060162831A1 Pneumatic tire 有权
标题翻译：气动轮胎
公开(公告)号：US20060162831A1
公开(公告)日：2006-07-27
申请号：US10531725
申请日：2003-11-11
申请人： Masahiro Ishida
发明人： Masahiro Ishida
IPC分类号： B60C11/04
CPC分类号： B60C11/0306 , B60C11/0302
摘要： A pneumatic tire having improved noise buffering capability and operation stability while maintaining excellent water discharge capability. A circumferential straight main groove (1) is provided at the center of a tread center region. Arc-like curved main grooves (3) where a plurality of arc-like grooves (3a) are circumferentially formed so as to be continuous in a repeated manner are arranged on both sides of the straight main groove (1). Further, circumferential auxiliary grooves (4) with a width smaller than that of any of the straight main groove (1) and arc-like curved main grooves (3) are provided in each of both tread shoulder regions.
摘要翻译：一种具有改善的噪声缓冲能力和操作稳定性同时保持优异的排水能力的充气轮胎。在胎面中心区域的中心设有圆周直的主槽（1）。在直的主槽（2）的两侧配置弧状的主槽（3），其中多个弧形槽（3a）沿周向形成为重复连续。此外，在两个胎面胎肩区域中的每一个中设置有宽度比任何直的主槽（1）和弧形弯曲主槽（3）的宽度的周向辅助槽（4）。

48. 发明申请

US20060048876A1 Pneumatic tire 有权
标题翻译：气动轮胎
公开(公告)号：US20060048876A1
公开(公告)日：2006-03-09
申请号：US10532069
申请日：2003-11-27
申请人： Kenji Yamane , Masahiro Ishida
发明人： Kenji Yamane , Masahiro Ishida
IPC分类号： B60C11/13 , B60C11/03
CPC分类号： B60C11/1384 , B60C11/0302 , B60C11/11 , B60C11/13 , B60C11/1315
摘要： A tread surface, the tire rotational direction of which is specified in one direction, has a center region. Blocks having obtuse-angled corner portions and acute-angled corner portions are defined in the center region by at least one first circumferential groove extending in a circumferential direction of the tire on one side of the tire centerline, and first lateral grooves which extend outwardly in a widthwise direction of the tire from the first circumferential groove so as to incline towards a direction of reverse rotation of the tire and are disposed at predetermined intervals in the tire circumferential direction. Groove wall surfaces located on both sides of the obtuse-angled corner portion of each block facing to the first circumferential groove are inclined such that the inclination angles thereof are gradually greater towards the obtuse-angled corner portion and are maximum at the obtuse-angled corner portion.
摘要翻译：轮胎旋转方向在一个方向上指定的胎面表面具有中心区域。具有钝角角部和锐角角部的块通过在轮胎中心线的一侧沿轮胎的圆周方向延伸的至少一个第一周向槽而限定在中心区域，以及第一侧向槽轮胎从第一周向槽的宽度方向朝向轮胎的反向旋转方向倾斜，并且沿轮胎周向以预定间隔设置。位于面向第一周向槽的每个块的钝角角部的两侧的槽壁表面倾斜，使得其倾斜角朝向钝角角部逐渐变大，并且在钝角处的角部最大一部分。

49. 发明申请

US20060031732A1 Generating test patterns used in testing semiconductor integrated circuit 失效
公开(公告)号：US20060031732A1
公开(公告)日：2006-02-09
申请号：US11238822
申请日：2005-09-28
申请人： Masahiro Ishida , Takahiro Yamaguchi
发明人： Masahiro Ishida , Takahiro Yamaguchi
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/2882 , G01R31/31813 , G01R31/3183 , G01R31/318328 , G01R31/31917 , G06F11/263
摘要： A test pattern sequence which is used to test a delay fault or an open fault which accompanies a delay occurring in an IC is easily and rapidly generated. A list of locations such as logic gates and signal lines within the circuit where a fault is likely to occur is prepared (101). One of the faults is selected, and an initialization test pattern v1 which establishes an initial value for activating the fault at the location of a fault is determined by the implication operation (103), and a propagation test pattern v2 which causes a stuck-at fault to be propagated to a following gate is determined by the implication operation (105). A sequence formed by v1 and v2 is registered with a test pattern list (107), and the described operations are repeated until there remains no unprocessed fault in the fault list.

50. 发明申请

US20050267696A1 Measurement instrument and measurement method 有权
标题翻译：测量仪器和测量方法
公开(公告)号：US20050267696A1
公开(公告)日：2005-12-01
申请号：US10925870
申请日：2004-08-25
申请人： Takahiro Yamaguchi , Masahiro Ishida , Mani Soma
发明人： Takahiro Yamaguchi , Masahiro Ishida , Mani Soma
IPC分类号： G01R29/02 , G01R29/027 , G01R29/26 , G01R31/317 , G01R31/319 , G01R31/3193 , H04L1/20 , G01R15/00
CPC分类号： G01R31/31709 , G01R29/02 , G01R29/0273 , G01R29/26 , G01R31/31922 , G01R31/31937 , H04L1/203 , H04L1/205
摘要： A measuring apparatus for measuring reliability against jitter of an electronic device, including: a jitter tolerance estimator operable to estimate a jitter tolerance of the electronic device based on an output signal output from the electronic device according to an input signal input through a transmission line of which the transmission length is shorter than a predetermined length so that it does not generate a deterministic jitter; a jitter tolerance degradation quantity estimator operable to estimate a quantity of degradation of the jitter tolerance which deteriorates by the deterministic jitter caused in the input signal by transmission through the long transmission line when the input signal is input into the electronic device through the transmission line, of which the transmission length is longer than a predetermined length so that it may cause the deterministic jitter; a system jitter tolerance estimator operable to estimate a jitter tolerance of the electronic device and a jitter tolerance of a system including the long transmission line and the electronic device based on quantity of degradation of the jitter tolerance, is provided.
摘要翻译：一种用于测量电子设备抖动的可靠性的测量装置，包括：抖动容限估计器，用于根据从电子设备输出的输出信号，根据通过传输线输入的输入信号来估计电子设备的抖动容限其传输长度短于预定长度，使得其不产生确定性抖动; 抖动容忍劣化量估计器，用于当通过传输线路将输入信号输入到电子设备中时，通过传输通过长传输线路来估计在输入信号中产生的确定性抖动而导致的抖动容差劣化的数量，其传输长度大于预定长度，从而可能导致确定性抖动; 提供了一种用于估计电子设备的抖动容限的系统抖动容限估计器，以及基于抖动容限的劣化量的包括长传输线路和电子设备的系统的抖动容限。

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