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    • 58. 发明授权
    • High-performance memory interface circuit architecture
    • 高性能存储器接口电路架构
    • US08305121B1
    • 2012-11-06
    • US13168499
    • 2011-06-24
    • Joseph HuangChiakang SungPhilip PanYan ChongAndy L. LeeBrian D. Johnson
    • Joseph HuangChiakang SungPhilip PanYan ChongAndy L. LeeBrian D. Johnson
    • H03L7/00
    • H03L7/0812G11C7/22G11C7/222H03L7/0805
    • A programmable memory interface circuit includes a programmable DLL delay chain, a phase offset control circuit and a programmable DQS delay chain. The DLL delay chain uses a set of serially connected delay cells, a programmable switch, a phase detector and a digital counter to generate a coarse phase shift control setting. The coarse phase shift control setting is then used to pre-compute a static residual phase shift control setting or generate a dynamic residual phase shift control setting, one of which is chosen by the phase offset control circuit to be added to or subtracted from the coarse phase shift control setting to generate a fine phase shift control setting. The coarse and fine phase shift control settings work in concert to generate a phase-delayed DQS signal that is center-aligned to its associated DQ signals.
    • 可编程存储器接口电路包括可编程DLL延迟链,相位偏移控制电路和可编程DQS延迟链。 DLL延迟链使用一组串行连接的延迟单元,可编程开关,相位检测器和数字计数器来产生粗略的相移控制设置。 然后,粗略的相移控制设置用于预先计算静态残留相移控制设置或生成动态残留相移控制设置,其中一个由相位偏移控制电路选择以被加到或从粗略 相移控制设置,以产生精细的相移控制设置。 粗调和精细相移控制设置一致地产生相位延迟的DQS信号,其中心对准其相关联的DQ信号。
    • 59. 发明授权
    • High-performance memory interface circuit architecture
    • 高性能存储器接口电路架构
    • US07969215B1
    • 2011-06-28
    • US12467681
    • 2009-05-18
    • Joseph HuangChiakang SungPhilip PanYan ChongAndy L. LeeBrian D. Johnson
    • Joseph HuangChiakang SungPhilip PanYan ChongAndy L. LeeBrian D. Johnson
    • H03L7/00
    • H03L7/0812G11C7/22G11C7/222H03L7/0805
    • A programmable memory interface circuit includes a programmable DLL delay chain, a phase offset control circuit and a programmable DQS delay chain. The DLL delay chain uses a set of serially connected delay cells, a programmable switch, a phase detector and a digital counter to generate a coarse phase shift control setting. The coarse phase shift control setting is then used to pre-compute a static residual phase shift control setting or generate a dynamic residual phase shift control setting, one of which is chosen by the phase offset control circuit to be added to or subtracted from the coarse phase shift control setting to generate a fine phase shift control setting. The coarse and fine phase shift control settings work in concert to generate a phase-delayed DQS signal that is center-aligned to its associated DQ signals.
    • 可编程存储器接口电路包括可编程DLL延迟链,相位偏移控制电路和可编程DQS延迟链。 DLL延迟链使用一组串行连接的延迟单元,可编程开关,相位检测器和数字计数器来产生粗略的相移控制设置。 然后,粗略的相移控制设置用于预先计算静态残留相移控制设置或生成动态残留相移控制设置,其中一个由相位偏移控制电路选择以被加到或从粗略 相移控制设置,以产生精细的相移控制设置。 粗调和精细相移控制设置一致地产生相位延迟的DQS信号,其中心对准其相关联的DQ信号。