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51. 发明申请

US20050129104A1 Testing apparatus and testing method 失效
标题翻译：检测仪器及检测方法
公开(公告)号：US20050129104A1
公开(公告)日：2005-06-16
申请号：US10824763
申请日：2004-04-14
申请人： Masahiro Ishida , Takahiro Yamaguchi , Mani Soma
发明人： Masahiro Ishida , Takahiro Yamaguchi , Mani Soma
IPC分类号： G01R29/02 , G01R31/28 , G01R31/3167 , G01R31/317 , G01R31/319 , G01R31/3193 , H04Q1/20
CPC分类号： G01R31/31709 , G01R31/31922 , G01R31/31937
摘要： A testing device for testing an electronic device is provided. The testing device includes: a deterministic jitter application unit for applying deterministic jitter to a given input signal without causing an amplitude modulation component and supplying the input signal with the deterministic jitter to the electronic device; a jitter amount controller for controlling the magnitude of the deterministic jitter generated by the deterministic jitter application unit; and a determination unit for determining whether or not the electronic device is defective based on an output signal output from the electronic device in accordance with the input signal.
摘要翻译：提供了一种用于测试电子设备的测试设备。测试设备包括：确定性抖动应用单元，用于将确定性抖动应用于给定的输入信号，而不引起幅度调制分量，并向电子设备提供具有确定性抖动的输入信号; 抖动量控制器，用于控制由确定性抖动施加单元产生的确定性抖动的大小; 以及确定单元，用于基于根据输入信号从电子设备输出的输出信号来确定电子设备是否有故障。

52. 发明授权

US06864158B2 Method of manufacturing nitride semiconductor substrate 失效
标题翻译：氮化物半导体衬底的制造方法
公开(公告)号：US06864158B2
公开(公告)日：2005-03-08
申请号：US10032563
申请日：2002-01-02
申请人： Masahiro Ishida
发明人： Masahiro Ishida
IPC分类号： C30B25/18 , H01L21/20
CPC分类号： H01L21/0262 , C30B25/18 , H01L21/0242 , H01L21/0243 , H01L21/0254 , H01L21/02658 , H01L21/02664
摘要： A main surface of a base substrate of sapphire is selectively formed an irregular region on the main surface. Then, a semiconductor layer of gallium nitride is grown to fill recessed portions in the irregular region of the base substrate and make the upper surface even. Then, a laser beam is irradiated upon the interface between the semiconductor layer and the irregular region of the base substrate to separate the semiconductor layer from the base substrate. As a result, a nitride semiconductor substrate is produced from the semiconductor layer.
摘要翻译：蓝宝石基底基板的主表面选择性地形成在主表面上的不规则区域。然后，生长氮化镓的半导体层以填充基底基板的不规则区域中的凹部，并使上表面均匀。然后，将激光束照射在半导体层与基底基板的不规则区域之间的界面上，以将半导体层与基底基板分离。结果，从半导体层制造氮化物半导体衬底。

53. 发明授权

US06828815B2 Method and apparatus for defect analysis of semiconductor integrated circuit 失效
标题翻译：半导体集成电路缺陷分析方法与装置
公开(公告)号：US06828815B2
公开(公告)日：2004-12-07
申请号：US10779905
申请日：2004-02-17
申请人： Masahiro Ishida , Takahiro Yamaguchi , Yoshihiro Hashimoto
发明人： Masahiro Ishida , Takahiro Yamaguchi , Yoshihiro Hashimoto
IPC分类号： G01R3126
CPC分类号： G01R31/3004 , G01R31/3181
摘要： A fault analysis method and apparatus which is able to improve the reliability of fault analysis of semiconductor integrated circuit. In case of supplying a test pattern sequence having a plurality of test patterns to the semiconductor IC, an analysis point whose electric potential changes according to the change of supplied test pattern is placed corresponding to the test pattern sequence. Then, a transient power supply current generated on the semiconductor IC according to the change of the test pattern is measured and determined whether the measured transient power supply current is abnormal or not. A defection point is presumed based on the test pattern sequence where the transient power supply current is abnormal, and the analysis point placed corresponding to the test pattern sequence.
摘要翻译：一种能够提高半导体集成电路故障分析可靠性的故障分析方法和装置。在向半导体IC提供具有多个测试图案的测试图案序列的情况下，根据所提供的测试图案的变化对其电位变化的分析点与测试图案序列相对应。然后，测量根据测试图案的变化在半导体IC上产生的瞬态电源电流，并确定测量的瞬态电源电流是否异常。基于瞬态电源电流异常的测试图案序列推测出缺点，并且对应于测试图案序列放置分析点。

54. 发明授权

US06775321B1 Apparatus for and method of measuring a jitter 失效
标题翻译：用于测量抖动的装置和方法
公开(公告)号：US06775321B1
公开(公告)日：2004-08-10
申请号：US09703469
申请日：2000-10-31
申请人： Mani Soma , Masahiro Ishida , Takahiro Yamaguchi , Toshifumi Watanabe
发明人： Mani Soma , Masahiro Ishida , Takahiro Yamaguchi , Toshifumi Watanabe
IPC分类号： H04B1700
CPC分类号： G01R29/26
摘要： A signal under measurement is transformed into a complex analytic signal using Hilbert transformation to estimate an instantaneous phase of the signal under measurement from the complex analytic signal. A least mean square line of the instantaneous phase is calculated to obtain a linear instantaneous phase of the signal under measurement, and a zero-crossing timing of the signal under measurement is estimated using an interpolation method. Then a difference between the instantaneous phase and the linear instantaneous phase at the zero-crossing timing is calculated to estimate a timing jitter sequence. A jitter of the signal under measurement is obtained from the jitter sequence.
摘要翻译：使用希尔伯特变换将测量信号转换成复数分析信号，以从复数分析信号估计测量信号的瞬时相位。计算瞬时相位的最小均方根以获得测量信号的线性瞬时相位，并且使用内插方法估计测量信号的过零定时。然后计算在过零时刻的瞬时相位和线性瞬时相位之间的差以估计定时抖动序列。从抖动序列获得测量信号的抖动。

55. 发明授权

US06737852B2 Clock skew measuring apparatus and method 失效
标题翻译：时钟偏差测量装置及方法
公开(公告)号：US06737852B2
公开(公告)日：2004-05-18
申请号：US10033188
申请日：2001-10-25
申请人： Mani Soma , Masahiro Ishida , Takahiro Yamaguchi
发明人： Mani Soma , Masahiro Ishida , Takahiro Yamaguchi
IPC分类号： G01R2302
CPC分类号： G01R31/31725
摘要： A clock skew measuring apparatus for measuring a clock skew between a plurality of clock signals to be measured in a device under test, includes: a clock signal selecting element for receiving clock signals and outputting them by selecting one of the clock signals one by one; and a clock skew estimator for receiving a reference signal input to the device under test and the clock signals to be measured selected by the clock signal selecting element one by one and for obtaining the clock skew between the clock signals to be measured.
摘要翻译：一种时钟偏差测量装置，用于测量被测器件中要测量的多个时钟信号之间的时钟偏差，包括：时钟信号选择元件，用于接收时钟信号并通过逐个选择一个时钟信号来输出; 以及时钟偏差估计器，用于一个接一个地接收输入到被测器件的参考信号和由时钟信号选择元件选择的要被测量的时钟信号，并用于获得待测时钟信号之间的时钟偏差。

56. 发明授权

US06653663B2 Nitride semiconductor device 有权
标题翻译：氮化物半导体器件
公开(公告)号：US06653663B2
公开(公告)日：2003-11-25
申请号：US09729424
申请日：2000-12-05
申请人： Masahiro Ishida
发明人： Masahiro Ishida
IPC分类号： H01L2715
CPC分类号： H01L33/32 , H01L33/16 , H01S5/3202 , H01S5/32341
摘要： The nitride semiconductor device includes: a substrate made of a III-V group compound semiconductor containing nitride; and a function region made of a III-V group compound semiconductor layer containing nitride formed on a main surface of the substrate. The main surface of the substrate is tilted from a {0001} plane by an angle in a range of 13° to 90° inclusive.
摘要翻译：氮化物半导体器件包括：由含有氮化物的III-V族化合物半导体制成的衬底; 以及由在衬底的主表面上形成的包含氮化物的III-V族化合物半导体层制成的功能区域。基板的主面从{0001}面倾斜13°〜90°的范围内的角度。

57. 发明授权

US06593765B1 Testing apparatus and testing method for semiconductor integrated circuit 失效
标题翻译：半导体集成电路测试仪器及测试方法
公开(公告)号：US06593765B1
公开(公告)日：2003-07-15
申请号：US09663700
申请日：2000-09-15
申请人： Masahiro Ishida , Takahiro Yamaguchi , Yoshihiro Hashimoto
发明人： Masahiro Ishida , Takahiro Yamaguchi , Yoshihiro Hashimoto
IPC分类号： G01R3126
CPC分类号： G01R31/31917 , G01R31/3004
摘要： A testing apparatus is able to test a semiconductor integrated circuit with high observability. The testing apparatus includes a test pattern inputting means 14 for inputting a test pattern for activating a path under test of a semiconductor integrated circuit 20 to the semiconductor integrated circuit, a transient power supply current measuring means 16 for measuring transient power supply current supplied to the semiconductor integrated circuit while the path under test is being activated, and a fault detecting means 34 for judging absence and presence of a fault of the path under test, based on transient power supply current measured by the transient power supply current measuring means.
摘要翻译：测试装置能够测试具有高可观察性的半导体集成电路。测试装置包括测试图案输入装置14，用于输入用于激活半导体集成电路20的测试路径的测试图案到半导体集成电路;瞬态电源电流测量装置16，用于测量提供给半导体集成电路20的瞬态电源电流。半导体集成电路，同时正在激活测试路径;以及故障检测装置34，用于基于由瞬态电源电流测量装置测量的瞬态电源电流来判断被测路径的故障的不存在和存在。

58. 发明授权

US06593159B1 Semiconductor substrate, semiconductor device and method of manufacturing the same 失效
标题翻译：半导体衬底，半导体器件及其制造方法
公开(公告)号：US06593159B1
公开(公告)日：2003-07-15
申请号：US09532063
申请日：2000-03-21
申请人： Tadao Hashimoto , Osamu Imafuji , Masaaki Yuri , Masahiro Ishida
发明人： Tadao Hashimoto , Osamu Imafuji , Masaaki Yuri , Masahiro Ishida
IPC分类号： H01L2100
CPC分类号： H01L33/007 , B82Y20/00 , C30B25/18 , H01S5/0207 , H01S5/021 , H01S5/2231 , H01S5/3201 , H01S5/34333 , H01S2301/173
摘要： A sapphire substrate, a buffer layer of undoped GaN and a compound semiconductor crystal layer successively formed on the sapphire substrate together form a substrate of a light emitting diode. A first cladding layer of n-type GaN, an active layer of undoped In0.2Ga0.8N and a second cladding layer successively formed on the compound semiconductor crystal layer together form a device structure of the light emitting diode. On the second cladding layer, a p-type electrode is formed, and on the first cladding layer, an n-type electrode is formed. In a part of the sapphire substrate opposing the p-type electrode, a recess having a trapezoidal section is formed, so that the thickness of an upper portion of the sapphire substrate above the recess can be substantially equal to or smaller than the thickness of the compound semiconductor crystal layer.
摘要翻译：蓝宝石衬底，未掺杂GaN的缓冲层和连续形成在蓝宝石衬底上的化合物半导体晶体层一起形成发光二极管的衬底。 n型GaN的第一包层，未掺杂的In 0.2 Ga 0.8 N的有源层和连续形成在化合物半导体晶体层上的第二覆层一起形成发光二极管的器件结构。在第二包层上形成p型电极，在第一包层上形成n型电极。在与p型电极相对的蓝宝石衬底的一部分中，形成具有梯形截面的凹部，使得凹部上方的蓝宝石衬底的上部的厚度可以基本上等于或小于化合物半导体晶体层。

59. 发明授权

US06589857B2 Manufacturing method of semiconductor film 有权
公开(公告)号：US06589857B2
公开(公告)日：2003-07-08
申请号：US10100118
申请日：2002-03-19
申请人： Masahiro Ogawa , Daisuke Ueda , Masahiro Ishida
发明人： Masahiro Ogawa , Daisuke Ueda , Masahiro Ishida
IPC分类号： H01L2120
CPC分类号： C30B33/00 , C30B29/403 , C30B29/406 , C30B29/60 , H01L21/02389 , H01L21/0242 , H01L21/02458 , H01L21/0254 , H01L21/0262 , H01L21/02639 , H01L21/02647 , H01L33/007 , H01L33/0079 , H01S5/32341 , H01S2304/12
摘要： A first semiconductor film made of a nitride semiconductor is grown through epitaxial growth on a light transmitting substrate. A thermal decomposition layer is disposed in a space between the substrate and the first semiconductor film by irradiating laser light to the first semiconductor film from the back surface of the substrate. After a second semiconductor film made of a nitride semiconductor is grown through epitaxial growth while the first semiconductor film is placed on the substrate, the temperature of the substrate is lowered to room temperature. Then, by separating and removing the substrate from the first and second semiconductor films, it is possible to obtain a nitride semiconductor substrate having an area substantially as large as the area of the substrate.

60. 发明授权

US06566231B2 Method of manufacturing high performance semiconductor device with reduced lattice defects in the active region 失效
标题翻译：制造有源区域中具有减小的晶格缺陷的高性能半导体器件的方法
公开(公告)号：US06566231B2
公开(公告)日：2003-05-20
申请号：US09790908
申请日：2001-02-23
申请人： Masahiro Ogawa , Kenji Orita , Masahiro Ishida , Shinji Nakamura , Osamu Imafuji , Masaaki Yuri
发明人： Masahiro Ogawa , Kenji Orita , Masahiro Ishida , Shinji Nakamura , Osamu Imafuji , Masaaki Yuri
IPC分类号： H01L2176
CPC分类号： H01L33/007 , H01L21/02381 , H01L21/02389 , H01L21/02458 , H01L21/0254 , H01L21/02546 , H01L21/02642 , H01L21/02647
摘要： A first semiconductor layer is epitaxially grown on a semiconductor substrate and patterned to form concave and convex portions. A second semiconductor layer is formed on the first semiconductor layer using a top epitaxial mask covering the top surface of the convex portion. Lattice defects D propagating from the first semiconductor layer exist only in a region located above the center of the concave portion (a defect region Ra), while in the other region (a low defect region Rb) lattice defects D propagating from the first semiconductor layer hardly exist.
摘要翻译：第一半导体层在半导体衬底上外延生长并图案化以形成凹凸部分。使用覆盖凸部的顶面的顶部外延掩模，在第一半导体层上形成第二半导体层。从第一半导体层传播的晶格缺陷D仅存在于位于凹部的中心以上的区域（缺陷区域Ra），而在另一区域（低缺陷区域Rb）中，从第一半导体层传播的缺陷D 几乎不存在

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