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51. 发明授权

US09613664B2 Method of operating memory device including multi-level memory cells 有权
公开(公告)号：US09613664B2
公开(公告)日：2017-04-04
申请号：US14600754
申请日：2015-01-20
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Amit Berman , Uri Beitler , Jun Jin Kong
IPC分类号： H03M13/00 , G11C7/10 , G11C16/04 , G11C16/10
CPC分类号： G11C7/1006 , G11C16/0483 , G11C16/10 , G11C2207/102
摘要： A method of operating a memory device is provided. The memory device includes a plurality of multi-level memory cells of which each memory cell includes L levels. Data which is expressed in a binary number is received. A P-length string is generated from the data. The P-length string is converted to a Q-length string. The Q-length string is distributed using I levels by eliminating at least one level from the L levels. P and Q represent binary bit lengths of the P-length string and the Q-length string. Q is greater than P. L represents a maximum number of levels which each multi-level memory cell has. I is smaller than L. The Q-length string is programmed into the plurality of memory cells.

52. 发明授权

US09575661B2 Nonvolatile memory systems configured to use deduplication and methods of controlling the same 有权
标题翻译：配置为使用重复数据消除的非易失性存储器系统及其控制方法
公开(公告)号：US09575661B2
公开(公告)日：2017-02-21
申请号：US14463129
申请日：2014-08-19
申请人： Samsung Electronics Co., Ltd.
发明人： Avner Dor , Elona Erez , Jun Jin Kong
IPC分类号： G06F3/06 , G06F17/30 , G06F11/14
CPC分类号： G06F3/0608 , G06F3/0641 , G06F3/0679 , G06F3/0688 , G06F11/1453 , G06F17/30159
摘要： Systems and methods of determining a similarity between data units in a nonvolatile memory are disclosed. One method includes obtaining first and second data units and dividing the first and second data units into a first plurality of non-overlapping chunks of data and a second plurality of non-overlapping chunks of data. The method further includes determining a first plurality of values and a second plurality of values associated with the chunks, and determining a similarity between the first second data units based on the first plurality values and of the second plurality of values. In one example embodiment, a similarity between an incoming data unit and another data unit is determined based on the number of buckets storing an incoming index value and another index value associated with the another data unit. A plurality of buckets in a table is determined based on a selected plurality of hash values.
摘要翻译：公开了确定非易失性存储器中的数据单元之间的相似性的系统和方法。一种方法包括获得第一和第二数据单元，并将第一和第二数据单元划分成第一多个非重叠的数据块和第二多个非重叠的数据块。所述方法还包括确定与所述块相关联的第一多个值和第二多个值，以及基于所述第一多个值和所述第二多个值来确定所述第一第二数据单元之间的相似度。在一个示例实施例中，基于存储输入索引值的桶数和与另一数据单元相关联的另一索引值，确定输入数据单元与另一数据单元之间的相似度。基于所选择的多个散列值来确定表中的多个桶。

53. 发明授权

US09391646B2 Joint source-channel encoding and decoding for compressed and uncompressed data 有权
标题翻译：用于压缩和未压缩数据的联合源通道编码和解码
公开(公告)号：US09391646B2
公开(公告)日：2016-07-12
申请号：US14224572
申请日：2014-03-25
申请人： Samsung Electronics Co., Ltd.
发明人： Iddo Naiss , Uri Beitler , Jun Jin Kong
IPC分类号： G06F11/00 , H03M13/00 , H03M13/11 , G06F11/10
CPC分类号： H03M13/6312 , G06F11/1004 , H03M13/09 , H03M13/1102 , H03M13/152
摘要： A memory controller includes a joint source-channel encoder circuit and a joint source-channel decoder circuit. The joint source-channel encoder circuit source encodes received data independent of whether the received data is compressible data, performs error correction coding on the source encoded data, and stores the source encoded data in a memory device. The joint source-channel decoder circuit performs source decoding of the data read from the memory device between iterations of error correction coding of the read data, and outputs the read data to at least one of a buffer memory and a storage device interface. The joint source-channel decoder circuit performs the source decoding of the read data independent of whether the read data is compressed data.
摘要翻译：存储器控制器包括联合源通道编码器电路和联合源通道解码器电路。联合源信道编码器电路源对接收到的数据进行编码，独立于接收到的数据是否是可压缩数据，对源编码数据执行纠错编码，并将源编码数据存储在存储器件中。联合源信道解码器电路在读取数据的纠错编码的迭代之间对从存储器件读取的数据执行源解码，并将读取的数据输出到缓冲存储器和存储设备接口中的至少一个。联合源信道解码器电路执行读取数据的源解码，与读数据是否为压缩数据无关。

54. 发明授权

US09354969B2 Memory controller, method of operating the same, and system including the same 有权
标题翻译：内存控制器，操作方法以及包含其的系统
公开(公告)号：US09354969B2
公开(公告)日：2016-05-31
申请号：US14208340
申请日：2014-03-13
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Moshe Twitto , Avner Dor , Jun Jin Kong , Chang Kyu Seol , Hong Rak Son
IPC分类号： G11C29/00 , G06F11/10
CPC分类号： G06F11/1072 , G06F11/108
摘要： A method of processing data using a memory controller includes determining at least one cell state to which each of a plurality of multi-level cells can be changed to based on a current cell state of each multi-level cell, where each multi-level cell includes a plurality of data pages; determining one of the data pages as having a stuck bit when a value of the data page has a single mapping value based on mapping values mapped to the at least one cell state and generating stuck bit data regarding the stuck bit; and encoding write data to be stored in the multi-level cells based on the stuck bit data.
摘要翻译：使用存储器控制器处理数据的方法包括基于每个多级单元的当前单元状态来确定可以改变多个多电平单元中的每一个的至少一个单元状态，其中每个多电平单元包括多个数据页; 当数据页的值基于映射到所述至少一个单元状态的映射值具有单个映射值并且生成关于所述卡位的卡位位数据时，将所述数据页之一确定为具有卡住位; 以及基于所述卡住的位数据对要存储在所述多级单元中的写入数据进行编码。

55. 发明授权

US11128321B2 Method of operating decoder for reducing computational complexity and method of operating data storage device including the decoder 有权
公开(公告)号：US11128321B2
公开(公告)日：2021-09-21
申请号：US16882627
申请日：2020-05-25
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Dong Min Shin , Beom Kyu Shin , Heon Hwa Cheong , Jun Jin Kong , Hong Rak Son , Yeong Geol Song , Se Jin Lim
IPC分类号： H03M13/00 , H03M13/39 , H03M13/11
摘要： A method of operating a decoder, which has variable nodes and check nodes, includes receiving variable-to-check (V2C) messages from the variable nodes using a first check node among the check nodes. The number of messages having a specific magnitude among the V2C messages is counted. The magnitude of a check-to-variable (C2V) message to be transmitted to a first variable node, among the variable nodes, is determined based on the count value and the magnitude of a V2C message of the first variable node.

56. 发明申请

US20200326869A1 HALF-MATCH DEDUPLICATION 审中-公开
公开(公告)号：US20200326869A1
公开(公告)日：2020-10-15
申请号：US16382374
申请日：2019-04-12
申请人： Samsung Electronics Co., Ltd.
发明人： Noam LIVNE , Jun Jin Kong
IPC分类号： G06F3/06 , G06F16/22 , G06F12/10
摘要： A memory system may include a memory device configured to store data received from a host; and a memory controller configured to, receive a received block of the data and a logical address associated with the data from the host, detect at least one halves of the received block as being duplicate halves based on whether a respective one of the at least one halves of the received block match one or more existing halves of stored blocks stored in the memory device, selectively store the at least one halves of the received block in the memory device based on whether the respective one of the at least one halves are duplicate halves such that the duplicate halves of the received block are not stored in the memory device, and store metadata associated with retrieving the received block.

57. 发明授权

US10693503B2 Polar code decoding apparatus and method 有权
公开(公告)号：US10693503B2
公开(公告)日：2020-06-23
申请号：US16013053
申请日：2018-06-20
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Dong-Min Shin , Min Uk Kim , Ki Jun Lee , Jun Jin Kong , Hong Rak Son
IPC分类号： H03M13/29 , H03M13/13 , H03M13/27 , H03M13/09 , H03M13/00 , H03M13/15
摘要： A polar code encoding and decoding method includes generating a first and second sub-codewords. The sub-codewords correspond to pre-codewords, and the pre-codewords have a shared data aspect. The sub-codewords provide useful error-recovery for data stored in a memory. When data is read from the memory, decoding takes place. The data read operation may include hard decision decoding, soft decision decoding, or hard decision decoding followed by soft decision decoding. In the method, the shared data aspect is used to decode a first sub-codeword for which decoding was not initially successful. An apparatus is also provided.

58. 发明授权

US10607708B2 Operation method of nonvolatile memory device and storage device 有权
公开(公告)号：US10607708B2
公开(公告)日：2020-03-31
申请号：US16539290
申请日：2019-08-13
申请人： Samsung Electronics Co., Ltd.
发明人： Eun Chu Oh , Pilsang Yoon , Jun Jin Kong , Jisu Kim , Hong Rak Son , Jinbae Bang , Daeseok Byeon , Taehyun Song , Dongjin Shin , Dongsup Jin
IPC分类号： G11C16/28 , G11C29/02 , G11C16/04 , G11C29/50 , G11C16/26 , G11C16/34 , G11C11/56 , G11C16/10
摘要： An method of operating a nonvolatile memory device including a plurality of memory cells comprises receiving a read command from an external device, in response to the read command, performing, based on a reference voltage, a first cell counting operation with respect to the plurality of memory cells, adjusting at least one read voltage of first through nth read voltages (where n is a natural number greater than 1) based on a first result of the first cell counting operation, and performing, based on the adjusted at least one read voltage, a read operation corresponding to the read command with respect to the plurality of memory cells.

59. 发明申请

US20190252027A1 NON-VOLATILE MEMORY DEVICE AND A READ METHOD THEREOF 审中-公开
公开(公告)号：US20190252027A1
公开(公告)日：2019-08-15
申请号：US16141294
申请日：2018-09-25
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Dong Jin Shin , Ji Su Kim , Dae Seok Byeon , Ji Sang Lee , Jun Jin Kong , Eun Chu Oh
IPC分类号： G11C16/26 , G11C16/10 , G11C16/08 , G11C16/24 , G11C5/14
摘要： A non-volatile memory device including: a page buffer configured to latch a plurality of page data constituting one bit page of a plurality of bit pages, and a control logic configured to compare results of a plurality of read operations performed in response to a high-priority read signal set to select one of a plurality of read signals included in the high-priority read signal set as a high-priority read signal, and determine a low-priority read signal corresponding to the high-priority read signal, wherein the high-priority read signal set is for reading high-priority page data, and the low-priority read signal is for reading low-priority page data.

60. 发明申请

US20190058547A1 EFFICIENT SURVIVOR MEMORY ARCHITECTURE FOR SUCCESSIVE CANCELLATION LIST DECODING OF CHANNEL POLARIZATION CODES 审中-公开
公开(公告)号：US20190058547A1
公开(公告)日：2019-02-21
申请号：US15680661
申请日：2017-08-18
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Eran Hof , Moshe Twitto , Jun Jin Kong
IPC分类号： H04L1/00 , H03M13/37 , H03M13/45
摘要： A method of storing survivor data generated while decoding channel polarization codes in a memory module includes setting a list size that corresponds to a number of decoder units used to decode the channel polarization codes, inputting a stream of input bits to the decoder units, and sequentially decoding the input bits. Each input bit is decoded using all previous input bits decoded before the each input bit. The method further includes selecting a plurality of survivor bits from among the decoded input bits, and storing the selected survivor bits in the memory module in a binary tree configuration. The number of edges in each level of the binary tree configuration does not exceed the list size.

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