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51. 发明授权

US09893047B2 Manufacture of wafer—panel die package assembly technology 有权
公开(公告)号：US09893047B2
公开(公告)日：2018-02-13
申请号：US15490377
申请日：2017-04-18
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Bing Dang , John Knickerbocker
IPC分类号： H01L21/66 , H01L25/00 , H01L25/065 , H01L23/00 , H01L21/78 , H01L21/56 , H01L21/683 , H01L25/16 , H01L25/18 , H01L25/075 , H01L25/11 , H01L25/04 , H01L25/07
CPC分类号： H01L25/50 , H01L21/561 , H01L21/563 , H01L21/6835 , H01L21/6836 , H01L21/78 , H01L22/20 , H01L24/32 , H01L24/81 , H01L24/95 , H01L24/96 , H01L24/97 , H01L25/043 , H01L25/0652 , H01L25/0657 , H01L25/074 , H01L25/0756 , H01L25/117 , H01L25/167 , H01L25/18 , H01L2221/68322 , H01L2221/68327 , H01L2221/68359 , H01L2221/68363 , H01L2221/68381 , H01L2223/6677 , H01L2224/14181 , H01L2224/16146 , H01L2224/32145 , H01L2224/73204 , H01L2224/80121 , H01L2224/80143 , H01L2224/81005 , H01L2224/95001 , H01L2224/95144 , H01L2224/95146 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014
摘要： Disclosed is a process, structure, equipment and apparatus directed to a low cost, high volume approach for the assembly of ultra small die to three-dimensional (3D) or 2.5D semiconductor packages.

52. 发明申请

US20170221872A1 MANUFACTURE OF WAFER - PANEL DIE PACKAGE ASSEMBLY TECHNOLOGY 有权
公开(公告)号：US20170221872A1
公开(公告)日：2017-08-03
申请号：US15490377
申请日：2017-04-18
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Bing Dang , John Knickerbocker
IPC分类号： H01L25/00 , H01L21/66 , H01L21/78 , H01L25/18 , H01L25/16 , H01L23/00 , H01L21/683 , H01L21/56
CPC分类号： H01L25/50 , H01L21/561 , H01L21/563 , H01L21/6835 , H01L21/6836 , H01L21/78 , H01L22/20 , H01L24/32 , H01L24/81 , H01L24/95 , H01L24/96 , H01L24/97 , H01L25/043 , H01L25/0652 , H01L25/0657 , H01L25/074 , H01L25/0756 , H01L25/117 , H01L25/167 , H01L25/18 , H01L2221/68322 , H01L2221/68327 , H01L2221/68359 , H01L2221/68363 , H01L2221/68381 , H01L2223/6677 , H01L2224/14181 , H01L2224/16146 , H01L2224/32145 , H01L2224/73204 , H01L2224/80121 , H01L2224/80143 , H01L2224/81005 , H01L2224/95001 , H01L2224/95144 , H01L2224/95146 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014
摘要： Disclosed is a process, structure, equipment and apparatus directed to a low cost, high volume approach for the assembly of ultra small die to three-dimensional (3D) or 2.5D semiconductor packages.

53. 发明授权

US09478471B2 Apparatus and method for verification of bonding alignment 有权
标题翻译：用于验证焊接对准的装置和方法
公开(公告)号：US09478471B2
公开(公告)日：2016-10-25
申请号：US14184402
申请日：2014-02-19
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Xin-Hua Huang , Ping-Yin Liu , Lan-Lin Chao
IPC分类号： H01L21/66 , H01L23/492 , H01L21/768 , H01L23/00
CPC分类号： H01L22/34 , H01L21/768 , H01L22/20 , H01L22/30 , H01L23/492 , H01L24/05 , H01L24/08 , H01L24/80 , H01L24/89 , H01L24/94 , H01L2224/0237 , H01L2224/05647 , H01L2224/08145 , H01L2224/80011 , H01L2224/80013 , H01L2224/80075 , H01L2224/80121 , H01L2224/802 , H01L2224/80203 , H01L2224/80894 , H01L2224/80895 , H01L2224/80896 , H01L2224/94 , H01L2224/80 , H01L2924/00012 , H01L2924/00014
摘要： Presented herein is a device comprising a common node disposed in a first wafer' a test node disposed in a first wafer and having a plurality of test pads exposed at a first surface of the first wafer. The test node also has test node lines connected to the test pads and that are separated by a first spacing and extend to a second surface of the first wafer. A comb is disposed in a second wafer and has a plurality of comb lines having a second spacing different from the first spacing. Each of the comb lines has a first surface exposed at a first side of the second wafer. The comb lines provide an indication of an alignment of the first wafer and second wafer by a number or arrangement of connections made by the plurality of comb lines between the test node lines and the common node.
摘要翻译：这里提出的装置包括设置在第一晶片中的公共节点，设置在第一晶片中的测试节点，并且具有暴露在第一晶片的第一表面处的多个测试焊盘。测试节点还具有连接到测试焊盘并且被第一间隔分开并延伸到第一晶片的第二表面的测试节点线。梳子设置在第二晶片中，并且具有多个具有不同于第一间隔的第二间距的梳状线。每个梳状线具有在第二晶片的第一侧露出的第一表面。梳线通过由测试节点线和公共节点之间的多条梳线形成的多个或多个连接布置提供第一晶片和第二晶片的对准的指示。

54. 发明授权

US09048283B2 Hybrid bonding systems and methods for semiconductor wafers 有权
标题翻译：用于半导体晶片的混合键合系统和方法
公开(公告)号：US09048283B2
公开(公告)日：2015-06-02
申请号：US13542507
申请日：2012-07-05
申请人： Ping-Yin Liu , Shih-Wei Lin , Xin-Hua Huang , Lan-Lin Chao , Chia-Shiung Tsai
发明人： Ping-Yin Liu , Shih-Wei Lin , Xin-Hua Huang , Lan-Lin Chao , Chia-Shiung Tsai
IPC分类号： H01L21/30 , H01L23/00
CPC分类号： H01L24/80 , H01L24/03 , H01L24/05 , H01L24/08 , H01L24/27 , H01L24/74 , H01L24/94 , H01L2224/02215 , H01L2224/0361 , H01L2224/03616 , H01L2224/0381 , H01L2224/05647 , H01L2224/05687 , H01L2224/08145 , H01L2224/74 , H01L2224/7501 , H01L2224/75101 , H01L2224/7565 , H01L2224/75753 , H01L2224/75824 , H01L2224/80004 , H01L2224/80007 , H01L2224/8001 , H01L2224/80011 , H01L2224/80013 , H01L2224/80014 , H01L2224/80065 , H01L2224/80075 , H01L2224/80097 , H01L2224/80121 , H01L2224/80136 , H01L2224/80203 , H01L2224/80895 , H01L2224/80896 , H01L2224/83889 , H01L2224/94 , H01L2924/00014 , H01L2924/1461 , H01L2924/351 , Y10T156/15 , Y10T156/1744 , H01L2924/00012 , H01L2224/80 , H01L2924/05442 , H01L2924/00
摘要： Hybrid bonding systems and methods for semiconductor wafers are disclosed. In one embodiment, a hybrid bonding system for semiconductor wafers includes a chamber and a plurality of sub-chambers disposed within the chamber. A robotics handler is disposed within the chamber that is adapted to move a plurality of semiconductor wafers within the chamber between the plurality of sub-chambers. The plurality of sub-chambers includes a first sub-chamber adapted to remove a protection layer from the plurality of semiconductor wafers, and a second sub-chamber adapted to activate top surfaces of the plurality of semiconductor wafers prior to hybrid bonding the plurality of semiconductor wafers together. The plurality of sub-chambers also includes a third sub-chamber adapted to align the plurality of semiconductor wafers and hybrid bond the plurality of semiconductor wafers together.
摘要翻译：公开了用于半导体晶片的混合键合系统和方法。在一个实施例中，用于半导体晶片的混合键合系统包括腔室和设置在腔室内的多个子腔室。机器人处理器设置在腔室内，其适于移动多个子室内的室内的多个半导体晶片。多个子室包括适于从多个半导体晶片去除保护层的第一子室，以及适于在混合结合多个半导体之前激活多个半导体晶片的顶表面的第二子室晶圆在一起多个子室还包括适于对准多个半导体晶片并将多个半导体晶片混合地结合在一起的第三子室。

55. 发明申请

US20130256907A1 BONDED PROCESSED SEMICONDUCTOR STRUCTURES AND CARRIERS 审中-公开
公开(公告)号：US20130256907A1
公开(公告)日：2013-10-03
申请号：US13900157
申请日：2013-05-22
申请人： Soitec
发明人： Mariam Sadaka , Ionut Radu
IPC分类号： H01L23/00 , H01L23/538
CPC分类号： H01L21/76254 , H01L21/2007 , H01L21/6835 , H01L21/76898 , H01L23/5384 , H01L23/562 , H01L24/03 , H01L24/05 , H01L24/08 , H01L24/27 , H01L24/28 , H01L24/29 , H01L24/32 , H01L24/80 , H01L24/83 , H01L24/92 , H01L24/94 , H01L24/98 , H01L25/50 , H01L2221/68327 , H01L2221/68363 , H01L2221/68377 , H01L2221/68381 , H01L2224/03616 , H01L2224/0362 , H01L2224/0401 , H01L2224/04026 , H01L2224/05009 , H01L2224/056 , H01L2224/05647 , H01L2224/05687 , H01L2224/08121 , H01L2224/08146 , H01L2224/0903 , H01L2224/16145 , H01L2224/27444 , H01L2224/27616 , H01L2224/29187 , H01L2224/32145 , H01L2224/73204 , H01L2224/80 , H01L2224/80006 , H01L2224/80011 , H01L2224/80121 , H01L2224/802 , H01L2224/80203 , H01L2224/80357 , H01L2224/80805 , H01L2224/80895 , H01L2224/80896 , H01L2224/80905 , H01L2224/83 , H01L2224/83005 , H01L2224/83011 , H01L2224/83022 , H01L2224/83121 , H01L2224/83191 , H01L2224/83193 , H01L2224/832 , H01L2224/83203 , H01L2224/83205 , H01L2224/83805 , H01L2224/83896 , H01L2224/92 , H01L2224/9211 , H01L2224/94 , H01L2225/06513 , H01L2225/06541 , H01L2924/00 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01051 , H01L2924/01074 , H01L2924/01079 , H01L2924/01322 , H01L2924/05042 , H01L2924/05442 , H01L2924/10253 , H01L2924/12042 , H01L2924/1301 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/3512
摘要： Methods of fabricating semiconductor structures include implanting atom species into a carrier die or wafer to form a weakened region within the carrier die or wafer, and bonding the carrier die or wafer to a semiconductor structure. The semiconductor structure may be processed while using the carrier die or wafer to handle the semiconductor structure. The semiconductor structure may be bonded to another semiconductor structure, and the carrier die or wafer may be divided along the weakened region therein. Bonded semiconductor structures are fabricated using such methods.

56. 发明申请

US20130252375A1 Magnet Assisted Alignment Method for Wafer Bonding and Wafer Level Chip Scale Packaging 审中-公开
标题翻译：用于晶圆接合和晶圆级芯片级封装的磁辅助对准方法
公开(公告)号：US20130252375A1
公开(公告)日：2013-09-26
申请号：US13429440
申请日：2012-03-26
申请人： Ge Yi , Zongrong Liu , Yunjun Tang , Shaoping Li
发明人： Ge Yi , Zongrong Liu , Yunjun Tang , Shaoping Li
IPC分类号： H01L23/00
CPC分类号： H01L24/83 , H01L24/03 , H01L24/05 , H01L24/08 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/80 , H01L24/81 , H01L24/94 , H01L24/97 , H01L2224/0345 , H01L2224/03452 , H01L2224/03462 , H01L2224/03612 , H01L2224/03614 , H01L2224/0362 , H01L2224/03826 , H01L2224/03827 , H01L2224/0401 , H01L2224/05009 , H01L2224/05073 , H01L2224/05082 , H01L2224/05083 , H01L2224/05084 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05157 , H01L2224/05547 , H01L2224/05576 , H01L2224/05578 , H01L2224/056 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05657 , H01L2224/08146 , H01L2224/1145 , H01L2224/11452 , H01L2224/11462 , H01L2224/1162 , H01L2224/13022 , H01L2224/13025 , H01L2224/131 , H01L2224/16146 , H01L2224/80121 , H01L2224/80143 , H01L2224/80169 , H01L2224/80801 , H01L2224/81121 , H01L2224/81143 , H01L2224/81169 , H01L2224/81801 , H01L2224/94 , H01L2224/97 , H01L2924/01322 , H01L2924/1461 , H01L2924/00015 , H01L2924/00014 , H01L2924/014 , H01L2924/01026 , H01L2924/01028 , H01L2924/01078 , H01L2924/01024 , H01L2224/80 , H01L2224/81 , H01L2224/03 , H01L2224/11 , H01L2924/00
摘要： A high-precision alignment method with high throughput is proposed, which can be used for wafer-to-wafer, chip-to-wafer or chip-to-chip bonding. The scheme implements pairing patterned magnets predetermined designed and made using wafer level process on two components (wafer or chip). The magnetization in patterned magnet can be set at predetermined configuration before bonding starts. When, the two components are bought to close proximity after a coarse alignment, the magnetic force will bring the magnet pairs together and aligned the patterned magnet on one component with its mirrored or complimentary patterned magnets on the other component to minimize the overall the magnetic energy of the pairing magnet. A few patterned magnet structures and materials, with their unique merits are proposed as examples for magnet pair for the self-alignment purpose. This method enables solid contact at the bonding interface via patterned magnets under the magnetic force, which avoid the wafer drafting due to the formation of the liquid phases.
摘要翻译：提出了一种高精度的高通量对准方法，可用于晶圆到晶圆，晶片到晶圆或芯片间的接合。该方案实现了使用晶片级处理在两个部件（晶片或芯片）上预先设计和制造的配对图案化磁体。在接合开始之前，图案化磁体中的磁化可以被设定为预定的配置。当两个部件在粗对准之后被购买成靠近时，磁力将使磁体对在一起，并将其上的图案化磁体与其另一部件上的镜像或互补的图案化磁体对准，以最小化整个磁能的配对磁铁。提出了一些具有独特优点的图案化磁体结构和材料作为用于自对准目的的磁体对的示例。该方法能够在磁力下通过图案化的磁体在接合界面处实现牢固的接触，从而避免由于液相的形成引起的晶片牵伸。

57. 发明授权

US08440546B2 Methods and devices for fabricating and assembling printable semiconductor elements 有权
公开(公告)号：US08440546B2
公开(公告)日：2013-05-14
申请号：US13113504
申请日：2011-05-23
申请人： Ralph G. Nuzzo , John A. Rogers , Etienne Menard , Keon Jae Lee , Dahl-Young Khang , Yugang Sun , Matthew Meitl , Zhengtao Zhu
发明人： Ralph G. Nuzzo , John A. Rogers , Etienne Menard , Keon Jae Lee , Dahl-Young Khang , Yugang Sun , Matthew Meitl , Zhengtao Zhu
IPC分类号： H01L21/322
CPC分类号： H01L29/76 , B81C2201/0185 , B82Y10/00 , H01L21/02521 , H01L21/02603 , H01L21/02628 , H01L21/308 , H01L21/322 , H01L21/6835 , H01L23/02 , H01L24/03 , H01L24/05 , H01L24/08 , H01L24/29 , H01L24/32 , H01L24/80 , H01L24/83 , H01L24/94 , H01L24/97 , H01L25/0753 , H01L27/1285 , H01L27/1292 , H01L29/04 , H01L29/06 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/068 , H01L29/12 , H01L29/78603 , H01L29/78681 , H01L29/78696 , H01L31/0392 , H01L31/03926 , H01L31/1804 , H01L31/1864 , H01L31/1896 , H01L33/007 , H01L33/0079 , H01L33/32 , H01L2221/68368 , H01L2221/68381 , H01L2224/03 , H01L2224/0332 , H01L2224/0345 , H01L2224/03614 , H01L2224/0362 , H01L2224/05073 , H01L2224/05082 , H01L2224/05124 , H01L2224/05144 , H01L2224/05155 , H01L2224/05166 , H01L2224/05552 , H01L2224/05553 , H01L2224/05554 , H01L2224/05555 , H01L2224/05644 , H01L2224/05666 , H01L2224/08225 , H01L2224/2919 , H01L2224/32225 , H01L2224/80 , H01L2224/80006 , H01L2224/80121 , H01L2224/80862 , H01L2224/80895 , H01L2224/83 , H01L2224/83005 , H01L2224/83121 , H01L2224/83192 , H01L2224/83193 , H01L2224/8385 , H01L2224/83862 , H01L2224/9202 , H01L2224/94 , H01L2224/95 , H01L2224/97 , H01L2924/00012 , H01L2924/01032 , H01L2924/0665 , H01L2924/10253 , H01L2924/10329 , H01L2924/12032 , H01L2924/12036 , H01L2924/12041 , H01L2924/12042 , H01L2924/12043 , H01L2924/12044 , H01L2924/1305 , H01L2924/1306 , H01L2924/13063 , H01L2924/13091 , H01L2924/14 , H01L2924/1461 , H01L2924/15159 , H01L2924/15162 , H01L2924/15788 , H01L2924/1579 , Y02E10/547 , Y02P70/521 , Y10S977/707 , Y10S977/724 , H01L2924/00014 , H01L2924/00
摘要： The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations.

58. 发明申请

US20120013013A1 TEMPORARY SEMICONDUCTOR STRUCTURE BONDING METHODS AND RELATED BONDED SEMICONDUCTOR STRUCTURES 有权
标题翻译：临界半导体结构结合方法和相关的结合半导体结构
公开(公告)号：US20120013013A1
公开(公告)日：2012-01-19
申请号：US12839203
申请日：2010-07-19
申请人： Mariam Sadaka , Ionut Radu
发明人： Mariam Sadaka , Ionut Radu
IPC分类号： H01L23/52 , H01L21/30
CPC分类号： H01L21/76254 , H01L21/2007 , H01L21/6835 , H01L21/76898 , H01L23/5384 , H01L23/562 , H01L24/03 , H01L24/05 , H01L24/08 , H01L24/27 , H01L24/28 , H01L24/29 , H01L24/32 , H01L24/80 , H01L24/83 , H01L24/92 , H01L24/94 , H01L24/98 , H01L25/50 , H01L2221/68327 , H01L2221/68363 , H01L2221/68377 , H01L2221/68381 , H01L2224/03616 , H01L2224/0362 , H01L2224/0401 , H01L2224/04026 , H01L2224/05009 , H01L2224/056 , H01L2224/05647 , H01L2224/05687 , H01L2224/08121 , H01L2224/08146 , H01L2224/0903 , H01L2224/16145 , H01L2224/27444 , H01L2224/27616 , H01L2224/29187 , H01L2224/32145 , H01L2224/73204 , H01L2224/80 , H01L2224/80006 , H01L2224/80011 , H01L2224/80121 , H01L2224/802 , H01L2224/80203 , H01L2224/80357 , H01L2224/80805 , H01L2224/80895 , H01L2224/80896 , H01L2224/80905 , H01L2224/83 , H01L2224/83005 , H01L2224/83011 , H01L2224/83022 , H01L2224/83121 , H01L2224/83191 , H01L2224/83193 , H01L2224/832 , H01L2224/83203 , H01L2224/83205 , H01L2224/83805 , H01L2224/83896 , H01L2224/92 , H01L2224/9211 , H01L2224/94 , H01L2225/06513 , H01L2225/06541 , H01L2924/00 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01051 , H01L2924/01074 , H01L2924/01079 , H01L2924/01322 , H01L2924/05042 , H01L2924/05442 , H01L2924/10253 , H01L2924/12042 , H01L2924/1301 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/3512
摘要： Methods of fabricating semiconductor structures include implanting atom species into a carrier die or wafer to form a weakened region within the carrier die or wafer, and bonding the carrier die or wafer to a semiconductor structure. The semiconductor structure may be processed while using the carrier die or wafer to handle the semiconductor structure. The semiconductor structure may be bonded to another semiconductor structure, and the carrier die or wafer may be divided along the weakened region therein. Bonded semiconductor structures are fabricated using such methods.
摘要翻译：制造半导体结构的方法包括将原子物质注入到载体晶粒或晶片中以在载体晶片或晶片内形成弱化区域，并将载体晶片或晶片结合到半导体结构。可以在使用载体晶片或晶片来处理半导体结构的同时对半导体结构进行处理。半导体结构可以结合到另一个半导体结构，并且载体晶片或晶片可以沿其中的弱化区域分割。使用这种方法制造粘合的半导体结构。

59. 发明申请

WO2016185883A1 半導体装置および撮像装置审中-公开
标题翻译：半导体器件和成像器件
公开(公告)号：WO2016185883A1
公开(公告)日：2016-11-24
申请号：PCT/JP2016/063037
申请日：2016-04-26
申请人：ソニー株式会社
发明人：琴尾　健吾 , 小池　薫
IPC分类号： H01L25/065 , H01L21/60 , H01L25/07 , H01L25/18
CPC分类号： H01L27/14634 , G06F17/5068 , H01L23/522 , H01L23/5226 , H01L23/528 , H01L23/53228 , H01L23/562 , H01L23/585 , H01L24/08 , H01L24/89 , H01L25/065 , H01L25/07 , H01L25/18 , H01L27/14621 , H01L27/14627 , H01L27/14636 , H01L27/1469 , H01L2224/08145 , H01L2224/80121 , H01L2224/80895 , H01L2224/80896
摘要：半導体チップ間の接合強度を向上させる。　半導体装置において、第１の半導体チップは、第１の絶縁層と第１の絶縁層により絶縁される第１の内層回路が電気的に接続される複数の第１のパッドと複数の第１のパッドの外側に配置される線状の第１の金属層とを有する第１の接合面を備える。第２の半導体チップは、第２の絶縁層と第１のパッドに対向する位置に配置されるとともに第２の絶縁層により絶縁される第２の内層回路が電気的に接続される複数の第２のパッドと第１の金属層に対向する位置に配置される線状の第２の金属層とを有して第１の接合面と接合される第２の接合面を備える。第１の金属層および第２の金属層の幅を、第１の半導体チップの端部から第１のパッドに至る領域の第１の絶縁層および第２の絶縁層の接合強度と第１の金属層および第２の金属層の接合強度とに基づく幅にする。
摘要翻译：本发明提高了半导体芯片之间的接合强度。在该半导体器件中，第一半导体芯片设置有具有第一绝缘层的第一接合面，与第一绝缘层绝缘的第一内层电路与第一绝缘层绝缘的多个第一焊盘电连接的第一焊盘，布线到多个第一焊盘的外侧的线状层。第二半导体芯片设置有用于接合到第一接合表面并具有第二绝缘层的第二接合表面，多个第二焊盘电连接第二内层电路，第二内层电路布置在面向第一焊盘的位置并且被第二绝缘层绝缘，并且布置在面向第一金属层的位置处的线状的第二金属层。第一金属层和第二金属层的宽度是基于第一绝缘层和第二绝缘层在从第一半导体芯片的端部延伸到第一焊盘的区域中的接合强度和在接头上的宽度第一金属层和第二金属层的强度。

60. 发明申请

WO2016060274A1 基板どうしの接合方法、基板接合装置审中-公开
标题翻译：用于将基板与基板结合的方法，以及基板结合装置
公开(公告)号：WO2016060274A1
公开(公告)日：2016-04-21
申请号：PCT/JP2015/079446
申请日：2015-10-19
申请人：ボンドテック株式会社
发明人：山内　朗
IPC分类号： H01L21/02 , B23K20/00 , B23K20/16 , B23K20/24 , H01L21/68 , H01L21/683
CPC分类号： H01L24/83 , B23K20/023 , B23K20/233 , B23K20/24 , B23K37/0408 , B23K37/047 , B23K2201/40 , B23K2203/50 , H01L21/187 , H01L21/67092 , H01L21/67259 , H01L21/68 , H01L21/6831 , H01L21/6838 , H01L21/68735 , H01L23/544 , H01L24/75 , H01L24/80 , H01L24/94 , H01L2223/54426 , H01L2224/08145 , H01L2224/08146 , H01L2224/7501 , H01L2224/75102 , H01L2224/75251 , H01L2224/75252 , H01L2224/75272 , H01L2224/75303 , H01L2224/75305 , H01L2224/757 , H01L2224/75701 , H01L2224/75702 , H01L2224/75704 , H01L2224/75705 , H01L2224/75724 , H01L2224/75725 , H01L2224/75744 , H01L2224/75745 , H01L2224/75753 , H01L2224/759 , H01L2224/75901 , H01L2224/7592 , H01L2224/75981 , H01L2224/80012 , H01L2224/80013 , H01L2224/8003 , H01L2224/80047 , H01L2224/8009 , H01L2224/8013 , H01L2224/80132 , H01L2224/80203 , H01L2224/80213 , H01L2224/80893 , H01L2224/80895 , H01L2224/80896 , H01L2224/80907 , H01L2224/80908 , H01L2224/80986 , H01L2224/83009 , H01L2224/8309 , H01L2224/83896 , H01L2224/83908 , H01L2224/94 , H01L2924/00012 , H01L2224/80 , H01L2924/00014 , H01L2224/8001 , H01L2224/80009 , H01L2224/80121
摘要：【課題】基板どうしを接合する際に、基板どうしの間でのボイドの発生を防ぐとともに、ひずみを抑制して、高い位置精度で接合する。【解決手段】第一の基板と第二の基板とを接合する方法であって、前記第一の基板及び前記第二の基板のそれぞれの接合面の表面に水又はＯＨ含有物質を付着させる親水化処理を行う工程と、前記第一の基板と前記第二の基板とを、前記接合面どうしを対向させて配置するとともに、前記第一の基板を、前記接合面の外周部に対して中央部が前記第二の基板側に突出するように撓ませる工程と、前記第一の基板の前記接合面と前記第二の基板の前記接合面とを、前記中央部どうしで突き合わせる工程と、前記中央部どうしが非接合状態を維持する圧力で突き合わせた状態で、前記第一の基板の外周部と前記第二の基板の外周部との距離を縮め、前記第一の基板の前記接合面と前記第二の基板の前記接合面とを全面で突き合わせる突き合わせ工程と、を備える基板どうしの接合方法。
摘要翻译：为了将基板粘合在一起，防止在基板之间形成空隙，使应变最小化，并且以高位置精度进行接合。 [解决方案]一种将第一基板和第二基板结合在一起的方法，其中所述方法具有：进行亲水处理的步骤，其中使水或含OH物质粘附到各个键合物的表面第一基板和第二基板的表面; 用于将所述第一基板和所述第二基板布置成使得所述接合表面彼此面对并且使所述第一基板偏转以使得所述中心部分相对于所述接合表面的外周部分朝向所述第二基板侧突出的步骤; 使第一基板的接合面和第二基板的接合面在中心部彼此抵接的步骤; 并且一旦使中心部分在非粘合状态的压力下彼此抵接，则使得第一基板的外周部分与第二基板的外周部分之间的距离减小的邻接步骤并且使得第一基板的接合表面和第二基板的接合表面在整个表面上彼此邻接。

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