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51. 发明申请

US20040222819A1 General purpose delay logic 失效
标题翻译：通用延时逻辑
公开(公告)号：US20040222819A1
公开(公告)日：2004-11-11
申请号：US10453129
申请日：2003-06-03
发明人： Tyler James Johnson
IPC分类号： H03K019/173
CPC分类号： G06F1/10 , H03K2005/00156 , H03K2005/00241
摘要： A logic circuit for delaying a signal input thereto a specified number of clock cycles X, wherein X is between 1 and 2N is described. In one embodiment, the logic circuit comprises a demultiplexer (nullDEMUXnull) comprising an input for receiving the signal and N outputs; a register array comprising 2N clocked registers, wherein each of a first N of the clocked registers is connected to one of the N outputs of the DEMUX and wherein data is shifted out of one clocked register to a next clocked register on each clock cycle; and a multiplexer (nullMUXnull) comprising M inputs, wherein each of the M inputs is connected to one of the clocked registers.
摘要翻译：描述用于将输入的信号延迟到指定数量的时钟周期X的逻辑电路，其中X在1和2 N之间。在一个实施例中，逻辑电路包括解复用器（“DEMUX”），其包括用于接收信号和N个输出的输入; 包括2个N个时钟寄存器的寄存器阵列，其中，第一N个时钟控制寄存器中的每一个连接到DEMUX的N个输出中的一个，并且其中数据从一个时钟控制的寄存器中移出到每个时钟上的下一个有时钟的寄存器周期; 以及包括M个输入的多路复用器（“MUX”），其中M个输入中的每一个连接到其中一个计时寄存器。

52. 发明申请

US20030025539A1 Digitally controlled analog delay locked loop (DLL) 有权
标题翻译：数字控制模拟延迟锁定环（DLL）
公开(公告)号：US20030025539A1
公开(公告)日：2003-02-06
申请号：US09918583
申请日：2001-07-31
申请人： CYPRESS SEMICONDUCTOR CORP.
发明人： Timothy E. Fiscus
IPC分类号： H03L007/06
CPC分类号： H03L7/0814 , H03K5/133 , H03K2005/00026 , H03K2005/00208 , H03K2005/00241 , H03L7/087
摘要： An apparatus comprising an analog delay line and a control circuit. The analog delay line may be configured to generate an output signal in response to an input signal, a first control signal, and a second control signal. A phase of the output signal may be (i) coarsely adjustable with respect to the input signal in response to the first control signal and (ii) finely and continuously adjustable in response to the second control signal. The control circuit may be configured to generate the first and the second control signals in response to the input signal and the output signal.
摘要翻译：一种包括模拟延迟线和控制电路的装置。模拟延迟线可以被配置为响应于输入信号，第一控制信号和第二控制信号而产生输出信号。输出信号的相位可以（i）响应于第一控制信号而相对于输入信号可粗略调节，以及（ii）响应于第二控制信号精细地且连续地可调。控制电路可以被配置为响应于输入信号和输出信号而产生第一和第二控制信号。

53. 发明专利

NO20054234A 未知
公开(公告)号：NO20054234A
公开(公告)日：2006-03-15
申请号：NO20054234
申请日：2005-09-13
申请人： NIPPON PRECISION CIRCUITS
发明人： KANEHACHI KAORU , TOYAMA AKIRA
IPC分类号： H03L7/08 , H03L20060101
CPC分类号： H03L7/0807 , H03K2005/00052 , H03K2005/00156 , H03K2005/00241

54. 发明公开

EP1811664A3 System and method for multiple-phase clock generation 审中-公开
标题翻译：系统和方法，用于产生多相位时钟
公开(公告)号：EP1811664A3
公开(公告)日：2010-01-27
申请号：EP06127217.5
申请日：2006-12-27
申请人： STMicroelectronics Pvt. Ltd.
发明人： Sen, Tanmoy , Kumar, Anand , Kumar Jain, Deependra Padam Chand Jain
IPC分类号： H03K5/15
CPC分类号： H03K3/0315 , H03K3/03 , H03K5/15013 , H03K5/15026 , H03K5/1506 , H03K2005/00241 , H03K2005/00247 , H03L7/095 , H03L7/0995 , Y10S331/02
摘要： A system and method for multiple phase clock generation is disclosed. The disclosed multiple phase clock circuit comprises of a multiple stage voltage controlled oscillator (401) (VCO) and multiple clock dividers (402A-402M). The voltage controlled oscillator (VCO) is made to operate at frequency 'N' times higher than the required output frequency. It generates 'M' equally spaced outputs having different phases but same frequency which are sent to multiple clock dividers. A modified Johnson counter is used as a clock divider. Each counter divides the frequency of the clock signal by N. As a result, each of the M outputs of the VCO are divided into N outputs, thereby making a total of 'M x N' equally spaced outputs. These output clock pulses have same frequency but different phases. A sequential logic (403) is provided within the device for enabling the Johnson counters as soon as the VCO starts giving output. This maintains the sequence of the output of the Johnson counters.

55. 发明公开

EP1811664A2 System and method for multiple-phase clock generation 审中-公开
标题翻译：系统和Verfahren zur Erzeugung eines Mehrphasentaktes
公开(公告)号：EP1811664A2
公开(公告)日：2007-07-25
申请号：EP06127217.5
申请日：2006-12-27
申请人： STMicroelectronics Pvt. Ltd.
发明人： Sen, Tanmoy , Kumar, Anand , Kumar Jain, Deependra Padam Chand Jain
IPC分类号： H03K5/15
CPC分类号： H03K3/0315 , H03K3/03 , H03K5/15013 , H03K5/15026 , H03K5/1506 , H03K2005/00241 , H03K2005/00247 , H03L7/095 , H03L7/0995 , Y10S331/02
摘要： A system and method for multiple phase clock generation is disclosed. The disclosed multiple phase clock circuit comprises of a multiple stage voltage controlled oscillator (401) (VCO) and multiple clock dividers (402A-402M). The voltage controlled oscillator (VCO) is made to operate at frequency 'N' times higher than the required output frequency. It generates 'M' equally spaced outputs having different phases but same frequency which are sent to multiple clock dividers. A modified Johnson counter is used as a clock divider. Each counter divides the frequency of the clock signal by N. As a result, each of the M outputs of the VCO are divided into N outputs, thereby making a total of 'M x N' equally spaced outputs. These output clock pulses have same frequency but different phases. A sequential logic (403) is provided within the device for enabling the Johnson counters as soon as the VCO starts giving output. This maintains the sequence of the output of the Johnson counters.
摘要翻译：公开了一种用于多相时钟产生的系统和方法。所公开的多相时钟电路包括多级压控振荡器（401）（VCO）和多个时钟分频器（402A-402M）。压控振荡器（VCO）的工作频率高于所需输出频率的“N”倍。它产生具有不同相位但相同频率的“M”等间距输出，发送到多个时钟分频器。修改后的约翰逊计数器用作时钟分频器。每个计数器将时钟信号的频率除以N.结果，VCO的M个输出中的每一个被分成N个输出，从而形成总共“M×N”个等间隔的输出。这些输出时钟脉冲具有相同的频率但不同的相位。一旦在VCO开始输出时，该器件内就提供一个顺序逻辑（403），用于启用约翰逊计数器。这保持了约翰逊计数器的输出顺序。

56. 发明授权

EP1282229B1 Digitally controlled analog delay locked loop (DLL) 有权
标题翻译：数字控制的模拟延迟锁定环
公开(公告)号：EP1282229B1
公开(公告)日：2007-05-23
申请号：EP01127404.0
申请日：2001-11-23
申请人： CYPRESS SEMICONDUCTOR CORPORATION
发明人： Fiscus, Timothy E.
IPC分类号： H03K5/15 , H03K5/13 , H03L7/087 , H03L7/081
CPC分类号： H03L7/0814 , H03K5/133 , H03K2005/00026 , H03K2005/00208 , H03K2005/00241 , H03L7/087

57. 发明公开

EP1490970A1 DIGITALE VERZÖGERUNGSLEITUNG 审中-公开
标题翻译：数字延迟线
公开(公告)号：EP1490970A1
公开(公告)日：2004-12-29
申请号：EP02792652.6
申请日：2002-12-11
申请人： ROBERT BOSCH GMBH
发明人： HOETZEL, Juergen , KIRCHHOF-FALTER, Guenther , MEUTH, Hermann
IPC分类号： H03K5/13 , G01S13/00
CPC分类号： H03K5/131 , G01S13/00 , H03K5/133 , H03K2005/00241 , H03K2005/00247
摘要： The invention relates to a digital delay line comprising a first feedback delay line (1) with a first number (n) of interlinked first delay elements (2) and at least a second feedback counter device (5, 8, 9,...) with a second number (n) of second interlinked counter elements (6), whereby the counter elements are supplied with pulses by one of the first delay elements.

58. 发明授权

EP0158980B1 Digital time base corrector 失效
标题翻译：数字时基校正器
公开(公告)号：EP0158980B1
公开(公告)日：1992-07-08
申请号：EP85104421.4
申请日：1985-04-11
申请人： SONY CORPORATION
发明人： Shirota, Norihisa , Yamazaki, Takao , Iwase, Seiichiro
IPC分类号： G06F5/06
CPC分类号： H03K5/131 , G11B20/18 , H03K2005/00241 , H04N5/95

59. 发明公开

EP0158980A3 Digital time base corrector 失效
标题翻译：数字时基校正器
公开(公告)号：EP0158980A3
公开(公告)日：1989-09-06
申请号：EP85104421.4
申请日：1985-04-11
申请人： SONY CORPORATION
发明人： Shirota, Norihisa , Yamazaki, Takao , Iwase, Seiichiro
IPC分类号： G06F5/06
CPC分类号： H03K5/131 , G11B20/18 , H03K2005/00241 , H04N5/95
摘要： There is provided a digital time base corrector in which a digital input signal of one block consisting of a continuous data time sequence is converted to a digital signal including data lack intervals or vice versa by a variable delay circuit (11, 51). A signal selecting circuit (12) is divided into N first unit selecting circuits (21, 22, 23, 24) and a second unit selecting circuit (25). M of the output signals of a shift register (R 1 , R 2 , ...) are inputted to the first unit selecting circuits (21, 22, 23, 24), by which one of them is selected. The outputs of the N first unit selecting circuits (21, 22, 23, 24) are supplied to the second unit selecting circuit (25), by which one of them is selected. A pipeline process is performed by inserting a delay circuit (R 21 , R 22 , R 23 , R 2 4) to delay the signal for the time of one clock period into the input/output line of the second unit selecting circuit (25). Further, the selecting signal can be made variable for every one clock and a delay circuit (33,37) is inserted on the output side of a selecting signal forming circuit (13). With this corrector, the influence of the gate delay of the selectors can be reduced and the high speed data process can be performed.

60. 发明公开

EP0158980A2 Digital time base corrector 失效
标题翻译：数字时基校正器
公开(公告)号：EP0158980A2
公开(公告)日：1985-10-23
申请号：EP85104421.4
申请日：1985-04-11
申请人： SONY CORPORATION
发明人： Shirota, Norihisa , Yamazaki, Takao , Iwase, Seiichiro
IPC分类号： G06F5/06
CPC分类号： H03K5/131 , G11B20/18 , H03K2005/00241 , H04N5/95
摘要： There is provided a digital time base corrector in which a digital input signal of one block consisting of a continuous data time sequence is converted to a digital signal including data lack intervals or vice versa by a variable delay circuit (11, 51). A signal selecting circuit (12) is divided into N first unit selecting circuits (21, 22, 23, 24) and a second unit selecting circuit (25). M of the output signals of a shift register (R 1 , R 2 , ...) are inputted to the first unit selecting circuits (21, 22, 23, 24), by which one of them is selected. The outputs of the N first unit selecting circuits (21, 22, 23, 24) are supplied to the second unit selecting circuit (25), by which one of them is selected. A pipeline process is performed by inserting a delay circuit (R 21 , R 22 , R 23 , R 2 4) to delay the signal for the time of one clock period into the input/output line of the second unit selecting circuit (25). Further, the selecting signal can be made variable for every one clock and a delay circuit (33,37) is inserted on the output side of a selecting signal forming circuit (13). With this corrector, the influence of the gate delay of the selectors can be reduced and the high speed data process can be performed.
摘要翻译：提供了一种数字时基校正器，其中由连续数据时间序列组成的一个数据块的数字输入信号由可变延迟电路（11,51）转换为包括数据缺失间隔的数字信号，反之亦然。信号选择电路（12）被分成N个第一单元选择电路（21,22,23,24）和第二单元选择电路（25）。移位寄存器（R1，R2，...）的输出信号的M被输入到第一单元选择电路（21,22,23,24），通过它们中的一个被选择。 N个第一单元选择电路（21,22,23,24）的输出被提供给第二单元选择电路（25），通过它们中的一个被选择。通过插入延迟电路（R21，R22，R23，R24）以将信号延迟一个时钟周期的时间到第二单元选择电路（25）的输入/输出线中来执行流水线处理。此外，选择信号可以在每个时钟中变化，并且延迟电路（33,37）被插入选择信号形成电路（13）的输出侧。利用该校正器，可以减少选择器的门延迟的影响并且可以执行高速数据处理。

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