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61. 发明专利

JP2004516571A Hardware loop to use resources efficiently 有权
公开(公告)号：JP2004516571A
公开(公告)日：2004-06-03
申请号：JP2002551695
申请日：2001-12-20
申请人：アナログ・デバイセズ・インコーポレイテッドAnalog Devices, Inc , インテル・コーポレーション
发明人：イノウエ，リョウ , オーバカンプ，グレゴリー，エー , シン，ラヴィ，ピー , ロス，チャールズ，ピー
IPC分类号： G06F9/30 , G06F9/32 , G06F9/38
CPC分类号： G06F9/3885 , G06F9/30101 , G06F9/325 , G06F9/3867
摘要：ある実施例において、プログラム可能なプロセッサは、ハードウェア・ループをサポートするために適合される。プロセッサは、レジスタの第１セット、レジスタの第２セット、第１パイプライン、および第２パイプラインのようなハードウェアを含む。さらに、プロセッサは、ハードウェア・ループを実行するときに、ハードウェアを効率的に実行するために適合された制御ユニットを含む。

62. 发明专利

JP2004516545A Load of instruction after a reset of the processor 审中-公开
公开(公告)号：JP2004516545A
公开(公告)日：2004-06-03
申请号：JP2002550516
申请日：2001-12-10
申请人：アナログ・デバイセズ・インコーポレイテッドAnalog Devices, Inc , インテル・コーポレーション
发明人：カラゴトラ，ラヴィ , シン，ラヴィ，ピー , レビーラ，ジュアン，ジー , ロス，チャールズ，ピー
IPC分类号： G06F1/24 , G06F9/38
CPC分类号： G06F9/3802 , G06F1/24 , G06F9/3861
摘要：一実施例において、拡張リセットでプロセッサの命令フェッチ要求を保持するための方法が示される。プロセッサがリセットされているとき、フェッチ要求は不能である。リセットが終了したとき、命令メモリがロードされている場合にはフェッチ要求は不能のままである。命令メモリのロードが終了したとき、フェッチ要求が可能になる。

63. 发明专利

JP2002141793A DRIVER CIRCUIT WITH HIGH VOLTAGE TOLERANCE AND EXTENSIBILITY 审中-公开
公开(公告)号：JP2002141793A
公开(公告)日：2002-05-17
申请号：JP2001270596
申请日：2001-09-06
申请人： ANALOG DEVICES INC
发明人： SINGH JASPREET , KOKER GREGORY T , NEWMAN MARK R
IPC分类号： H03K17/10 , G06F13/40 , H03K19/003 , H03K19/0175
摘要： PROBLEM TO BE SOLVED: To provide an input output driver circuit that has both high level voltage tolerance and extensibility and has only two power supply pins. SOLUTION: The input output driver circuit employs two PMOS switching transistors (T1A, T1B) between an output line (30) of the circuit and an output power terminal (42) instead of one transistor to provide a buffer interface between a functional digital circuit (14) and a common bus (18) for other digital circuits and uses only the two required power pins (38, 42) while attaining high level voltage tolerance and the extensibility. Applying a voltage of an output power supply (40) to one-side gates of the transistors and the output line voltage to the other gates switches off the transistors. Thus, at least either of the transistors is surely turned off as required at maximum independently of whether or not the output line voltage exceeds the output power level.

64. 发明专利

JP2000068748A DIRECT CONVERSION CIRCUIT 失效
公开(公告)号：JP2000068748A
公开(公告)日：2000-03-03
申请号：JP22840199
申请日：1999-08-12
申请人： ANALOG DEVICES INC
发明人： ATKINSON SIMON
IPC分类号： H03D1/22 , H03D3/00
摘要： PROBLEM TO BE SOLVED: To reduce interference between a local oscillation signal and an RF (radio frequency) signal. SOLUTION: This circuit includes two mixers 32, 36 in an orthogonal relation, a phase shifting unit 50 and a local oscillator. The two mixers 32 and 36 are connected with the input port 30 of a radio frequency signal to mix a radio frequency inputted signal to convert into a low frequency. The unit 50 is connected with at least one of the mixers 32 and 36 to phase-shift the local oscillation signal. The local oscillator is constituted of a phase-locked loop including frequency dividers 40 and 44. The output signal of a first voltage controlled oscillator 38 is frequency-multiplied to be a non-integer value N/M-fold by this loop to be a local oscillation signal. Since the frequency of the oscillator 38 is the non-integer multiple of RF, interference from RF is reduced.

65. 发明专利

JPH104352A METHOD AND DEVICE FOR CLAMPING INPUT 失效
公开(公告)号：JPH104352A
公开(公告)日：1998-01-06
申请号：JP2362297
申请日：1997-02-06
申请人： ANALOG DEVICES INC
发明人： CHRISTOPHER W MANGELSDORFF , NAKAMURA KATSUSHI
IPC分类号： G11C27/02 , H03G11/00 , H03K5/08 , H03M1/10 , H03M1/18 , H04N5/18 , H04N5/20 , H04N5/357 , H04N5/361 , H04N5/372 , H04N5/378 , H04N5/335
摘要： PROBLEM TO BE SOLVED: To clamp an input voltage level to a desired voltage within an operating range of the device by calibrating an offset level added to a signal and collating the signal with a desired reference level at an output. SOLUTION: A correlation double sampling circuit 71 samples two signals on an input line 24, low frequency noise and offset in common to both the samples are eliminated and a difference signal is outputted. A black level correction circuit 77' calibrates the offset level so as to obtain a desired reference level at the output of the device. Then a clamp circuit, controls an output voltage of the correlation double sampling circuit 71 and a desired voltage level at an input of the correlation double sampling circuit 71 so as to servo within a device supply range and the operating range.

66. 发明专利

JPH08237045A INTEGRATED CIRCUIT AMPLIFIER 失效
公开(公告)号：JPH08237045A
公开(公告)日：1996-09-13
申请号：JP34462395
申请日：1995-12-05
申请人： ANALOG DEVICES INC
发明人： ROIYARU EI GOTSUSAA , JIEFURII EI TAUNZENDO
IPC分类号： H03F1/32 , H03F3/18 , H03F3/30 , H03F3/34
摘要： PROBLEM TO BE SOLVED: To provide an IC amplifier provided with a continuous series of cascade stages by providing an additional control circuit in a form of a complementary gm (mutual conductance) generator to control the collector current of a transistor TR in the second stage. SOLUTION: Coupled gain stages A1/the inverse of A1 and A2/the inverse of A2 give a negative feedback mutual resistance gain. A stage GMC/the inverse of GMC is a mutual conductance generator which reduces a close loop gain error in a low gain and gives a common mode static current control of the gain stage A2/the inverse of A2. That is, the gmc generator gives a common mode collector current control of a corresponding TR Q5/Q6, and the static current control is operated to stabilize the output stage gain in such method that the common mode collector current is prevented from being zero or infinite. A stage A3 is a single gain buffer amplifier which gives external load separation to increase an amplifier open loop gain and a DC precision. Each stage uses a symmetrical complementary design.

67. 发明专利

JPH0620113B2 失效
公开(公告)号：JPH0620113B2
公开(公告)日：1994-03-16
申请号：JP2848285
申请日：1985-02-18
申请人： ANALOG DEVICES INC
发明人： PIITAA AARU HOROEI
IPC分类号： H01L21/8234 , H01L21/8249 , H01L27/06 , H01L27/07 , H01L27/088 , H03M1/00

68. 发明专利

JPH04337910A SINGLE POWER SUPPLY CAPACITANCE AND AMPLIFIER FOR INSTRUMENTATION OF SIMPLE GAIN EQUALIZATION 失效
公开(公告)号：JPH04337910A
公开(公告)日：1992-11-25
申请号：JP2930192
申请日：1992-02-17
申请人： ANALOG DEVICES INC
发明人： DEREKU EFU BOWAAZU
IPC分类号： H03F3/347 , H03F3/45 , H03G1/00
摘要： PURPOSE: To provide an instrumentation amplifier that employs three operational amplifiers, each having a feedback circuit from each output to an inverting input. CONSTITUTION: An operational amplifier A4 has a feedback 2 and is connected to an inverting input of an operational amplifier A5, via a gain-setting receiver Rg . An output of an operational amplifier A6 is connected to the inverting input of the operational amplifier A5 via a resistor R5, and a noninverting input of the operational amplifier A6 is connected to any of inputs to the operational amplifier A5. A differential voltage input is connected to noninverting inputs of the operational amplifiers A4, A5, and a reference voltage is given to an inverting input of the operational amplifier A6. This circuit is acted by a single power supply voltage V+, by setting a negative power supply voltage V-together with a reference voltage of a ground level. This circuit has a simple gain equivalence, based on a ratio of a feedback resistance Rf to the gain-setting resistance Rg , with respect to the operational amplifier A5.

69. 发明专利

JPH04227107A WIDE DYNAMIC RANGE TRANSCONDUCTANCE STAGE 失效
公开(公告)号：JPH04227107A
公开(公告)日：1992-08-17
申请号：JP26609491
申请日：1991-10-15
申请人： ANALOG DEVICES INC
发明人： JIEEMUSU AARU BATORAA , DAGURASU ESU SUMISU
IPC分类号： H03F3/343 , H03F3/345 , H03F3/45
摘要： PURPOSE: To obtain large gm in a wide voltage range by constituting two circuit branches through mutual conductance(MC) circuit routes and providing each route with MC larger than that of the other route with respect to a branch within an input signal voltage range. CONSTITUTION: Current sources I3 and I4 supply current for the collector-emitter currents of pnp bipolar Tr Q3 and Q4 . I3 and I4 are connected between a positive voltage bus V+ and the emitters of Tr Q3 and Q4 , and on the other band, a Tr collector is connected with a negative bus V- through resistors R3 and R4 . Output terminals T1 and T2 with respect to a differential current output are connected to the opposite sides of R3 and R4 from the negative bus. An additional circuit route between the positive bus and the resistors R3 and R4 is given by FET J3 and J4 . The source and drain circuit of J3 and J4 is supplied with a current from a current source 15 combined with the positive bus V+. A pair of impedances in the forms of Tr D1 and D2 divide the current from a current source I6 between the emitter circuits of Q3 and Q4 . gm of Q3 and Q4 dominates gm of J3 and J4 .

70. 发明专利

JPH0261822B2 失效
公开(公告)号：JPH0261822B2
公开(公告)日：1990-12-21
申请号：JP12002381
申请日：1981-07-30
申请人： ANALOG DEVICES INC
发明人： ADORIAN HOORU BUROKAU
IPC分类号： H03M1/78 , H03M1/00

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