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61. 发明授权

US11791811B2 Delay circuit and clock error correction device including the same 有权
公开(公告)号：US11791811B2
公开(公告)日：2023-10-17
申请号：US17806827
申请日：2022-06-14
申请人： Samsung Electronics Co., Ltd.
发明人： Hyunsub Rie , Eunseok Shin , Youngdon Choi , Junyoung Park , Hyunyoon Cho , Junghwan Choi
IPC分类号： H03K5/156 , G11C7/22 , H03K5/135 , H03K3/017 , H03K5/00
CPC分类号： H03K5/1565 , G11C7/222 , H03K3/017 , H03K5/135 , H03K2005/00241
摘要： A delay circuit for a clock signal includes a first signal generator, a first inverting circuit, a second signal generator and a second inverting circuit. The first signal generator is configured to generate a plurality of first switching signals based on a delay code. The first inverting circuit includes a plurality of first inverters that are selectively turned on in response to the plurality of first switching signals, respectively, and is configured to adjust a first delay time for both of a first edge and a second edge of the clock signal. The second signal generator is configured to generate a plurality of second switching signals based on a duty code. The second inverting circuit includes a plurality of second pull-up units and a plurality of second pull-down units, respective ones of the plurality of second pull-up units or respective ones of the plurality of second pull-down units are selectively turned on in response to respective ones of the plurality of second switching signals. The second inverting circuit is configured to adjust a second delay time for the first edge, the second edge, or both of the first edge and the second edge of the clock signal.

62. 发明授权

US08994424B2 Distributing multiplexing logic to remove multiplexor latency on the output path for variable clock cycle, delayed signals 有权
标题翻译：分配多路复用逻辑，以消除可变时钟周期，延迟信号的输出路径上的多路复用器延迟
公开(公告)号：US08994424B2
公开(公告)日：2015-03-31
申请号：US13797252
申请日：2013-03-12
申请人： International Business Machines Corporation
发明人： Huu N. Dinh , Robert S. Horton , Bill N. On
IPC分类号： H03L7/00 , H03K5/159
CPC分类号： H03K5/159 , H03K3/037 , H03K19/1737 , H03K2005/00104 , H03K2005/00241
摘要： A logic unit is configured with least one multiplexor distributed along a delay path of a logic unit, wherein each at least one multiplexor is configured to receive two inputs and output one of the two inputs, wherein each at least one multiplexor is configured to select one of the two inputs to control a particular programmable number of clock cycles of delay added to a signal from 1 to N clock cycles. The logic unit is configured with at least two latches distributed along the delay path of the logic unit, wherein each at least one latch is configured to add a clock cycle of delay, wherein a terminating latch from among the at least two latches is configured to output the signal delayed by the particular programmable number of clock cycles.
摘要翻译：逻辑单元配置有沿着逻辑单元的延迟路径分布的至少一个多路复用器，其中每个至少一个复用器被配置为接收两个输入并输出两个输入中的一个，其中每个至少一个多路复用器被配置为选择一个的两个输入来控制特定的可编程数量的延迟的时钟周期，这些时钟周期被添加到从1到N个时钟周期的信号。逻辑单元配置有沿着逻辑单元的延迟路径分布的至少两个锁存器，其中每个至少一个锁存器被配置为增加延迟的时钟周期，其中来自所述至少两个锁存器的终止锁存器被配置为输出延迟特定可编程时钟周期数的信号。

63. 发明授权

US08774305B1 Bit slip circuitry for serial data signals 有权
标题翻译：用于串行数据信号的位滑动电路
公开(公告)号：US08774305B1
公开(公告)日：2014-07-08
申请号：US13908599
申请日：2013-06-03
申请人： Altera Corporation
发明人： Richard Yen-Hsiang Chang
IPC分类号： H04L25/00
CPC分类号： H04L7/02 , H03K5/135 , H03K2005/00241 , H04L25/14
摘要： Circuitry for use in aligning bytes in a serial data signal (e.g., with deserializer circuitry that operates in part in response to a byte rate clock signal) includes a multistage shift register for shifting the serial data signal through a number of stages at least equal to (and in many cases, preferably more than) the number of bits in a byte. The output signal of any shift register stage can be selected as the output of this “bit slipping” circuitry so that any number of bits over a fairly wide range can be “slipped” to produce or help produce appropriately aligned bytes. The disclosed bit slipping circuitry is alternatively or additionally usable in helping to align (“deskew”) two or more serial data signals that are received via separate communication channels.
摘要翻译：用于对齐串行数据信号中的字节的电路（例如，使用部分响应于字节速率时钟信号进行操作的解串器电路）包括多级移位寄存器，用于将串行数据信号移位至少等于（并且在许多情况下，优选大于）一个字节中的比特数。可以选择任何移位寄存器级的输出信号作为该“滑移”电路的输出，使得在相当宽的范围内的任何数量的位可以“滑动”以产生或帮助产生适当对齐的字节。公开的位滑动电路可选地或另外可用于帮助对齐（“偏斜”）两个或更多个经由分离的通信信道接收的串行数据信号。

64. 发明申请

US20140139276A1 MATRIX PHASE DETECTOR 有权
标题翻译：矩阵相位检测器
公开(公告)号：US20140139276A1
公开(公告)日：2014-05-22
申请号：US13688175
申请日：2012-11-28
申请人： NVIDIA CORPORATION
发明人： William J. Dally
IPC分类号： H03L7/00
CPC分类号： H03L7/00 , G06F1/10 , H03K5/00 , H03K2005/00104 , H03K2005/00241
摘要： A method and a system are provided for clock phase detection. A first set of delayed versions of a first clock signal is generated and a second set of delayed versions of a second clock signal is generated. The second set of delayed versions of the second clock signal is sampled using the first set of delayed versions of the first clock signal to produce an array of clock samples in a domain corresponding to the first clock signal. At least one edge indication is located within the array of clock samples.
摘要翻译：提供了一种用于时钟相位检测的方法和系统。生成第一时钟信号的第一组延迟版本，并且产生第二组第二时钟信号的延迟版本。使用第一时钟信号的第一组延迟版本对第二时钟信号的第二组延迟版本进行采样，以产生与第一时钟信号对应的域中的时钟采样阵列。至少一个边缘指示位于时钟采样阵列内。

65. 发明授权

US08477897B1 Bit slip circuitry for serial data signals 有权
标题翻译：用于串行数据信号的位滑动电路
公开(公告)号：US08477897B1
公开(公告)日：2013-07-02
申请号：US12283617
申请日：2008-09-12
申请人： Richard Yen-Hsiang Chang
发明人： Richard Yen-Hsiang Chang
IPC分类号： H04L25/00
CPC分类号： H04L7/02 , H03K5/135 , H03K2005/00241 , H04L25/14
摘要： Circuitry for use in aligning bytes in a serial data signal (e.g., with deserializer circuitry that operates in part in response to a byte rate clock signal) includes a multistage shift register for shifting the serial data signal through a number of stages at least equal to (and in many cases, preferably more than) the number of bits in a byte. The output signal of any shift register stage can be selected as the output of this “bit slipping” circuitry so that any number of bits over a fairly wide range can be “slipped” to produce or help produce appropriately aligned bytes. The disclosed bit slipping circuitry is alternatively or additionally usable in helping to align (“deskew”) two or more serial data signals that are received via separate communication channels.
摘要翻译：用于对齐串行数据信号中的字节的电路（例如，使用部分响应于字节速率时钟信号进行操作的解串器电路）包括多级移位寄存器，用于将串行数据信号移位至少等于（并且在许多情况下，优选大于）一个字节中的比特数。可以选择任何移位寄存器级的输出信号作为该“滑移”电路的输出，使得在相当宽的范围内的任何数量的位可以“滑动”以产生或帮助产生适当对齐的字节。公开的位滑动电路可选地或另外可用于帮助对齐（“偏斜”）两个或更多个经由分离的通信信道接收的串行数据信号。

66. 发明申请

US20130082755A1 FILTERING CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT HAVING THE SAME 有权
标题翻译：滤波电路和具有该电路的半导体集成电路
公开(公告)号：US20130082755A1
公开(公告)日：2013-04-04
申请号：US13302167
申请日：2011-11-22
申请人： Hye-Young LEE , Yong-Mi KIM
发明人： Hye-Young LEE , Yong-Mi KIM
IPC分类号： H03L7/06 , H03K5/00
CPC分类号： H03L7/0814 , H03K2005/00241 , H03L7/0816 , H03L7/093
摘要： A filtering circuit includes jitter determination reference control unit configured to determine a jitter determination reference in correspondence to an operation mode and output a control signal in response to the jitter determination reference, and a filtering unit configured to set the jitter determination reference in response to the control signal and determine whether an input signal is maintained during a sample period in response to the set jitter determination reference.
摘要翻译：滤波电路包括：抖动判定基准控制部，被配置为根据操作模式确定抖动判定基准，响应抖动判定基准输出控制信号;滤波部，被配置为响应于抖动判定基准控制信号，并且响应于所设置的抖动判定参考，确定在采样周期期间是否维持输入信号。

67. 发明授权

US07642865B2 System and method for multiple-phase clock generation 有权
标题翻译：用于多相时钟生成的系统和方法
公开(公告)号：US07642865B2
公开(公告)日：2010-01-05
申请号：US11616742
申请日：2006-12-27
申请人： Tanmoy Sen , Anand Kumar , Deependra Kumar Jain
发明人： Tanmoy Sen , Anand Kumar , Deependra Kumar Jain
IPC分类号： H03B27/00
CPC分类号： H03K3/0315 , H03K3/03 , H03K5/15013 , H03K5/15026 , H03K5/1506 , H03K2005/00241 , H03K2005/00247 , H03L7/095 , H03L7/0995 , Y10S331/02
摘要： A multiple phase clock circuit includes a multiple stage voltage controlled oscillator (VCO) and multiple clock dividers. The VCO is operative at a frequency ‘N’ times higher than the required output frequency and generates ‘M’ equally spaced outputs having different phases but same frequency which are sent to multiple clock dividers. A modified Johnson counter is used as a clock divider. Each counter divides the frequency of the clock signal by N. As a result, each of the M outputs of the VCO are divided into N outputs, thereby making a total of ‘M×N’ equally spaced outputs. These output clock pulses have same frequency but different phases. A sequential logic is provided within the device for enabling the Johnson counters as soon as the VCO starts giving output, thus maintaining the sequence of the output of the Johnson counters.
摘要翻译：多相时钟电路包括多级压控振荡器（VCO）和多个时钟分频器。 VCO的工作频率高于所需输出频率的“N”倍，并产生具有不同相位但相同频率的“M”等间距输出，发送到多个时钟分频器。修改后的约翰逊计数器用作时钟分频器。每个计数器将时钟信号的频率除以N.结果，VCO的M个输出中的每一个被分成N个输出，从而形成总共“M×N”个等间隔的输出。这些输出时钟脉冲具有相同的频率但不同的相位。在该装置内提供一个顺序逻辑，用于一旦VCO开始输出输出就能使约翰逊计数器得以实现，从而保持约翰逊计数器的输出顺序。

68. 发明申请

US20090146716A1 Timing control circuit, timing generation system, timing control method and semiconductor memory device 有权
标题翻译：定时控制电路，定时生成系统，定时控制方法和半导体存储器件
公开(公告)号：US20090146716A1
公开(公告)日：2009-06-11
申请号：US12314207
申请日：2008-12-05
申请人： Akira Ide , Yasuhiro Takai , Akira Kotabe , Tomonori Sekiguchi , Riichiro Takemura , Satoru Akiyama
发明人： Akira Ide , Yasuhiro Takai , Akira Kotabe , Tomonori Sekiguchi , Riichiro Takemura , Satoru Akiyama
IPC分类号： H03H11/26
CPC分类号： G11C11/4076 , G11C7/04 , G11C7/1072 , G11C7/222 , G11C19/00 , H03K5/131 , H03K5/14 , H03K2005/00058 , H03K2005/00241
摘要： A timing control circuit DLY1 receives clock signal CKa with period T1 and activation signal ACT and outputs fine timing signal FT with delay of m*T1+tda measured from the clock signal where m denotes a non-negative integer and tda denotes delay in the analog delay element. The timing control circuit DLY1 comprises a coarse delay circuit CD and a fine delay circuit FD. The coarse delay circuit CD comprises a counter for counting a rising edge of the clock signal CKa after receiving activation signal ACT and outputs coarse timing signal CT with delay of m*T1 measured from a rising edge of the clock signal CKa. The fine delay circuit FD comprises a plurality of analog delay elements and outputs fine delay timing signal FT with delay of tda measured from the coarse timing signal CT. Variation in delay of timing signal is reduced.
摘要翻译：定时控制电路DLY1接收具有周期T1和激活信号ACT的时钟信号CKa，并从m表示非负整数的时钟信号输出延迟m * T1 + tda的精确定时信号FT，并且tda表示模拟延迟元件定时控制电路DLY1包括粗延迟电路CD和精细延迟电路FD。粗延迟电路CD包括用于在接收到激活信号ACT之后对时钟信号CKa的上升沿进行计数的计数器，并输出从时钟信号CKa的上升沿测量的具有延迟m * T1的粗定时信号CT。精细延迟电路FD包括多个模拟延迟元件，并输出从粗定时信号CT测得的具有延迟tda的精细延迟定时信号FT。定时信号延迟的变化减小。

69. 发明申请

US20080197931A1 OSCILLATOR 审中-公开
标题翻译：振荡器
公开(公告)号：US20080197931A1
公开(公告)日：2008-08-21
申请号：US12031796
申请日：2008-02-15
申请人： Yosuke Ueno
发明人： Yosuke Ueno
IPC分类号： H03K3/03
CPC分类号： H03K3/0315 , H03K5/133 , H03K2005/00241 , H03L7/0995
摘要： The present invention provides an oscillation circuit including: a plurality of multi-stage inverter rings each having an odd number of inverters connected to each other in cascade to form a ring through the same odd number of nodes on the ring; an inverter group for connecting each one of the nodes on any specific one of the multi-stage inverter rings to a counterpart one of the nodes on another one of the multi-stage inverter rings so as to join the specific and other multi-stage inverter rings to each other in order to shift the phases of generated oscillation signals from each other by a fixed difference: and a current source connected to the inverters of the multi-stage inverter rings and the inverters of the inverter group.
摘要翻译：本发明提供一种振荡电路，包括：多个多级反相器环，每个具有奇数个反相器级联的反相器，以通过环上相同奇数个节点形成环; 用于将多级变换器环中的任何特定一个节点上的每个节点连接到多级变换器环中的另一个上的节点中的一个节点的逆变器组，以便连接特定的和其他多级逆变器相互振荡以使产生的振荡信号的相位相互偏移一个固定的差异：连接到多级逆变器的反相器的电流源和逆变器组的反相器。

70. 发明申请

US20070030045A1 Delay circuit and delay synchronization loop device 有权
标题翻译：延迟电路和延迟同步环路装置
公开(公告)号：US20070030045A1
公开(公告)日：2007-02-08
申请号：US11544598
申请日：2006-10-10
申请人： Yasuhiro Takai , Shotaro Kobayashi
发明人： Yasuhiro Takai , Shotaro Kobayashi
IPC分类号： H03H11/26
CPC分类号： H03K5/133 , H03K5/135 , H03K2005/00058 , H03K2005/00241 , H03K2005/00247 , H03K2005/00273 , H03L7/0814 , H03L7/087
摘要： A delay circuit includes a first delay line circuit having a plurality of stages of delay units, a second delay line circuit having a plurality of stages of delay units, a plurality of transfer circuits provided in association with respective stages of the delay units of the first delay line circuit, the transfer circuits controlling the transfer of the outputs of the delay units of the first delay line circuit to associated stages of the delay units of the second delay line circuit. The delay units of respective stages of the first delay line circuit inverting input signals. Each stage delay unit of the second delay line circuit includes a logic circuit receiving an output signal of the transfer circuit associated with the delay unit in question and an output signal of a preceding stage to send an output signal to a following stage. The duty ratio is rendered variable by independently selecting the rising edge of the input signal and a propagation path of the falling edge.
摘要翻译：延迟电路包括具有多级延迟单元的第一延迟线电路，具有多级延迟单元的第二延迟线电路，与第一延迟单元的延迟单元的相应级相关联地设置的多个传输电路延迟线电路，所述传送电路控制第一延迟线电路的延迟单元的输出到第二延迟线电路的延迟单元的相关级的传送。第一延迟线电路各级的延迟单元反相输入信号。第二延迟线电路的各级延迟单元包括接收与所讨论的延迟单元相关联的传送电路的输出信号的逻辑电路和将前一级的输出信号发送到后级的输出信号。通过独立地选择输入信号的上升沿和下降沿的传播路径，使占空比变化。

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