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71. 发明申请

WO03005447A2 STRUCTURE AND METHOD OF FABRICATING EMBEDDED VERTICAL DRAM ARRAYS WITH SILICIDED BITLINE AND POLYSILICON INTERCONNECT 审中-公开
标题翻译：硅化双线和多晶硅互连嵌入式垂直DRAM阵列的结构和制作方法
公开(公告)号：WO03005447A2
公开(公告)日：2003-01-16
申请号：PCT/GB0202961
申请日：2002-06-27
申请人： IBM , IBM UK , INFINEON TECHNOLOGIES AG
发明人： DIVAKARUNI RAMACHANDRA , GRUENING ULRIKE , MANDELMAN JACK , NESBIT LARRY , RADENS CARL
IPC分类号： H01L21/8234 , H01L21/8242 , H01L27/088 , H01L27/108
CPC分类号： H01L27/10891 , H01L27/10864 , H01L27/10876 , H01L27/10894
摘要： A structure and process for fabricating embedded vertical DRAM cells includes fabricating vertical MOSFET DRAM cells with silicided polysilicon layers in the array regions, the landing pad and/or interconnect structures, the support source and drain regions and/or the gate stack. The process eliminates the need for a M0 metallization layer.
摘要翻译：用于制造嵌入式垂直DRAM单元的结构和工艺包括在阵列区域，连接焊盘和/或互连结构，支撑源极和漏极区域和/或栅极堆叠中制造具有硅化多晶硅层的垂直MOSFET DRAM单元。该工艺消除了对M0金属化层的需求。

72. 发明申请

WO0225730A8 SELF ALIGNED TRENCH AND METHOD OF FORMING THE SAME 审中-公开
标题翻译：自对准TRENCH及其形成方法
公开(公告)号：WO0225730A8
公开(公告)日：2002-12-27
申请号：PCT/US0142263
申请日：2001-09-24
申请人： INFINEON TECHNOLOGIES CORP , IBM
发明人： KUNKEL GERHARD , BUTT SHAHID , DIVAKARUNI RAMACHANDRAN , REITH ARMIN M , NAEEM MUNIR D
IPC分类号： H01L21/8242
CPC分类号： H01L27/10864 , H01L27/1087 , H01L27/10891
摘要： A method of forming a trench can be used in the fabrication of dynamic random access memory (DRAM) cells. In one aspect, a first layer of a first material (e.g., polysilicon) (104) is formed over a semiconductor region (e.g., a silicon substrate) (100). The first layer is patterned to remove portions of the first material. A second material (e.g., oxide) (112, 120) can then be deposited to fill the portions where the first material was removed. After removing the remaining portions of the first layer of first material, a trench (122) can be etched in the semiconductor region. The trench would be substantially aligned to the second material.
摘要翻译：形成沟槽的方法可用于制造动态随机存取存储器（DRAM）单元。在一个方面，在半导体区域（例如，硅衬底）（100）上形成第一材料（例如，多晶硅）（104）的第一层。图案化第一层以去除第一材料的部分。然后可以沉积第二材料（例如氧化物）（112,120）以填充去除第一材料的部分。在去除第一材料的第一层的剩余部分之后，可以在半导体区域中蚀刻沟槽（122）。沟槽将基本上对准第二材料。

73. 发明申请

WO0229889A2 AN INTEGRATED CIRCUIT COMPRISING A SELF ALIGNED TRENCH, AND METHOD OF FORMING THEREOF 审中-公开
标题翻译：包含自对准TRENCH的集成电路及其形成方法
公开(公告)号：WO0229889A2
公开(公告)日：2002-04-11
申请号：PCT/US0129194
申请日：2001-09-19
申请人： INFINEON TECHNOLOGIES CORP
发明人： SHEN HUA
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10864 , H01L27/10876 , H01L27/10885
摘要： An integrated circuit comprising a vertically oriented device formed with a substantially SELF ALIGNED process, in which the trench, active area (e.g., 128, 228), and gate (e.g., 132, 232) of a DRAM cell may be formed using a minimal number of masks and lithographic steps. Using this process, a DRAM cell comprising a vertical transistor and a buried word line (e.g., 132, 232) may be formed. A gate dielectric (e.g., 130, 230) may be disposed adjacent the active area, and the portion of the buried word line adjacent the gate dielectric may function as the vertically oriented gate for the vertical transistor. The DRAM memory cell may comprise one of a variety of capacitors, such a trench capacitor underlying the vertical transistor, or a stack capacitor (e.g., 241) overlying the vertical transistor. When a stack capacitor is used, a buried bit line (e.g., 208) underlying the vertical transistor may also be used.
摘要翻译：一种集成电路，其包括以基本上自对准的方法形成的垂直取向的器件，其中DRAM单元的沟槽，有源区（例如，128,228）和栅极（例如，132,232）可以使用最小的掩模数和光刻步骤。使用该过程，可以形成包括垂直晶体管和掩埋字线（例如，132,232）的DRAM单元。栅电介质（例如，130,230）可以邻近有源区设置，并且与栅极电介质相邻的掩埋字线的部分可以用作垂直晶体管的垂直取向的栅极。 DRAM存储单元可以包括各种电容器中的一个，垂直晶体管下面的这种沟槽电容器，或叠加在垂直晶体管上的堆叠电容器（例如241）。当使用堆叠电容器时，也可以使用垂直晶体管下面的掩埋位线（例如208）。

74. 发明申请

WO2005069372A1 CARBON NANOTUBE CONDUCTOR FOR TRENCH CAPACITORS 审中-公开
标题翻译：用于TRENCH电容器的碳纳米管导体
公开(公告)号：WO2005069372A1
公开(公告)日：2005-07-28
申请号：PCT/US2003/040295
申请日：2003-12-18
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , FURUKAWA, Toshiharu , HAKEY, Mark, C. , HOLMES, Steven, J. , HORAK, David, V. , KOBURGER, Charles, W., III , NESBIT, Larry, A.
发明人： FURUKAWA, Toshiharu , HAKEY, Mark, C. , HOLMES, Steven, J. , HORAK, David, V. , KOBURGER, Charles, W., III , NESBIT, Larry, A.
IPC分类号： H01L27/108
CPC分类号： H01L27/10864 , B82Y10/00 , H01L27/10861 , Y10S977/936 , Y10S977/943 , Y10S977/948
摘要： A trench-type storage device includes a trench in a substrate (100), with bundles of carbon nanotubes (202) lining the trench and a trench conductor (300) filling the trench. A trench dielectric (200) may be formed between the carbon nanotubes and the sidewall of the trench. The bundles of carbon nanotubes form an open cylinder structure lining the trench. The device is formed by providing a carbon nanotube catalyst structure on the substrate and patterning the trench in the substrate; the carbon nanotubes are then grown down into the trench to line the trench with the carbon nanotube bundles, after which the trench is filled with the trench conductor.
摘要翻译：沟槽型存储装置包括在衬底（100）中的沟槽，具有衬在沟槽上的碳纳米管（202）的束和填充沟槽的沟槽导体（300）。可以在碳纳米管和沟槽的侧壁之间形成沟槽电介质（200）。碳纳米管束形成在沟槽内衬的开放圆筒结构。该器件通过在衬底上提供碳纳米管催化剂结构并图案化衬底中的沟槽而形成; 然后将碳纳米管向下生长到沟槽中以与碳纳米管束对准沟槽，然后用沟槽导体填充沟槽。

75. 发明申请

WO2004040644A3 MEMORY CELL, MEMORY CELL ARRANGEMENT, STRUCTURING ARRANGEMENT AND METHOD FOR PRODUCTION OF A MEMORY CELL 审中-公开
标题翻译：存储单元中，存储器单元装置，纹理安排及其制造方法的存储单元
公开(公告)号：WO2004040644A3
公开(公告)日：2004-08-12
申请号：PCT/DE0303589
申请日：2003-10-29
申请人： INFINEON TECHNOLOGIES AG , GRAHAM ANDREW , HOFMANN FRANZ , HOENLEIN WOLFGANG , KRETZ JOHANNES , KREUPL FRANZ , LANDGRAF ERHARD , LUYKEN RICHARD JOHANNES , ROESNER WOLFGANG , SCHULZ THOMAS , SPECHT MICHAEL
发明人： GRAHAM ANDREW , HOFMANN FRANZ , HOENLEIN WOLFGANG , KRETZ JOHANNES , KREUPL FRANZ , LANDGRAF ERHARD , LUYKEN RICHARD JOHANNES , ROESNER WOLFGANG , SCHULZ THOMAS , SPECHT MICHAEL
IPC分类号： G11C13/02 , H01L21/8242 , H01L27/108 , H01L51/00 , H01L51/05 , H01L51/30 , H01L21/8239 , H01L51/20
CPC分类号： G11C13/025 , B82Y10/00 , G11C13/0033 , G11C2213/16 , H01L27/10841 , H01L27/10864 , H01L27/10876 , H01L27/283 , H01L51/0048 , H01L51/0052 , H01L51/0512 , H01L51/057
摘要： The invention relates to a memory cell, memory cell arrangement, structuring arrangement and method for production of a memory cell. The memory cell has a vertical gate transistor and a memory capacitor, whereby the vertical gate transistor comprises a semiconducting nanostructure, grown on at least part of the memory capacitor.
摘要翻译：本发明涉及一种存储器单元，存储器单元阵列，纹理化装置和一种用于制造存储器单元的方法。该存储单元有一个垂直的开关晶体管和存储电容器，所述具有半导体纳米结构垂直开关晶体管上生长至少存储电容器的一部分。

76. 发明申请

WO2004040644A2 SPEICHERZELLE, SPEICHERZELLEN-ANORDNUNG, STRUKTURIER-ANORDNUNG UND VERFAHREN ZUM HERSTELLEN EINER SPEICHERZELLE 审中-公开
标题翻译：存储器单元，存储器单元布置，结构布置和用于产生存储器单元的方法
公开(公告)号：WO2004040644A2
公开(公告)日：2004-05-13
申请号：PCT/DE2003/003589
申请日：2003-10-29
申请人： INFINEON TECHNOLOGIES AG , GRAHAM, Andrew , HOFMANN, Franz , HÖNLEIN, Wolfgang , KRETZ, Johannes , KREUPL, Franz , LANDGRAF, Erhard , LUYKEN, Richard, Johannes , RÖSNER, Wolfgang , SCHULZ, Thomas , SPECHT, Michael
发明人： GRAHAM, Andrew , HOFMANN, Franz , HÖNLEIN, Wolfgang , KRETZ, Johannes , KREUPL, Franz , LANDGRAF, Erhard , LUYKEN, Richard, Johannes , RÖSNER, Wolfgang , SCHULZ, Thomas , SPECHT, Michael
IPC分类号： H01L21/8239
CPC分类号： G11C13/025 , B82Y10/00 , G11C13/0033 , G11C2213/16 , H01L27/10841 , H01L27/10864 , H01L27/10876 , H01L27/283 , H01L51/0048 , H01L51/0052 , H01L51/0512 , H01L51/057
摘要： Die Erfindung betrifft eine Speicherzelle, eine Speicherzellen-Anordnung, eine Strukturier-Anordnung und ein Verfahren zum Herstellen einer Speicherzelle. Die Speicherzelle hat einen Vertikal-Schalt-Transistor und einen Speicher-Kondensator, wobei der Vertikal-Schalt-Transistor eine halbleitende Nanostruktur aufweist, die auf zumindest einem Teil des Speicher-Kondensators aufgewachsen ist.
摘要翻译：存储器单元，存储器单元布置，构造布置以及用于制造存储器单元的方法技术领域本发明涉及一种存储器单元，存储器单元具有垂直开关晶体管和存储电容器，垂直开关晶体管具有在至少部分存储电容器上生长的半导体纳米结构

77. 发明申请

WO0249100A3 METHOD OF FORMING VERTICAL TRANSISTOR GATE FOR TRENCH CAPACITOR DRAM CELL 审中-公开
标题翻译：形成用于TRENCH电容器DRAM单元的垂直晶体闸门的方法
公开(公告)号：WO0249100A3
公开(公告)日：2003-04-03
申请号：PCT/US0143905
申请日：2001-11-14
申请人： INFINEON TECHNOLOGIES CORP
发明人： WEIS ROLF
IPC分类号： H01L21/8242
CPC分类号： H01L27/10864 , H01L27/10876 , H01L27/10891
摘要： A device and method for fabricating a gate structure are disclosed. A first conductive material (42) is deposited in a trench (14) formed in a substrate (12) and the first conductive material is recessed to a level below a top surface of the substrate in the trench. A dielectric layer (58) is conformally deposited in contact with the first conductive material in the trench and in contact with sidewalls of the trench. A hole is formed in the dielectric layer to expose the first conductive layer, and the hole is filled with a conductive material (62). A gate stack (60) is formed over the trench such that an electrical connection is made to the first conductive layer in the trench by employing the conductive material through the dielectric layer.
摘要翻译：公开了一种用于制造栅极结构的器件和方法。第一导电材料（42）沉积在形成在衬底（12）中的沟槽（14）中，并且第一导电材料凹陷到沟槽中的衬底顶表面以下的水平。电介质层（58）与沟槽中的第一导电材料共形沉积成与沟槽的侧壁接触。在电介质层中形成一个孔以露出第一导电层，并且该孔填充有导电材料（62）。在沟槽上方形成栅极叠层（60），使得通过使用导电材料通过电介质层与沟槽中的第一导电层形成电连接。

78. 发明申请

WO02029888A2 AN EXTENDIBLE PROCESS FOR IMPROVED TOP OXIDE LAYER FOR DRAM ARRAY AND THE GATE INTERCONNECTS WHILE PROVIDING SELF-ALIGNED GATE CONTACTS 审中-公开
标题翻译：用于DRAM阵列的改进顶氧化物层的可扩展过程和提供自对准门控接点的门控互连
公开(公告)号：WO02029888A2
公开(公告)日：2002-04-11
申请号：PCT/US2001/027366
申请日：2001-08-31
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10864 , H01L27/10891
摘要： A Top Oxide Method is used to form an oxide layer over an array of vertical transistors as in a trench dynamic random access memory (DRAM) array with vertically stacked access metal oxide semiconductor field effect transistors (MOSFETs). The Top Oxide is formed by first forming the vertical devices with the pad nitride remaining in place. Once the devices have been formed and the gate polysilicon has been planarized down to the surface of the pad nitride, the pad nitride is stripped away leaving the tops of the gate polysilicon plugs extending above the active silicon surface. This pattern of polysilicon plugs defines the pattern over which the Top Oxide is deposited. The deposited Top Oxide fills the regions between and on top of the polysilicon plugs. The Top Oxide is than planarized back to the tops of the polysilicon plugs so contacts can be made between the passing interconnects and the gates of the vertical devices. The Top Oxide layer serves to separate the passing interconnects from the active silicon thereby reducing capacitive coupling between the two levels and providing a robust etch-stop layer for the reactive ion etch (RIE) patterning of the subsequent interconnect level.
摘要翻译：如在具有垂直堆叠的存取金属氧化物半导体场效应晶体管（MOSFET）的沟槽动态随机存取存储器（DRAM）阵列中，顶部氧化物方法用于在垂直晶体管阵列上形成氧化物层。顶部氧化物通过首先形成垂直装置而形成，其中衬垫氮化物保持就位。一旦器件已经形成并且栅极多晶硅已经被平坦化到衬底氮化物的表面之下，衬垫氮化物被剥离掉，留下栅极多晶硅插塞的顶部延伸到活性硅表面之上。这种多晶硅插塞的图形定义了顶部氧化物沉积的图案。沉积的顶部氧化物填充多晶硅插塞之间和之上的区域。顶部氧化物被平坦化回到多晶硅插塞的顶部，因此可以在通过的互连件和垂直装置的栅极之间形成接触。顶部氧化物层用于将通过的互连与有源硅分离，从而减少两个电平之间的电容耦合，并提供用于后续互连电平的反应离子蚀刻（RIE）图案化的鲁棒蚀刻停止层。

79. 发明申请

WO0211200A8 SEMICONDUCTOR MEMORY CELL ARRANGEMENT AND METHOD FOR PRODUCING THE SAME 审中-公开
标题翻译：半导体存储器单元装置和方法及其
公开(公告)号：WO0211200A8
公开(公告)日：2002-04-11
申请号：PCT/DE0102798
申请日：2001-07-23
申请人： INFINEON TECHNOLOGIES AG , GOEBEL BERND , LUETZEN JOERN , POPP MARTIN , SEIDL HARALD
发明人： GOEBEL BERND , LUETZEN JOERN , POPP MARTIN , SEIDL HARALD
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10864
摘要： The invention relates to a semiconductor memory cell arrangement comprising dynamic memory cells (10) which each have a trench capacitor (1) and a vertical selection transistor (2). Said vertical selection transistor (2) is situated essentially above the trench capacitor (1) and has a series of layers which is offset from the inner electrode of the trench capacitor (1) and which is connected to said inner electrode (11) of the trench capacitor (1). An active intermediate layer (22) is completely surrounded by an insulator layer (24) and a gate electrode layer (25) which is connected to a word line (7). The dynamic memory cells (10) are arranged in the form of a matrix, the trench capacitors (1) and the corresponding vertical selection transistors (2) of the dynamic memory cells (10) succeeding each other in a line and/or column sequence, respectively.
摘要翻译：具有动态存储单元的半导体存储器单元阵列（10），每一个都具有严重的电容器（1）和一个verikalen选择晶体管（2），其特征在于，垂直选择晶体管（2）基本上高于WOM严重电容器（1）被布置和相对的内部电极被严重电容器（1）与一个布置成与严重电容器（1），其特征在于，有源中间层（22）被封闭具有完全的绝缘体层（24）和栅电极层（25）的内电极（11）偏移的层序列 Worleitung（7）连接，其中，所述动态存储单元（10）被布置成矩阵，和坟墓电容器（1）和相关联的垂直选择Transistore（2）的动态存储器单元（10），每行和/或列状连续的。

80. 发明申请

WO02011200A1 SEMICONDUCTOR MEMORY CELL ARRANGEMENT AND METHOD FOR PRODUCING THE SAME 审中-公开
标题翻译：半导体存储器单元布置及其制造方法
公开(公告)号：WO02011200A1
公开(公告)日：2002-02-07
申请号：PCT/DE2001/002798
申请日：2001-07-23
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10864
摘要： The invention relates to a semiconductor memory cell arrangement comprising dynamic memory cells (10) which each have a trench capacitor (1) and a vertical selection transistor (2). Said vertical selection transistor (2) is situated essentially above the trench capacitor (1) and has a series of layers which is offset from the inner electrode of the trench capacitor (1) and which is connected to said inner electrode (11) of the trench capacitor (1). An active intermediate layer (22) is completely surrounded by an insulator layer (24) and a gate electrode layer (25) which is connected to a word line (7). The dynamic memory cells (10) are arranged in the form of a matrix, the trench capacitors (1) and the corresponding vertical selection transistors (2) of the dynamic memory cells (10) succeeding each other in a line and/or column sequence, respectively.
摘要翻译：具有动态存储单元的半导体存储器单元阵列（10），每一个都具有严重的电容器（1）和一个verikalen选择晶体管（2），其特征在于，垂直选择晶体管（2）基本上高于WOM严重电容器（1）被布置和相对的内部电极被严重电容器（1）与一个布置成与严重电容器（1），其特征在于，有源中间层（22）被封闭具有完全的绝缘体层（24）和栅电极层（25）的内电极（11）偏移的层序列 Worleitung（7）连接，其中，所述动态存储单元（10）被布置成矩阵，和坟墓电容器（1）和相关联的垂直选择Transistore（2）的动态存储器单元（10），每行和/或列状连续的。

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