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71. 发明公开

EP2650905A3 Methods and devices for fabricating and assembling printable semiconductor elements 审中-公开
标题翻译：的方法和设备用于制造和装配可印刷的半导体元件
公开(公告)号：EP2650905A3
公开(公告)日：2014-10-01
申请号：EP13003426.7
申请日：2005-06-02
申请人： The Board of Trustees of the University of Illinois
发明人： Nuzzo, Ralph G. , Rogers, John, A. , Menard, Etienne , Lee, Keon Jae , Khang, Dahl-Young , Sun, Yugang , Meitl, Matthew , Zhu, Zhengtao
IPC分类号： H01L21/30 , H01L21/326 , H01L21/4763 , H01L23/48 , H01L27/01 , H01L29/06 , H01L29/08 , H01L21/02
CPC分类号： H01L29/76 , B81C2201/0185 , B82Y10/00 , H01L21/02521 , H01L21/02603 , H01L21/02628 , H01L21/308 , H01L21/322 , H01L21/6835 , H01L23/02 , H01L24/03 , H01L24/05 , H01L24/08 , H01L24/29 , H01L24/32 , H01L24/80 , H01L24/83 , H01L24/94 , H01L24/97 , H01L25/0753 , H01L27/1285 , H01L27/1292 , H01L29/04 , H01L29/06 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/068 , H01L29/12 , H01L29/78603 , H01L29/78681 , H01L29/78696 , H01L31/0392 , H01L31/03926 , H01L31/1804 , H01L31/1864 , H01L31/1896 , H01L33/007 , H01L33/0079 , H01L33/32 , H01L2221/68368 , H01L2221/68381 , H01L2224/03 , H01L2224/0332 , H01L2224/0345 , H01L2224/03614 , H01L2224/0362 , H01L2224/05073 , H01L2224/05082 , H01L2224/05124 , H01L2224/05144 , H01L2224/05155 , H01L2224/05166 , H01L2224/05552 , H01L2224/05553 , H01L2224/05554 , H01L2224/05555 , H01L2224/05644 , H01L2224/05666 , H01L2224/08225 , H01L2224/2919 , H01L2224/32225 , H01L2224/80 , H01L2224/80006 , H01L2224/80121 , H01L2224/80862 , H01L2224/80895 , H01L2224/83 , H01L2224/83005 , H01L2224/83121 , H01L2224/83192 , H01L2224/83193 , H01L2224/8385 , H01L2224/83862 , H01L2224/9202 , H01L2224/94 , H01L2224/95 , H01L2224/97 , H01L2924/00012 , H01L2924/01032 , H01L2924/0665 , H01L2924/10253 , H01L2924/10329 , H01L2924/12032 , H01L2924/12036 , H01L2924/12041 , H01L2924/12042 , H01L2924/12043 , H01L2924/12044 , H01L2924/1305 , H01L2924/1306 , H01L2924/13063 , H01L2924/13091 , H01L2924/14 , H01L2924/1461 , H01L2924/15159 , H01L2924/15162 , H01L2924/15788 , H01L2924/1579 , Y02E10/547 , Y02P70/521 , Y10S977/707 , Y10S977/724 , H01L2924/00014 , H01L2924/00
摘要： The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations.

72. 发明公开

EP2447993A4 ELECTRONIC MODULE AND PACKAGING METHOD THEREOF 审中-公开
标题翻译： ELEKTRONISCHES MODUL UND VERPACKUNGSVERFAHRENDAFÜR
公开(公告)号：EP2447993A4
公开(公告)日：2014-10-01
申请号：EP10809474
申请日：2010-05-07
申请人： HUAWEI DEVICE CO LTD
发明人： QIAO JITAO
IPC分类号： H01L23/48 , H01L23/12 , H01L23/13 , H01L25/00
CPC分类号： H01L23/49805 , H01L23/13 , H01L25/105 , H01L25/16 , H01L2924/15162 , H01L2924/15323 , H05K1/141 , H05K3/3436 , H05K3/3442 , H05K2201/09136 , H05K2201/10727
摘要： Embodiments of the present invention provide an electronic module and a packaging structure of the electronic module. The electronic module includes: a substrate; at least one electronic component, arranged on an upper surface of the substrate; and a first conductive part and a second conductive part, configured to connect the electronic module to an external printed circuit board; the first conductive part is arranged at a lower surface of the substrate and is electrically connected to the electronic component; and the second conductive part is arranged across a lateral surface of the substrate and the lower surface of the substrate. The electronic module is packaged with the printed circuit board by arranging a second conductive part across the lateral surface of the substrate and the lower surface of the substrate, which improves the quality of welding between the electronic module and the printed circuit board.
摘要翻译：本发明的实施例提供了电子模块和电子模块的包装结构。电子模块包括：基板; 至少一个电子部件，布置在所述基板的上表面上; 以及第一导电部和第二导电部，被配置为将所述电子模块连接到外部印刷电路板; 第一导电部件布置在基板的下表面处并且电连接到电子部件; 并且第二导电部分跨越衬底的侧表面和衬底的下表面布置。电子模块通过在基板的侧表面和基板的下表面上布置第二导电部件而与印刷电路板封装，这提高了电子模块和印刷电路板之间的焊接质量。

73. 发明公开

EP1019960A4 BALL GRID ARRAY SEMICONDUCTOR PACKAGE AND METHOD FOR MAKING THE SAME 失效
标题翻译： HERBLEITER-KUGELMATRIXPACKUNG UND HERSTELLUNGSVERFAHRENDAFÜR
公开(公告)号：EP1019960A4
公开(公告)日：2002-03-20
申请号：EP98920999
申请日：1998-05-05
申请人： SIGNETICS KP CO LTD
发明人： KARNEZOS MARCOS
IPC分类号： H01L23/12 , H01L23/31 , H01L23/36 , H01L23/48 , H01L23/544 , H05K1/02 , H05K3/34 , H01L23/498 , H01L23/52 , H01L29/40
CPC分类号： H01L24/49 , H01L23/3128 , H01L23/36 , H01L23/544 , H01L24/48 , H01L24/73 , H01L2223/54473 , H01L2223/54486 , H01L2224/16 , H01L2224/16225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/48465 , H01L2224/49109 , H01L2224/73253 , H01L2224/73265 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01021 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01042 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/07802 , H01L2924/14 , H01L2924/15153 , H01L2924/15157 , H01L2924/15162 , H01L2924/15165 , H01L2924/1517 , H01L2924/15311 , H01L2924/1532 , H01L2924/181 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H05K1/0219 , H05K3/3436 , H01L2924/00 , H01L2924/00012 , H01L2224/45099
摘要： Disclosed is a semiconductor package that includes a heat spreader (110). The package further includes a ground plane (160) having a first side that is attached to the heat spreader with an elctrically insulating adhesive (127). The ground plane has a first aperture (166a) defining a path to a surface of the heat spreader tthat is configured to receive a semiconductor die. An interconnect substrate (125) is adhesively attached to the ground plane, and the interconnect substrate has a second apperture (154) over the first aperture of the ground plane. Preferably, the interconnect substrate has a plurality of metal patterns (118) for electrically interconnecting the semiconductor die to electrical connections that are external to the package. The package further includes at least one conductively filled via (119) that is defined through the interconnect substrate and is in electrical contact with the ground plane. A second side of the ground plane includes patterned wettable pads over selected regions that are in electrical contact with at least one via.
摘要翻译：公开了一种半导体封装结构。封装结构包括散热器，用于散发在半导体封装结构内产生的热量。该封装还包括接地平面，该接地平面具有用电绝缘粘合剂附接到散热器的第一侧。接地平面具有限定到散热器的表面的路径的第一孔，其构造成接收半导体管芯。互连基板粘合地附接到接地平面，并且互连基板在接地平面的第一孔上方具有互补的第二孔。优选地，互连衬底具有用于将半导体管芯电连接到半导体封装结构外部的电连接的多个金属图案。封装结构还包括至少一个通过互连衬底限定的导电填充通孔，并且与接地平面电接触以建立与互连衬底的多个金属图案中的选定的金属图案的直接接地连接。优选地，接地平面的第二侧包括在与通过互连衬底限定的至少一个导电填充的通孔电接触的选定区域上的图案化的可润湿压板。

74. 发明公开

EP1019960A1 BALL GRID ARRAY SEMICONDUCTOR PACKAGE AND METHOD FOR MAKING THE SAME 失效
标题翻译：半导体封装与球矩阵处理用于生产
公开(公告)号：EP1019960A1
公开(公告)日：2000-07-19
申请号：EP98920999.4
申请日：1998-05-05
申请人： Signetics KP Co., Ltd.
发明人： KARNEZOS, Marcos
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/49 , H01L23/3128 , H01L23/36 , H01L23/544 , H01L24/48 , H01L24/73 , H01L2223/54473 , H01L2223/54486 , H01L2224/16 , H01L2224/16225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/48465 , H01L2224/49109 , H01L2224/73253 , H01L2224/73265 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01021 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01042 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/07802 , H01L2924/14 , H01L2924/15153 , H01L2924/15157 , H01L2924/15162 , H01L2924/15165 , H01L2924/1517 , H01L2924/15311 , H01L2924/1532 , H01L2924/181 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H05K1/0219 , H05K3/3436 , H01L2924/00 , H01L2924/00012 , H01L2224/45099
摘要： Disclosed is a semiconductor package that includes a heat spreader (110). The package further includes a ground plane (160) having a first side that is attached to the heat spreader with an elctrically insulating adhesive (127). The ground plane has a first aperture (166a) defining a path to a surface of the heat spreader tthat is configured to receive a semiconductor die. An interconnect substrate (125) is adhesively attached to the ground plane, and the interconnect substrate has a second apperture (154) over the first aperture of the ground plane. Preferably, the interconnect substrate has a plurality of metal patterns (118) for electrically interconnecting the semiconductor die to electrical connections that are external to the package. The package further includes at least one conductively filled via (119) that is defined through the interconnect substrate and is in electrical contact with the ground plane. A second side of the ground plane includes patterned wettable pads over selected regions that are in electrical contact with at least one via.

75. 发明公开

EP0315792A2 Interconnection system for integrated circuit chips 失效
标题翻译： Zwischenschaltungsystemfürintegrierte Halbleiterschaltungen。
公开(公告)号：EP0315792A2
公开(公告)日：1989-05-17
申请号：EP88117121.9
申请日：1988-10-14
申请人： LORAL AEROSPACE CORPORATION
发明人： Chall, Louis Edmond, Jr.
IPC分类号： H01L23/48 , H05K7/20 , H01L23/52
CPC分类号： H01L23/52 , G01R31/318505 , G11C29/006 , H01L23/13 , H01L23/473 , H01L23/5385 , H01L2924/0002 , H01L2924/15162 , H01L2924/3011 , H05K1/0286 , H05K1/142 , H05K3/3442 , H05K3/403 , H05K7/20545 , H05K2201/09181 , H05K2201/09418 , H05K2201/1053 , H05K2201/10727 , Y02P70/613 , H01L2924/00
摘要： A novel packaging system for VLSI circuits allows low-cost construction and maintenance of complex high density high-performance devices with low power requirements. The devices can be individually created by software means from a small selection of standardizable IC chips by disposing a plurality of chips in leadless chip carriers in a mosaic on a substrate, and configuring them by software to selectively communicate with other chips of the mosaic or even to individually change their operating function. The immediate juxtaposition of the chip carries in the mosaic eliminates transmission line data skew, and also allows considerable savings in chip space and power requirements by dispensing with interconnection drivers, receivers and bonding pads. The chip carrier mosaics may be assembled into modules suitable for plug-in connection to an interconnecting backplane to create even larger devices, and individual modules can be dynamically tested in their high-performance mode by configuring one or more modules as test modules and either plugging them into modules to be tested or making them a permanent part of the device's module array.
摘要翻译：用于VLSI电路的新型封装系统允许低成本构建和维护具有低功耗要求的复杂高密度高性能器件。通过在基板上的马赛克中的无引线芯片载体中布置多个芯片，并且通过软件来配置它们以选择性地与马赛克的其他芯片进行通信，甚至可以通过软件来从小量的可标准化的IC芯片中分别创建设备单独改变其操作功能。芯片中马上并置的马赛克并排消除了传输线数据的偏移，并且通过分配互连驱动器，接收器和接合焊盘，可以大大节省芯片空间和功耗。芯片载体马赛克可以组装成适合于插入连接到互连背板的模块，以创建更大的设备，并且可以通过将一个或多个模块配置为测试模块和插件来以高性能模式动态测试各个模块它们被组合成要测试的模块或使其成为设备模块阵列的永久部分。

76. 发明申请

WO2014149448A1 PACKAGING FOR AN ELECTRONIC CIRCUIT 审中-公开
标题翻译：包装电子电路
公开(公告)号：WO2014149448A1
公开(公告)日：2014-09-25
申请号：PCT/US2014/018525
申请日：2014-02-26
申请人： ALLEGRO MICROSYSTEMS, LLC
发明人： LIU, Shixi, Louis , WONG, Harianto , DAVID, Paul , SAUBER, John, B. , MILANO, Shaun, D. , KANDA, Raguvir , HEMENWAY, Bruce
IPC分类号： G01R15/20 , H01L23/495 , H01L23/00 , H01L43/06
CPC分类号： H01L43/14 , G01R15/202 , G01R15/207 , G01R33/0052 , G01R33/09 , H01L21/4828 , H01L23/49548 , H01L24/13 , H01L24/16 , H01L24/81 , H01L43/04 , H01L43/065 , H01L2224/131 , H01L2224/16245 , H01L2224/81801 , H01L2924/15162 , H01L2924/014 , H01L2924/00014
摘要： In one aspect, a method includes processing a metal substrate, performing a first etch on a first surface of the metal substrate to form, for an integrated circuit package, secondary leads and a curved component having two primary leads and performing a second etch, on a second surface of the substrate opposite the first surface, at locations (230) on the secondary leads and locations on the curved component to provide a locking mechanism. Each primary lead is located at a respective end of the curved component.
摘要翻译：在一个方面，一种方法包括处理金属衬底，在金属衬底的第一表面上执行第一蚀刻，以形成用于集成电路封装的次级引线和具有两个初级引线并执行第二次蚀刻的弯曲元件所述基板的与所述第一表面相对的第二表面，在所述次级引线上的位置（230）处和所述弯曲部件上的位置以提供锁定机构。每个主引线位于弯曲部件的相应端部。

77. 发明申请

WO2014020975A1 積層基板审中-公开
标题翻译：分层基板
公开(公告)号：WO2014020975A1
公开(公告)日：2014-02-06
申请号：PCT/JP2013/064579
申请日：2013-05-27
申请人：株式会社村田製作所
发明人：林繁利 , 横山智哉 , 佐藤貴子
IPC分类号： H01L23/12 , H01L23/13
CPC分类号： H05K1/112 , H01L23/13 , H01L23/15 , H01L23/49805 , H01L23/49822 , H01L23/49838 , H01L2224/16225 , H01L2924/15162 , H01L2924/1531 , H01L2924/19105 , H05K1/0271 , H05K1/0298 , H05K1/0306 , H05K1/092 , H05K1/113 , H05K1/116 , H05K1/165 , H05K3/403 , H05K3/4629 , H05K2201/083 , H05K2201/09145
摘要：　電極パッドとセラミックとの線膨張係数の差に起因して生じる応力により、クラックが発生することを防止する積層基板を提供する。　最外層の部品搭載用電極パッド（２１Ａ）の下層に配置されている電極パッド（７１）は、当該部品搭載用電極パッド（２１Ａ）よりも面積が広い。同様に、部品搭載用電極パッド（２１Ｂ）の下層に配置されている電極パッド（７７）は、当該部品搭載用電極パッド（２１Ｂ）よりも面積が広く、部品搭載用電極パッド（２１Ｃ）の下層に配置されている電極パッド（７８）は、当該部品搭載用電極パッド（２１Ｃ）のよりも面積が広く、部品搭載用電極パッド（２１Ｄ）の下層に配置されている電極パッド（７４）は、当該部品搭載用電極パッド（２１Ｄ）よりも面積が広い。
摘要翻译：提供一种用于防止由电极焊盘和陶瓷的线性膨胀系数之间的差异引起的应力产生裂纹的分层基板。布置在用于在最外层上安装部件的电极焊盘（21A）的下层上的电极焊盘（71）的表面积大于用于安装部件的电极焊盘（21A）的表面积。类似地，布置在用于安装部件的电极焊盘（21B）的下层上的电极焊盘（77）的表面积大于用于安装部件的电极焊盘（21B）的表面积，电极焊盘（78）布置在用于安装部件的电极焊盘（21C）的下层上的表面积大于用于安装部件的电极焊盘（21C）的表面积，以及布置在电极焊盘的下层上的电极焊盘（74）（21D）用于安装部件的表面积大于用于安装部件的电极焊盘（21D）的表面积。

78. 发明申请

WO2012167488A1 COF、COF载带及液晶电视的驱动电路审中-公开
公开(公告)号：WO2012167488A1
公开(公告)日：2012-12-13
申请号：PCT/CN2011/077594
申请日：2011-07-26
申请人：深圳市华星光电技术有限公司 , 林柏伸 , 廖良展 , 张勇
发明人：林柏伸 , 廖良展 , 张勇
IPC分类号： H01L23/498 , H01L21/60
CPC分类号： H01L23/4985 , H01L2924/0002 , H01L2924/15162 , H01L2924/00
摘要：一种COF载带，包括由若干个COF（200）依次连接起来构成的COF带以及与所述COF带相连接的载体（301）。所述COF（200）外形为由两条相互平行走线边（201、202）和两条不平行的侧边（203、205）构成的梯形，相邻两个所述COF（200）之间，一COF（200）的长走线边（202）与另一COF（200）的短走线边（201）相接并在同一直线上，两个COF（200）另外的短走线边（201）、长走线边（202）也相接并在同一直线上。通过这种设计，COF节省了材料。在载带型半导体装置中，这种COF能在规定长度的载带上增加COF的数量，从而大幅度地降低成本。

79. 发明申请

WO2006030517A1 半導体装置及びその製造方法审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：WO2006030517A1
公开(公告)日：2006-03-23
申请号：PCT/JP2004/013629
申请日：2004-09-17
申请人：富士通株式会社 , 藤沢哲也 , 小澤要 , 佐藤光孝
发明人：藤沢哲也 , 小澤要 , 佐藤光孝
IPC分类号： H01L23/12
CPC分类号： H01L23/49827 , H01L23/13 , H01L23/3128 , H01L23/49816 , H01L23/50 , H01L23/5384 , H01L23/5386 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/81 , H01L24/85 , H01L24/91 , H01L24/97 , H01L25/0652 , H01L25/18 , H01L2224/0401 , H01L2224/05554 , H01L2224/06135 , H01L2224/16145 , H01L2224/16225 , H01L2224/274 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/48465 , H01L2224/49171 , H01L2224/73204 , H01L2224/73207 , H01L2224/73215 , H01L2224/73265 , H01L2224/81801 , H01L2224/85 , H01L2224/97 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/12041 , H01L2924/15162 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19104 , H01L2924/30105 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要：　本発明は、支持基板上に搭載される半導体素子及びその製造方法に関し、前記半導体素子において選択された外部接続用電極パッドが、前記支持基板に設けられた開口或いは切欠きを介して前記支持基板の他方の主面に導出され、前記支持基板の他方の主面に配設された配線層に電気的に接続されてなる半導体装置、及びその製造方法を提供するものであって、半導体装置としてより小形化が可能である構造とその製造方法に関する。
摘要翻译：公开了一种安装在支撑基板上的半导体器件及其制造方法。具体公开了一种半导体器件，其中用于半导体器件的外部连接的所选择的电极焊盘通过设置在衬底中的开口或切口引导到支撑衬底的另一个主表面，并与布置在另一个主体上的布线层电连接支撑基板的表面。此外，通过采用这种结构，可以减小半导体器件的尺寸，并且还公开了其制造工艺。

80. 发明申请

WO1998019340A1 LARGE-AREA HIGH-CURRENT MODULE OF A FIELD-CONTROLLED INTERRUPTIBLE POWER SEMICONDUCTOR SWITCH 审中-公开
标题翻译：控制区大面积HOCHSTROM模块，可断开功率半导体开关
公开(公告)号：WO1998019340A1
公开(公告)日：1998-05-07
申请号：PCT/DE1997002418
申请日：1997-10-20
申请人： SIEMENS AKTIENGESELLSCHAFT , OETJEN, Jens
发明人： SIEMENS AKTIENGESELLSCHAFT
IPC分类号： H01L25/07
CPC分类号： H01L25/07 , H01L25/072 , H01L2224/48091 , H01L2924/01004 , H01L2924/01066 , H01L2924/01067 , H01L2924/01068 , H01L2924/01078 , H01L2924/1301 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/15162 , H01L2924/00014 , H01L2924/00
摘要： The invention concerns a large-area high-current module of a field-controlled interruptible power semiconductor switch which comprises two large-area contact plates arranged opposite each other and n field-controlled interruptible low-volt power chips (6) whose drain terminals are electrically switched in parallel by one contact plate (2) and whose source terminals (8) are electrically switched in parallel by the other contact plate (4), these contact plates (2, 4) being insulated from each other at their contact faces. According to the invention, one contact plate (2) comprises a plurality of cavities into which insulation devices (10) plug a plurality of busbars (18) which are connected in an electrically conductive manner to the source terminals (8) of the n low-volt power chips (6). The contact plate (4), which connects the source terminals (8) of the n low-volt power chips (6) to one another in an electrically conductive manner, is provided with webs (20) corresponding to these busbars. As a result thereof, it is possible to produce in a simple manner a large-area high-current module of a field-controlled interruptible power semiconductor switch which can be combined in a housing with a GTO thyristor plate to form a GTO cascade circuit.
摘要翻译：本发明涉及一种场控制的关断功率半导体开关的一个大面积的高功率模块中，场控制的两个大面积相对的接触板，并且n，可断开低电压功率芯片（6），其漏极端子通过接触板（2）和的手段其源极端子（8）的其他接触板（4）的并联电连接的装置，所述接触板（2,4）分别绝缘它们的接触表面上的彼此。根据本发明，一个接触板（2），其中由绝缘的装置的多个凹部（10）中的多个汇流条（18）插头，其导电地连接到源极端子（8）的n个低电压功率芯片（6），和接触板（4）连接的源极端子（8）在n低电压功率芯片（6）相互导电的，设置有对应腹板这些母线（20）的。因此，获得一个简单的，以产生大面积的高电流模块可与GTO GTO Thyristorscheibe在一个场控制关断功率半导体开关的外壳组合以级联电路。

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