会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 71. 发明公开
    • 임피던스 교정회로
    • 阻抗校准电路
    • KR1020140003077A
    • 2014-01-09
    • KR1020120070625
    • 2012-06-29
    • 에스케이하이닉스 주식회사
    • 장동욱
    • G11C7/10G11C7/22
    • H03K17/16H03K17/166H03K2217/0063H03K2217/0072
    • An impedance calibration circuit comprises: a first calibrated voltage driving unit which is driven in response to a first enable signal and drives a first calibrated voltage by comparing the first calibrated voltage connected to external resistors and a first standard voltage; a first control code generator which is driven in response to a second enable signal and generates a first control code by comparing the first calibrated voltage and a first target voltage; and a first standard voltage generator which generates a level-adjustable first standard voltage in response to the first control code. [Reference numerals] (122) First counter; (123) First pull-up driving unit; (13) First control code generator; (14) First reference voltage generator; (151) Second pull-up driving unit; (153) Second counter; (154) Pull-down driving unit; (16) Second control code generator; (17) Second reference voltage generator
    • 阻抗校准电路包括:第一校准电压驱动单元,其响应于第一使能信号被驱动,并且通过比较连接到外部电阻器的第一校准电压和第一标准电压来驱动第一校准电压; 第一控制码发生器,其响应于第二使能信号被驱动,并通过比较第一校准电压和第一目标电压来产生第一控制码; 以及第一标准电压发生器,其响应于第一控制码产生电平可调节的第一标准电压。 (附图标记)(122)第一计数器 (123)第一上拉驱动单元; (13)第一控制码发生器; (14)第一参考电压发生器; (151)第二上拉驱动单元; (153)第二柜台; (154)下拉驱动单元; (16)第二控制码发生器; (17)第二参考电压发生器
    • 74. 发明申请
    • 半導体装置
    • 半导体器件
    • WO2016204122A1
    • 2016-12-22
    • PCT/JP2016/067584
    • 2016-06-13
    • 富士電機株式会社
    • 手塚 伸一大橋 英知
    • H03K17/08H02M1/08H03K17/687
    • H02M1/084G11C11/4091G11C2211/4013H01L29/0603H01L29/772H01L29/7802H02M1/32H02M7/48H02M7/5387H03K17/08122H03K17/0822H03K17/687H03K2217/0063H03K2217/0072
    • ハイサイドのパワーデバイスをオフ状態にするタイミングが遅れることで上下アーム短絡が発生するようなことがあっても、システムとして動作を継続できるようにする。 ハイサイド電位検出回路(18)により検出されたハイサイド基準電位(VS)が立上るとハイサイド電位判定回路(19)がイベント信号(EVENT)を出力し、そのとき論理入力信号(HIN)がLレベルであるとパルス生成回路(16)がハイサイド駆動回路(12)に対するリセット信号(RESET)を再生成する。過電流検出判定回路(21)は、ハイサイド制御用の論理入力信号(HIN)がLレベルのとき、イベント信号(EVENT)が入力されると過電流検出回路(20)からの過電流検出信号(OC_OUT)を無効にした過電流信号(VOC)を出力し、イベント信号(EVENT)が入力されていないと過電流検出信号(OC_OUT)を有効とする。
    • 本发明的目的是使得半导体器件能够作为系统继续工作,即使高侧功率器件关断的定时被延迟,导致上下臂之间的短路。 当由高侧电位检测电路(18)检测的高侧基准电位(VS)上升时,高侧电位判定电路(19)输出事件信号(EVENT)。 此时,如果逻辑输入信号(HIN)为低电平,则脉冲发生电路(16)再生用于高侧驱动电路(12)的复位信号(RESET)。 如果用于高侧控制的逻辑输入信号(HIN)处于低电平,则当输入事件信号(EVENT)时,过电流检测和确定电路(21)输出禁止过电流检测的过电流信号(VOC) 来自过电流检测电路(20)的信号(OC_OUT),如果未输入事件信号(EVENT),则使能过电流检测信号(OC_OUT)。
    • 75. 发明申请
    • HIGH-SPEED GATE DRIVER FOR POWER SWITCHES WITH REDUCED VOLTAGE RINGING
    • 具有降低电压环的电源开关的高速栅极驱动器
    • WO2014057084A2
    • 2014-04-17
    • PCT/EP2013071267
    • 2013-10-11
    • SL3J SYSTEMS S A R L
    • AJRAM SAMI
    • H03K19/003H03K17/082H03K19/0185
    • H03K19/00361H03K17/082H03K19/018507H03K2217/0063H03K2217/0072
    • A fast power switch comprises one or more field- effect transistors, such as pull-up and pull-down transistors, that are coupled to a load. Respective driver electronic circuits for each of the field-effect transistors include parallel first and second drivers (X30, X33) with a shared driver output coupled to a gate of the field-effect transistor. The first and second drivers (X30, X33) are operative to switch the shared driver output for the appropriate field-effect transistor in response to a transition (e.g., low-to-high or high-to-low) at a driver input terminal. A control circuit (X35) enables the stronger second driver (X33) in response to a transition at the driver input terminal and subsequently disables the second driver (X33) once a transition threshold at the gate of the field-effect transistor(s) is crossed. The weaker first driver (X30) is sized to damp reactive energy at the load to minimize ringing.
    • 快速功率开关包括耦合到负载的一个或多个场效应晶体管,例如上拉和下拉晶体管。 用于每个场效应晶体管的相应驱动器电子电路包括具有耦合到场效应晶体管的栅极的共享驱动器输出的并联第一和第二驱动器(X30,X33)。 第一和第二驱动器(X30,X33)响应于在驱动器输入端子处的转变(例如,从低到高或从高到低)而操作以切换适当的场效应晶体管的共享驱动器输出 。 控制电路(X35)响应于驱动器输入端子处的转变而启用较强的第二驱动器(X33),并且随后一旦场效应晶体管(一个或多个)的栅极处的转变阈值为 交叉。 较弱的第一个驱动器(X30)的大小可以减小负载的无功能量,以最大限度地减少振铃。
    • 76. 发明申请
    • HALF BRIDGE ADAPTIVE DEAD TIME CIRCUIT AND METHOD
    • 半桥自适应死区时间电路和方法
    • WO2005079513B1
    • 2007-06-21
    • PCT/US2005005349
    • 2005-02-22
    • INT RECTIFIER CORPRUSU IULIAWILHELM DANAGREEN PETER
    • RUSU IULIAWILHELM DANAGREEN PETER
    • G05F1/00G05F1/40H02M1/38H03K17/296
    • H02M1/38H03K17/166H03K17/284H03K17/6871H03K2217/0063H03K2217/0072H03K2217/0081
    • A high voltage offset detection circuit registers the voltage at the midpoint of a switching half-bridge and may determine when the midpoint voltage reaches a given value to avoid hard-switching in the half-bridge switches. The midpoint voltage of the switching half-bridge is applied through a buffer to a MOSFET that is current limited to produce a voltage that reflects the voltage of the midpoint of the switching half-bridge. The voltage produced by the MOSFET may be supplied to a comparator with a threshold input to obtain a signal that indicates when the switches of the switching half-bridge may be turned on to avoid hard-switching. An adaptive dead-time circuit and method may comprise the above sensing circuit, a first circuit for generating a first signal indicative of a high to low transition of the midpoint voltage; and an output circuit for generating an adaptive dead-time output signal based thereon. A second circuit may generate a second signal indicative of a low to high transition of the voltage; wherein the output circuit generates the adaptive dead-time output signal based on both the first and second signals. The second circuit preferably generates the second signal by reproducing the first signal. The first circuit may generate the first signal by charging a capacitor in response to pulses, and the second circuit may generate the second signal by charging a second capacitor corresponding to said first capacitor, and the adaptive dead-time output signal may be responsive to the charges on the first and second capacitors.
    • 高电压偏移检测电路将电压记录在开关半桥的中点处,并且可以确定中点电压何时达到给定值以避免半桥开关中的硬切换。 通过缓冲器将开关半桥的中点电压施加到MOSFET,该MOSFET被限制电流以产生反映开关半桥中点电压的电压。 由MOSFET产生的电压可以被提供给具有阈值输入的比较器以获得指示开关半桥的开关何时可以导通以避免硬开关的信号。 自适应死区电路和方法可以包括上述感测电路,用于产生指示中点电压的高到低转变的第一信号的第一电路; 以及用于基于此产生自适应停滞时间输出信号的输出电路。 第二电路可以产生指示电压从低到高转换的第二信号; 其中所述输出电路基于所述第一信号和所述第二信号二者来生成所述自适应死区输出信号。 第二电路最好通过再现第一信号来产生第二信号。 第一电路可响应于脉冲通过对电容器充电来产生第一信号,并且第二电路可通过对与所述第一电容器对应的第二电容器充电来产生第二信号,并且自适应停滞时间输出信号可响应 第一和第二电容器上的电荷。