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    • 83. 发明授权
    • Data processing apparatus and method for determining an initial estimate of a result value of a reciprocal operation
    • 用于确定倒数操作的结果值的初始估计的数据处理装置和方法
    • US07747667B2
    • 2010-06-29
    • US11058421
    • 2005-02-16
    • David Raymond LutzChristopher Neal HindsDominic Hugo SymesSimon Andrew Ford
    • David Raymond LutzChristopher Neal HindsDominic Hugo SymesSimon Andrew Ford
    • G06F7/38
    • G06F7/535G06F9/30014G06F9/3004G06F2207/3824G06F2207/5354G06F2207/5355G06F2207/5356
    • A data processing apparatus and method generate an initial estimate of a result value that would be produced by performing a reciprocal operation on an input value. The input value and the result value are either fixed point values or floating point values. The data processing apparatus comprises processing logic for executing instructions to perform data processing operations on data, and a lookup table referenced by the processing logic during generation of the initial estimate of the result value. The processing logic is responsive to an estimate instruction to reference the lookup table to generate, dependent on a modified input value that is within a predetermined range of values, a table output value. For a particular modified input value, the same table output value is generated irrespective of whether the input value is a fixed point value or a floating point value. The initial estimate of the result value is then derivable from the table output value. This provides a particularly efficient technique for performing the initial estimate generation within a data processing apparatus where the reciprocal operation may be performed on either fixed point values or floating point values.
    • 数据处理装置和方法生成对通过对输入值执行倒数操作而产生的结果值的初始估计。 输入值和结果值是固定点值或浮点值。 该数据处理装置包括执行用于对数据执行数据处理操作的指令的处理逻辑,以及在生成结果值的初始估计期间由处理逻辑引用的查找表。 处理逻辑响应于估计指令以引用查找表,以根据在预定范围内的修改的输入值来生成表输出值。 对于特定的修改输入值,无论输入值是固定点值还是浮点值,都会生成相同的表格输出值。 结果值的初始估计值可从表输出值推导出来。 这提供了用于在数据处理装置中执行初始估计生成的特别有效的技术,其中可以对固定点值或浮点值执行倒数操作。
    • 86. 发明授权
    • Data processing apparatus and method for performing floating point multiplication
    • 用于执行浮点乘法的数据处理装置和方法
    • US07668896B2
    • 2010-02-23
    • US11081833
    • 2005-03-17
    • David Raymond LutzChristopher Neal Hinds
    • David Raymond LutzChristopher Neal Hinds
    • G06F7/44
    • G06F7/49963G06F7/487G06F7/49915G06F7/49936
    • The first and second n-bit significands are multiplied producing a pair of 2n-bit vectors, and half adder logic produces a corresponding plurality of carry and sum bits. A product exponent is checked for correspondence with a predetermined exponent value. A sum operation generates a first result equivalent to the addition of the pair of 2n-bit vectors. First adder logic uses corresponding m carry and sum bits, the least significant of them carry bits being replaced with the increment value prior to the first adder logic performing the first sum operation. Second adder logic performs a second sum operation and uses the corresponding m−1 carry and sum bits replacing the least significant m−1 carry bits with the rounding increment value prior to the second adder logic second sum operation. The n-bit result is derived from either the first rounded result, the second rounded result or a predetermined result value.
    • 乘以第一和第二n位有效值产生一对2n位向量,而半加法器逻辑产生相应的多个进位和和位。 检查产品指数与预定指数值的对应关系。 和操作产生等价于一对2n位向量的相加的第一结果。 第一加法器逻辑使用对应的m进位和和位,其中最低有效位在第一加法器逻辑执行第一和运算之前,将位替换为增量值。 第二加法器逻辑执行第二和操作,并且在第二加法器逻辑第二和操作之前使用相应的m-1进位和和位来替换最低有效m-1进位与舍入增量值。 n位结果来自第一舍入结果,第二舍入结果或预定结果值。
    • 87. 发明授权
    • Serrated MEMS resonators
    • 锯齿型MEMS谐振器
    • US07545239B2
    • 2009-06-09
    • US11613910
    • 2006-12-20
    • Paul Merritt HagelinDavid Raymond Pedersen
    • Paul Merritt HagelinDavid Raymond Pedersen
    • H03H9/125H03H9/24H03B5/30H03H9/46
    • H03H9/02259H03H9/02244H03H9/02433H03H9/2405H03H9/2484H03H2009/0248H03H2009/02496
    • One embodiment of the present invention sets forth a serrated tooth actuator for driving MEMS resonator structures. The actuator includes a fixed drive electrode having a serrated tooth surface opposing a MEMS resonator arm also having a serrated tooth surface, where the MEMS resonator arm is configured to rotate towards the drive electrode when an AC signal is applied to the drive electrode. Such a configuration permits higher amplitude signals to be applied to the drive electrode without the performance of the actuator being compromised by nonlinear effects. In addition, the serrated tooth configuration enables a sufficiently high actuating force to be maintained even though the distance traversed by the MEMS resonator arm during operation is quite small. Further, the serrated configuration allows a MEMS resonator system to withstand larger fluctuations in voltage and larger substrate stresses without experiencing a substantial shift in resonant frequency.
    • 本发明的一个实施例提出了用于驱动MEMS谐振器结构的锯齿状致动器。 致动器包括固定的驱动电极,其具有与具有锯齿状齿表面的MEMS谐振器臂相对的锯齿状齿表面,其中,当将CCP信号施加到驱动电极时,MEMS谐振臂被配置为朝向驱动电极旋转。 这种配置允许将更高幅度的信号施加到驱动电极,而不会使致动器的性能受到非线性效应的影响。 此外,即使在操作期间由MEMS谐振器臂穿过的距离相当小,锯齿形齿构造也能够保持足够高的致动力。 此外,锯齿形配置允许MEMS谐振器系统承受较大的电压波动和较大的衬底应力,而不会发生谐振频率的实质性偏移。
    • 88. 发明授权
    • Data processing apparatus and method for converting a fixed point number to a floating point number
    • 用于将固定点数转换为浮点数的数据处理装置和方法
    • US07401107B2
    • 2008-07-15
    • US11019097
    • 2004-12-22
    • David Raymond LutzChristopher Neal Hinds
    • David Raymond LutzChristopher Neal Hinds
    • G06F5/00
    • G06F7/49963
    • A data processing apparatus and method are provided for converting an m-bit fixed point number to a rounded floating point number having an n-bit significand, where n is less than m. The data processing apparatus comprises determination logic for determining the bit location of the most significant bit of the value expressed within the m-bit fixed point number, and low order bit analysis logic for determining from a selected number of least significant bits of the m-bit fixed point number a rounding signal indicating whether a rounding increment is required in order to generate the n-bit significand. Generation logic is then arranged in response to the rounding signal to generate a rounding bit sequence appropriate having regard to the bit location determined by the determination logic. Adder logic then adds the rounding bit sequence to the m-bit fixed point number to generate an intermediate result, whereafter normalisation logic shifts the intermediate result to generate the n-bit significand. At this point, due to the incorporation of the rounding information prior to the addition, the generated n-bit significand is correctly rounded.
    • 提供了一种数据处理装置和方法,用于将m位固定点数转换为具有n位有效位的四舍五入浮点数,其中n小于m。 数据处理装置包括用于确定在m位固定点数中表示的值的最高有效位的位位置的确定逻辑,以及用于根据m位固定点数的选定数量的最低有效位确定的低阶位分析逻辑, 指定是否需要舍入增量以产生n位有效位的舍入信号的位固定点编号。 然后响应于舍入信号来安排生成逻辑,以便考虑到由确定逻辑确定的比特位置产生适当的舍入比特序列。 然后,加法器逻辑将舍入比特序列添加到m位固定点号以产生中间结果,之后归一化逻辑移位中间结果以产生n位有效位数。 在这一点上,由于在添加之前结合舍入信息,所生成的n位有效位数被正确地舍入。