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81. 发明申请

WO0182333A3 HOMOGENEOUS GATE OXIDE THICKNESS FOR VERTICAL TRANSISTOR STRUCTURES 审中-公开
标题翻译：用于垂直晶体管结构的均匀栅极氧化物厚度
公开(公告)号：WO0182333A3
公开(公告)日：2002-01-24
申请号：PCT/US0110919
申请日：2001-04-04
申请人： INFINEON TECHNOLOGIES CORP
发明人： TEWS HELMUT HORST , LEE BRIAN S , GRUENING ULRIKE
IPC分类号： H01L21/28 , H01L21/8242 , H01L29/04
CPC分类号： H01L21/28211 , H01L21/2236 , H01L21/26506 , H01L21/26586 , H01L21/2822 , H01L21/28238 , H01L27/10864 , H01L27/10873 , H01L29/045
摘要： Improved process for preparing vertical transistor structures in DRAMs, in which the trench top oxide separates the bottom storage capacitor from the switching transistor, and in which the upper part of the trench contains the vertical transistor at its side wall, to obtain homogeneous gate oxidation at all different crystal planes inside the trench so that homogeneous thickness is independent of crystal orientation comprising: a) subjecting a wafer trench side wall to ion bombardment (20) for a period sufficient to generate an amorphous layer (22) on the side wall; and b) heating the wafer resulting from step (a) in an oxidizing atmosphere to cause oxidation and recrystallization of the amorphous layer.
摘要翻译：在DRAM中制备垂直晶体管结构的改进方法，其中沟槽顶部氧化物将底部存储电容器与开关晶体管分离，并且其中沟槽的上部在其侧壁处包含垂直晶体管，以获得均匀的栅极氧化沟槽内的所有不同的晶面，使得均匀的厚度与晶体取向无关，包括：a）使晶片沟槽侧壁进行离子轰击（20）足以在侧壁上产生非晶层（22）的时间; 和b）在氧化气氛中加热由步骤（a）得到的晶片，以引起非晶层的氧化和再结晶。

82. 发明申请

WO02001567A2 STRUCTURE AND PROCESS FOR 6F<2> TRENCH CAPACITOR DRAM CELL WITH VERTICAL MOSFET AND 3F BITLINE PITCH 审中-公开
标题翻译：具有垂直MOSFET和3F位线点的6F 2晶体管电容器DRAM单元的结构和工艺
公开(公告)号：WO02001567A2
公开(公告)日：2002-01-03
申请号：PCT/US2001/020221
申请日：2001-06-25
IPC分类号： H01L21/8242 , H01L27/108 , G11C11/00
CPC分类号： H01L27/10864 , H01L27/10841
摘要： A memory cell structure including a planar semiconductor substrate. A deep trench is in the semiconductor substrate. The deep trench has a plurality of side walls and a bottom. A storage capacitor is at the bottom of the deep trench. A vertical transistor extends down at least one side wall of the deep trench above the storage capacitor. The transistor has a source diffusion extending in the plane of the substrate adjacent the deep trench. An isolation extends down at least one other side wall of the deep trench opposite the vertical transistor. Shallow trench isolation regions extend along a surface of the substrate in a direction transverse to the side wall where the vertical transistor extends. A gate conductor extends within the deep trench. A wordline extends over the deep trench and is connected to the gate conductor. A bitline extends above the surface plane of the substrate and has a contact to the source diffusion between the shallow trench isolation regions.
摘要翻译：一种存储单元结构，包括平面半导体衬底。深沟槽位于半导体衬底中。深沟槽具有多个侧壁和底部。存储电容器位于深沟槽的底部。垂直晶体管向下延伸存储电容器上方的深沟槽的至少一个侧壁。晶体管具有在邻近深沟槽的衬底的平面中延伸的源极扩散。隔离层向下延伸与垂直晶体管相对的深沟槽的至少另一个侧壁。浅沟槽隔离区域沿垂直晶体管延伸的侧壁横向延伸的衬底表面延伸。栅极导体在深沟槽内延伸。一条字线延伸穿过深沟槽并连接到栅极导体。位线延伸在衬底的表面平面之上，并且具有与浅沟槽隔离区之间的源极扩散的接触。

83. 发明申请

WO01088984A1 VERTICAL TRANSISTOR 审中-公开
标题翻译：垂直晶体管
公开(公告)号：WO01088984A1
公开(公告)日：2001-11-22
申请号：PCT/DE2001/001800
申请日：2001-05-11
IPC分类号： H01L27/108 , H01L21/336 , H01L21/8242 , H01L29/78 , H01L29/786
CPC分类号： H01L29/78612 , H01L27/10864 , H01L27/10876 , H01L29/66666 , H01L29/78642
摘要： The invention relates to a vertical transistor (1) such as is used in a DRAM memory cell. In DRAM memory cells the individual memory cells are insulated from one another by an insulation trench (6) (STI). Since its channel region is insulated from a substrate (2) by the insulation trench (6), the vertical transistor (1) is configured as an SOI transistor by said insulation trench (6). The invention also relates to a system and to a method for connecting the channel region (5) of the vertical transistor (1) to the substrate (2) by providing a conductive layer (10) in the insulating trench (6) between a lower insulation filling (8) and an upper insulating filling (9).
摘要翻译：本发明涉及纵向晶体管（1），这是例如在DRAM存储器单元使用。在DRAM的存储单元，这是共同的个别存储器单元与隔离沟槽（6）（STI）以彼此隔离。在此，垂直晶体管（1）通过隔离沟槽（6）形成为SOI晶体管，由于它的沟道区域是通过从基板（2）的隔离沟槽（6）分离。本发明涉及一种装置和用于在基板上的垂直晶体管（1）的（5）（2）通过在下部绝缘填充物之间的隔离沟槽（6）的导电层（10）连接的信道区域的方法（8）和上绝缘填充（9）被布置。

84. 发明申请

WO01017015A1 METHOD FOR PRODUCING A DRAM CELL ARRANGEMENT 审中-公开
标题翻译：一种用于生产DRAM单元安排
公开(公告)号：WO01017015A1
公开(公告)日：2001-03-08
申请号：PCT/DE2000/002647
申请日：2000-08-08
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L27/10864 , H01L27/10867
摘要： The invention relates to a DRAM cell arrangement. A cavity (V) for a capacitor of a storage cell pertaining to the DRAM cell arrangement is produced in a substrate (1). An insulation (I) and a storage node (SP) of the capacitor are generated in the cavity (V). A spacer consisting of silicon is produced over the storage node (SP). A first component of the spacer is doped by means of inclined implantation. The spacer is structured by using the different doping of the first component of the spacer. The storage node (SP) and the insulation (I) are changed by means of the structured spacer as a mask in such a way that the storage node (SP) is only directly adjacent to the substrate in a defined section of a flank pertaining to the cavity (V) and is otherwise separated from the substrate (1) by means of the insulation (I).
摘要翻译：在DRAM单元结构的存储单元的衬底（1），对于一个电容器中产生的凹部（V）。在凹陷（V），一个绝缘体（I）和所述电容器的存储节点（SP）产生的。上面的存储节点（SP），由硅制成的间隔件被产生。间隔物的第一部分是通过倾斜注入掺杂。以所述间隔物的第一部分的unterschliedlichen掺杂的优点，间隔件构造。具有图案化间隔物的帮助下作为掩模，存储节点（SP）和绝缘（I）被改变，使得存储节点（SP）是相邻只到凹陷（V）的侧壁的一个有限部直接在基板上（1）和否则通过从基板（1）绝缘物（I）被断开。

85. 发明申请

WO01001481A1 MOS TRANSISTOR AND DRAM CELL ARRANGEMENT AND METHOD FOR THE PRODUCTION THEREOF 审中-公开
标题翻译： MOS晶体管和DRAM单元安排和方法及其
公开(公告)号：WO01001481A1
公开(公告)日：2001-01-04
申请号：PCT/DE2000/001740
申请日：2000-05-29
IPC分类号： H01L21/336 , H01L21/8242 , H01L27/108 , H01L29/78 , H01L29/786
CPC分类号： H01L27/10864 , H01L27/10876 , H01L29/66666 , H01L29/7841 , H01L29/78642
摘要： The MOS transistor has an upper source/drain area (S/DO), a channel area and a lower source/drain area which are placed on top of each other as layers, forming a projection of a substrate. A gate dielectric (GD) is arranged adjacent to a first side surface of said projection. A gate electrode is arranged adjacent to the gate dielectric. A conductive structure (L) is arranged adjacent to a side surface of the projection in the region of the channel. The conductive structure is arranged adjacent to the gate electrode, whereby the channel area is conductively connected to the gate electrode. Floating body effects are avoided and the MOS transistor has a variable blocking voltage (DTMOS).
摘要翻译：所述MOS晶体管包括一个上源/漏区（S / DO），信道区域和下部的源极/漏极区（S / DU），其被堆叠为层，并且形成在基板的凸部上，栅极电介质（GD）邻近于所述突出部的第一侧表面。邻近该栅极电介质的栅电极。导电结构（L）邻近于所述沟道区的区域中的突出部的第二侧表面。该导电结构是邻近栅电极，使得所述沟道区导电性地连接到栅电极。避免浮体效应，和MOS晶体管具有可变阈值电压（DTMOS）。

86. 发明授权

EP0948053B1 Semiconductor device with vertical transistor and buried word line 有权
标题翻译：具有垂直晶体管的半导体器件和掩埋字线
公开(公告)号：EP0948053B1
公开(公告)日：2014-04-30
申请号：EP99102355.7
申请日：1999-02-06
申请人： Qimonda AG
发明人： Rupp, Thomas , Alsmeier, Johann
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L27/10864 , H01L27/10841

87. 发明授权

EP1186045B1 LAYOUT AND WIRING SCHEME FOR MEMORY CELLS WITH VERTICAL TRANSISTORS 有权
标题翻译：布局和连接方案与垂直晶体管的存储单元
公开(公告)号：EP1186045B1
公开(公告)日：2012-07-11
申请号：EP00936042.1
申请日：2000-05-18
申请人： Qimonda AG
发明人： RADIUS, Roland
IPC分类号： H01L27/108 , H01L21/8242 , H01L27/02
CPC分类号： H01L27/10864 , H01L27/0207 , H01L27/10841
摘要： A memory device (10) having vertical transistors in accordance with the present invention includes an active area pad (12) isolated from adjacent active area pads (12) on all sides and having a set of trench capacitors (14) associated therewith. The set of trench capacitors (14) are coupled to the active area pad (12) through vertical transistors (22). The active area pad is configured to connect the set of trench capacitors to a first contact (16). A gate conductor pad (18) is disposed between a set of active area pads and adapted to activate at least one vertical transistor in each active area pad adjacent to the gate conductor pad. Each gate conductor pad is activated by a second contact (24) such that when the gate conductor pad is activated through the second contact the at least one vertical transistor in each active area pad conducts to provide access to the trench capacitors and transfers a state between the first contact and the trench capacitors.

88. 发明授权

EP1661176B1 Implantation method for a vertical transistor 有权
标题翻译：植入的垂直晶体管的
公开(公告)号：EP1661176B1
公开(公告)日：2011-12-28
申请号：EP04780833.2
申请日：2004-08-12
申请人： International Business Machines Corporation
发明人： WANG, Geng , MCSTAY, Kevin , WEYBRIGHT, Mary, Elizabeth , LI, Yujun c/o IBM United Kingdom Ltd , CHIDAMBARRAO, Dureseti
IPC分类号： H01L21/8234 , H01L21/265 , H01L21/336 , H01L29/10 , H01L21/8242 , H01L29/78
CPC分类号： H01L27/10876 , H01L21/26586 , H01L27/10864 , H01L29/1041 , H01L29/66537 , H01L29/66666 , H01L29/7827 , H01L29/945
摘要： A method of formation of a deep trench vertical transistor is provided. A deep trench with a sidewall in a doped semiconductor substrate is formed. The semiconductor substrate includes a counterdoped drain region in the surface thereof and a channel alongside the sidewall. The drain region has a top level and a bottom level. A counterdoped source region is formed in the substrate juxtaposed with the sidewall below the channel. A gate oxide layer is formed on the sidewalls of the trench juxtaposed with a gate conductor. Perform the step of recessing the gate conductor below the bottom level of the drain region followed by performing angled ion implantation at an angle θ + δ with respect to vertical of a counterdopant into the channel below the source region and performing angled ion implantation at an angle θ with respect to vertical of a dopant into the channel below the source region.

89. 发明公开

EP1553631A3 Nitrided STI liner oxide for reduced corner device impact on vertical device performance 审中-公开
标题翻译：氮化STI Oxidtrennschicht角对垂直器件的性能降低的影响
公开(公告)号：EP1553631A3
公开(公告)日：2009-10-07
申请号：EP05250031.1
申请日：2005-01-06
申请人： International Business Machines Corporation , Infineon Technologies AG
发明人： Beintner, Jochen, IBM United Kingdom Ltd. , Divakaruni, Rama, IBM United Kingdom Ltd. , Jammy, Rajarao, IBM United Kingdom Ltd.
IPC分类号： H01L27/108 , H01L21/762 , H01L21/8242
CPC分类号： H01L27/10864 , H01L27/10841 , H01L27/10894
摘要： A method of fabricating an integrated circuit device comprises etching a trench in a substrate and forming a dynamic random access memory (DRAM) cell having a storage capacitor at a lower end and an overlying vertical metal oxide semiconductor field effect transistor (MOSFET) comprising a gate conductor and a boron-doped channel. The method includes forming trenches adjacent the DRAM cell and a silicon-oxy-nitride isolation liner on either side of the DRAM cell, adjacent the gate conductor. Isolation regions are then formed in the trenches on either side of the DRAM cell. Thereafter, the DRAM cell, including the boron-containing channel region adjacent the gate conductor, is subjected to elevated temperatures by thermal processing, for example, forming a support device on the substrate adjacent the isolation regions. The nitride-containing isolation liner reduces segregation of the boron in the channel region, as compared to an essentially nitrogen-free oxide-containing isolation liner.

90. 发明公开

EP1150349A3 Process for reduction of orientation-dependent oxidation in trench structures and semiconductor memory device produced thereby 审中-公开
标题翻译：一种用于定向相关的氧化在严重和结构及其制造的半导体存储器装置中的还原方法
公开(公告)号：EP1150349A3
公开(公告)日：2006-08-02
申请号：EP01110324.9
申请日：2001-04-26
申请人： Infineon Technologies North America Corp. , International Business Machines Corporation
发明人： Gruening von Schwerin, Ulrike , Jammy, Rajarao , Tews, Helmut H.
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10876 , H01L27/10864
摘要： A process for forming an oxide layer on a sidewall of a trench in a substrate. The process comprises the steps of forming the trench in the substrate, forming a nitride interface layer over a portion of the trench sidewall, forming an amorphous layer over the nitride interface layer, and oxidizing the amorphous layer to form the oxide layer. The process may be used, for example, to form a gate oxide for a vertical transistor, or an isolation collar. The invention also comprises a semiconductor memory device comprising a substrate, a trench in the substrate having a sidewall, an isolation collar comprising an isolation collar oxide layer on the trench sidewall in an upper region of the trench, and a vertical gate oxide comprising a gate oxide layer located on the trench sidewall above the isolation collar. The isolation collar oxide layer is disposed over an isolation collar nitride interface layer between the isolation collar oxide layer and the trench sidewall, the gate oxide layer is disposed over a gate nitride interface layer between the gate oxide layer and the trench sidewall, or both.

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