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    • 82. 发明专利
    • Ac coupling circuit
    • 交流耦合电路
    • JPS59165504A
    • 1984-09-18
    • JP3738083
    • 1983-03-09
    • Hitachi Ltd
    • MATSUI KAZUMASANAGASAWA KOUICHIMEGURO SATOSHI
    • H03F1/00H03F3/393
    • H03F3/393
    • PURPOSE:To shorten the power supply time by applying a DC bias with a variable resitance which can control its conduction with use of an intrinsic semiconductor itself as an FET and lowering the resistance value when the power is supplied. CONSTITUTION:The output of a circuit 1 of a preceding stage consisting of a switch S1 which is closed when the power is supplied, a signal power supply ei and a bias level power supply Ei is applied to a circuit 4 of a succeeding stage via a capacitor 2. A variable resistance 13 consisting of an FET of an intrinsic semiconductor is connected to the capacitor 2 at the side of the circuit 4. Then a pulse generator 23 is connected to the gate of the FET, and a pulse is generated when the power is supplied. Thus the FET conducts. Therefore the output of an AC coupling circuit, i.e. the input level of the circuit 4 is immediately set at an earth level to perform a normal operation.
    • 目的:通过施加可变电阻的直流偏置来缩短电源时间,可以通过使用本征半导体本身作为FET来控制其导通,并在供电时降低电阻值。 构成:由供电时闭合的开关S1,信号电源ei和偏置电平电源Ei构成的前级的电路1的输出经由a的后级施加到后级的电路4 由本征半导体的FET构成的可变电阻13与电路4侧的电容器2连接。然后,脉冲发生器23连接到FET的栅极,当脉冲发生器23 供电。 因此FET导通。 因此,AC耦合电路的输出,即电路4的输入电平立即设置在地电平以执行正常操作。