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1. 发明授权

US09678890B2 Synchronizing a translation lookaside buffer with an extended paging table 有权
公开(公告)号：US09678890B2
公开(公告)日：2017-06-13
申请号：US14867025
申请日：2015-09-28
申请人： Intel Corporation
发明人： Steven M. Bennett , Andrew V. Anderson , Gilbert Neiger , Richard A Uhlig , Scott Dion Rodgers , Rajesh M. Sankaran , Camron Rust , Sebastian Schoenberg
IPC分类号： G06F12/10 , G06F12/1027 , G06F12/1009 , G06F12/1036 , G06F12/02 , G06F9/455 , G06F12/0875 , G06F12/1045
CPC分类号： G06F12/1027 , G06F9/3004 , G06F9/30076 , G06F9/45558 , G06F12/0246 , G06F12/0875 , G06F12/1009 , G06F12/1036 , G06F12/1054 , G06F2009/45583 , G06F2212/152 , G06F2212/2022 , G06F2212/452 , G06F2212/50 , G06F2212/65 , G06F2212/657 , G06F2212/68 , G06F2212/683 , G06F2212/7201
摘要： A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.

2. 发明授权

US09678878B2 Disabling cache portions during low voltage operations 有权
公开(公告)号：US09678878B2
公开(公告)日：2017-06-13
申请号：US13652480
申请日：2012-10-16
申请人： Christopher Wilkerson , Muhammad M. Khellah , Vivek De , Ming Zhang , Jaume Abella , Javier Carretero Casado , Pedro Chaparro Monferrer , Xavier Vera , Antonio Gonzalez
发明人： Christopher Wilkerson , Muhammad M. Khellah , Vivek De , Ming Zhang , Jaume Abella , Javier Carretero Casado , Pedro Chaparro Monferrer , Xavier Vera , Antonio Gonzalez
IPC分类号： G06F12/08 , G06F12/126 , G06F12/0864 , G06F12/0804 , G06F1/32
CPC分类号： G06F12/0864 , G06F1/3243 , G06F12/0804 , G06F2212/1028 , Y02D10/13 , Y02D10/152
摘要： Methods and apparatus relating to disabling one or more cache portions during low voltage operations are described. In some embodiments, one or more extra bits may be used for a portion of a cache that indicate whether the portion of the cache is capable at operating at or below Vccmin levels. Other embodiments are also described and claimed.

3. 发明授权

US09244855B2 Method, system, and apparatus for page sizing extension 有权
标题翻译：用于页面大小调整的方法，系统和设备
公开(公告)号：US09244855B2
公开(公告)日：2016-01-26
申请号：US11967868
申请日：2007-12-31
申请人： Ed Grochowski , Julio Gago , Roger Gramunt , Roger Espasa , Rolf Kassa
发明人： Ed Grochowski , Julio Gago , Roger Gramunt , Roger Espasa , Rolf Kassa
IPC分类号： G06F12/10 , G06F12/14
CPC分类号： G06F12/1009 , G06F12/0864 , G06F12/1027 , G06F12/109 , G06F12/145 , G06F2212/152 , G06F2212/6032 , G06F2212/652 , G06F2212/657 , G06F2212/68
摘要： A method, system, and apparatus may initialize a fixed plurality of page table entries for a fixed plurality of pages in memory, each page having a first size, wherein a linear address for each page table entry corresponds to a physical address and the fixed plurality of pages are aligned. A bit in each of the page table entries for the aligned pages may be set to indicate whether or not the fixed plurality of pages is to be treated as one combined page having a second page size larger than the first page size. Other embodiments are described and claimed.
摘要翻译：方法，系统和装置可以对存储器中固定的多个页面的固定的多个页表条目进行初始化，每个页面具有第一大小，其中每个页表条目的线性地址对应于物理地址，固定多个的页面对齐。可以将针对对齐的页面的每个页表条目中的一个位设置为指示固定的多个页面是否被视为具有大于第一页面大小的第二页面大小的一个组合页面。描述和要求保护其他实施例。

4. 发明授权

US09189230B2 Method and system to provide concurrent user-level, non-privileged shared resource thread creation and execution 有权
标题翻译：方法和系统提供并发用户级，非特权共享资源线程的创建和执行
公开(公告)号：US09189230B2
公开(公告)日：2015-11-17
申请号：US10816103
申请日：2004-03-31
申请人： Edward T. Grochowski , Hong Wang , John P. Shen , Perry H. Wang , Jamison D. Collins , James P. Held , Partha Kundu , Raya Leviathan , Tin-Fook Ngai
发明人： Edward T. Grochowski , Hong Wang , John P. Shen , Perry H. Wang , Jamison D. Collins , James P. Held , Partha Kundu , Raya Leviathan , Tin-Fook Ngai
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30003 , G06F9/30087 , G06F9/3009 , G06F9/30101 , G06F9/3013 , G06F9/384 , G06F9/3851
摘要： A method and system to provide user-level multithreading are disclosed. The method according to the present techniques comprises receiving programming instructions to execute one or more shared resource threads (shreds) via an instruction set architecture (ISA). One or more instruction pointers are configured via the ISA; and the one or more shreds are executed simultaneously with a microprocessor, wherein the microprocessor includes multiple instruction sequencers.
摘要翻译：公开了提供用户级多线程的方法和系统。根据本技术的方法包括接收经由指令集架构（ISA）执行一个或多个共享资源线程（碎片）的编程指令。一个或多个指令指针通过ISA配置; 并且一个或多个碎片与微处理器同时执行，其中微处理器包括多个指令定序器。

5. 发明授权

US09122624B2 Synchronizing a translation lookaside buffer with an extended paging table 有权
标题翻译：将翻译后备缓冲区与扩展分页表同步
公开(公告)号：US09122624B2
公开(公告)日：2015-09-01
申请号：US14517849
申请日：2014-10-18
申请人： Intel Corporation
发明人： Steven M. Bennett , Andrew V. Anderson , Gilbert Neiger , Richard Uhlig , Dion Rodgers , Rajesh M. Sankaran , Camron Rust , Sebastian Schoenberg
IPC分类号： G06F12/00 , G06F12/10
CPC分类号： G06F12/1027 , G06F9/3004 , G06F9/30076 , G06F9/45558 , G06F12/0246 , G06F12/0875 , G06F12/1009 , G06F12/1036 , G06F12/1054 , G06F2009/45583 , G06F2212/152 , G06F2212/2022 , G06F2212/452 , G06F2212/50 , G06F2212/65 , G06F2212/657 , G06F2212/68 , G06F2212/683 , G06F2212/7201
摘要： A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.
摘要翻译：一种处理器，包括执行指令以使来自基于虚拟化的系统的客户机的物理地址（客户物理地址）到基于虚拟化系统的主机的物理地址（主机物理地址）的映射同步的指令，并且存储在翻译后备缓冲器（TLB），其中相应的映射存储在基于虚拟化的系统的扩展分页表（EPT）中。

6. 发明授权

US08914800B2 Behavioral model based multi-threaded architecture 有权
标题翻译：基于行为模型的多线程架构
公开(公告)号：US08914800B2
公开(公告)日：2014-12-16
申请号：US12611919
申请日：2009-11-03
申请人： Hong Jiang , Thomas A. Piazza
发明人： Hong Jiang , Thomas A. Piazza
IPC分类号： G06F9/46 , G06F9/30 , G06F9/48 , G06F9/52
CPC分类号： G06F9/52 , G06F9/3004 , G06F9/30087 , G06F9/4843
摘要： Multiple parallel passive threads of instructions coordinate access to shared resources using “active” and “proactive” semaphores. The active semaphores send messages to execution and/or control circuitry to cause the state of a thread to change. A thread can be placed in an inactive state by a thread scheduler in response to an unresolved dependency, which can be indicated by a semaphore. A thread state variable corresponding to the dependency is used to indicate that the thread is in inactive mode. When the dependency is resolved a message is passed to control circuitry causing the dependency variable to be cleared. In response to the cleared dependency variable the thread is placed in an active state. Execution can proceed on the threads in the active state. A proactive semaphore operates in a similar manner except that the semaphore is configured by the thread dispatcher before or after the thread is dispatched to the execution circuitry for execution.
摘要翻译：指令的多个并行被动线程使用“主动”和“主动”信号量协调对共享资源的访问。主动信号量将消息发送到执行和/或控制电路，以使线程的状态发生变化。线程调度程序可以响应未解决的依赖关系将线程置于无效状态，这可以由信号量指示。与依赖关系对应的线程状态变量用于指示线程处于非活动模式。当依赖关系被解析时，消息被传递给控制电路，导致依赖变量被清除。响应于清除的依赖变量，线程处于活动状态。处于活动状态的线程可执行。主动信号量以类似的方式运行，除了信号量由线程分派器在线程发送到执行电路执行之前或之后配置。

7. 发明授权

US08819394B2 Instruction and logic for processing text strings 有权
标题翻译：用于处理文本字符串的指令和逻辑
公开(公告)号：US08819394B2
公开(公告)日：2014-08-26
申请号：US13721725
申请日：2012-12-20
申请人： Intel Corporation
发明人： Michael A. Julier , Jeffrey D. Gray , Srinivas Chennupaty , Sean P. Mirkes , Mark P. Seconi
IPC分类号： G06F7/06 , G06F9/30 , G06F9/38
CPC分类号： G06F9/30145 , G06F7/06 , G06F9/30 , G06F9/3001 , G06F9/30021 , G06F9/30029 , G06F9/30036 , G06F9/30098 , G06F9/30109 , G06F9/3013 , G06F9/30167 , G06F9/3017 , G06F9/30185 , G06F9/30192 , G06F9/34 , G06F9/3802 , G06F9/3824 , G06F9/3853 , G06F9/3885 , G06F9/3887 , G06F12/0875 , G06F2212/452
摘要： Methods, apparatus, and instructions for performing string comparison operations. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store a result of a comparison between each data element of a first and second operand corresponding to a first and second text string, respectively.
摘要翻译：用于执行字符串比较操作的方法，装置和指令。在一个实施例中，一种装置包括执行第一指令的执行资源。响应于第一指令，所述执行资源分别存储对应于第一和第二文本串的第一和第二操作数的每个数据元素之间的比较结果。

8. 发明授权

US08745119B2 Processor for performing multiply-add operations on packed data 失效
公开(公告)号：US08745119B2
公开(公告)日：2014-06-03
申请号：US13801335
申请日：2013-03-13
申请人： Intel Corporation
发明人： Alexander Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf C. Witt
IPC分类号： G06F7/38
CPC分类号： G06F7/60 , G06F7/4812 , G06F7/49921 , G06F7/5324 , G06F7/5338 , G06F7/5443 , G06F9/3001 , G06F9/30036 , G06F9/30112 , G06F15/7817 , G06F17/10 , G06F17/147 , G06F17/16 , G06F2207/3828 , G06T1/20
摘要： A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.

9. 发明授权

US08694976B2 Sleep state mechanism for virtual multithreading 有权
标题翻译：虚拟多线程的休眠状态机制
公开(公告)号：US08694976B2
公开(公告)日：2014-04-08
申请号：US10742707
申请日：2003-12-19
申请人： Nicholas G. Samra
发明人： Nicholas G. Samra
IPC分类号： G06F9/44
CPC分类号： G06F9/485 , G06F9/3851
摘要： Method, apparatus and system embodiments provide support for multiple SoEMT software threads on multiple SMT logical thread contexts. A sleep state mechanism maintains a current value of an element of architecture state for each physical thread. The current value corresponds to an active virtual thread currently running on the physical thread. The sleep state mechanism also maintains sleep values of the architecture state element for each inactive thread. The active and inactive values may be maintained in a cross-bar configuration. Upon a read of the architecture state element, simplified mux logic selects among the current values to provide the current value for the appropriate active thread. Upon a thread switch, control logic associated with the sleep state mechanism swaps the active state value for the current thread with the inactive state value for the new thread.
摘要翻译：方法，装置和系统实施例提供对多个SMT逻辑线程上下文上的多个SoEMT软件线程的支持。休眠状态机制维护每个物理线程的架构状态元素的当前值。当前值对应于当前在物理线程上运行的活动虚拟线程。睡眠状态机制还为每个非活动线程维护体系结构状态元素的睡眠值。活动和非活动值可以保持在横杆配置中。在读取体系结构状态元素之后，简化的多路复用逻辑在当前值之间进行选择，以提供适当活动线程的当前值。在线程切换时，与休眠状态机制相关联的控制逻辑将为当前线程的活动状态值与新线程的非活动状态值进行交换。

10. 发明授权

US08694758B2 Mixing instructions with different register sizes 有权
标题翻译：混合使用不同寄存器大小的指令
公开(公告)号：US08694758B2
公开(公告)日：2014-04-08
申请号：US11965667
申请日：2007-12-27
申请人： Doron Orenstien , Zeev Sperber , Robert Valentine , Benny Eitan
发明人： Doron Orenstien , Zeev Sperber , Robert Valentine , Benny Eitan
IPC分类号： G06F9/34
CPC分类号： G06F9/30043 , G06F9/30036 , G06F9/30112 , G06F9/30181 , G06F9/3824 , G06F9/3885
摘要： When legacy instructions, that can only operate on smaller registers, are mixed with new instructions in a processor with larger registers, special handling and architecture are used to prevent the legacy instructions from causing problems with the data in the upper portion of the registers, i.e., the portion that they cannot directly access. In some embodiments, the upper portion of the registers are saved to temporary storage while the legacy instructions are operating, and restored to the upper portion of the registers when the new instructions are operating. A special instruction may also be used to disable this save/restore operation if the new instruction are not going to use the upper part of the registers.
摘要翻译：当只能在较小寄存器上运行的传统指令与具有较大寄存器的处理器中的新指令混合时，使用特殊处理和架构来防止遗留指令在寄存器上部的数据引起问题，即，他们不能直接访问的部分。在一些实施例中，当旧指令正在操作时，寄存器的上部保存到临时存储器中，并且当新指令正在操作时将寄存器的上部部分恢复到寄存器的上部。如果新指令不会使用寄存器的上半部分，也可以使用特殊指令禁用此保存/恢复操作。

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