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    • 9. 发明专利
    • Output circuit, and chip
    • 输出电路和芯片
    • JP2009022054A
    • 2009-01-29
    • JP2008269125
    • 2008-10-17
    • Cirrus Logic Incシーラス ロジック,インコーポレイテッドCirrus Logic,Inc.
    • KASHMIRI ABDUALASSAR MAHMUD
    • H02J1/00H03K19/0185G05F3/24H03K19/003H03K19/0175
    • H03K19/018521H03K19/00315
    • PROBLEM TO BE SOLVED: To provide an output circuit capable of generating an output signal with a relatively high voltage level from a chip manufactured by a process in a relatively low voltage level.
      SOLUTION: The output circuit has a control-signal logic circuit, a pseudo-ground generating circuit, and an output-signal generating circuit. The control-signal logic circuit receives three-volt data signals from an internal logic circuit in the chip, and generates a control signal as the function of these three-volt data signals. The pseudo-ground generating circuit is connected to the control-signal logic circuit to generate the pseudo-ground level higher than a zero volt and an intermediate output signal, as the function of the control signal generated by the control-signal logic circuit. The output-signal generating circuit is connected to the pseudo-ground generating circuit to generate a five-volt output signal, as the function of the intermediate output signal generated by the pseudo-ground generating circuit. A difference in voltage level in a semiconductor device inside the output circuit always shows below five volt due to generation of the pseudo-ground level.
      COPYRIGHT: (C)2009,JPO&INPIT
    • 要解决的问题:提供一种输出电路,其能够从由相对低电压电平的处理制造的芯片产生具有相对高的电压电平的输出信号。 解决方案:输出电路具有控制信号逻辑电路,伪地产生电路和输出信号发生电路。 控制信号逻辑电路从芯片中的内部逻辑电路接收三伏数据信号,并产生作为这三个三伏数据信号的函数的控制信号。 伪地产生电路连接到控制信号逻辑电路,以产生比零电压和中间输出信号高的伪地电平,作为由控制信号逻辑电路产生的控制信号的函数。 输出信号发生电路连接到伪地产生电路,以产生五伏输出信号,作为由伪地产生电路产生的中间输出信号的函数。 输出电路内部的半导体器件的电压电平差异由于产生伪地电平总是低于五伏。 版权所有(C)2009,JPO&INPIT
    • 10. 发明专利
    • Concurrent row/column syndrome generator for product code
    • 产品代码的同步线/列综合征发生器
    • JP2008148334A
    • 2008-06-26
    • JP2007329363
    • 2007-12-20
    • Cirrus Logic Incシーラス ロジック,インコーポレイテッドCirrus Logic,Inc.
    • AU FREDERICK SIU-HUANGYOON TONY JIHYUNKATO KEISUKEZOOK CHRISTOPHER P
    • H03M13/29G06F11/10G11B20/18H03M13/15
    • H03M13/1515G11B20/18G11B20/1833H03M13/29H03M13/2909
    • PROBLEM TO BE SOLVED: To provide an efficient error correction processor for correcting a multi-dimensional code comprising a first set of codewords that intersect with a second set of codewords.
      SOLUTION: The error correction is carried out by performing iterative passes over the first and second sets of codewords. The individual codewords are corrected using error syndromes which are computed as a function of the codeword data. In the preferred embodiment, the individual codewords are encoded according to a Reed-Solomon code and the error syndromes are computed as the modulo division of the codeword polynomial by the factors of a generator polynomial. To increase the throughput of the error correction processor, a syndrome buffer is employed to facilitate generating the error syndromes for both the first and second sets of codewords concurrently. In this manner, after a pass over the first set of codewords, the error syndromes for the second set of codewords are available for immediate processing.
      COPYRIGHT: (C)2008,JPO&INPIT
    • 要解决的问题:提供一种用于校正包括与第二组码字相交的第一组码字的多维码的有效纠错处理器。 解决方案:通过在第一组和第二组码字上进行迭代过程来进行纠错。 使用作为码字数据的函数计算的误差综合征校正各个码字。 在优选实施例中,根据Reed-Solomon码对各个码字进行编码,并且通过生成多项式的因子,计算错误校正子作为码字多项式的模除。 为了增加纠错处理器的吞吐量,采用校正子缓冲器以便于同时产生第一和第二组码字的错误综合征。 以这种方式,在经过第一组码字之后,用于第二组码字的错误综合征可用于立即处理。 版权所有(C)2008,JPO&INPIT