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1. 发明授权

US08458464B2 Mechanism to handle events in a machine with isolated execution 有权
公开(公告)号：US08458464B2
公开(公告)日：2013-06-04
申请号：US12869639
申请日：2010-08-26
申请人： Francis X. McKeen , Lawrence O. Smith , Benjamin Crawford Chaffin , Michael P. Cornaby , Bryant Bigbee
发明人： Francis X. McKeen , Lawrence O. Smith , Benjamin Crawford Chaffin , Michael P. Cornaby , Bryant Bigbee
IPC分类号： G06F21/00
CPC分类号： G06F21/74 , G06F12/145 , G06F12/1491 , G06F21/52 , G06F21/53
摘要： A platform and method for secure handling of events in an isolated environment. A processor executing in isolated execution “IsoX” mode may leak data when an event occurs as a result of the event being handled in a traditional manner based on the exception vector. By defining a class of events to be handled in IsoX mode, and switching between a normal memory map and an IsoX memory map dynamically in response to receipt of an event of the class, data security may be maintained in the face of such events.

2. 发明申请

US20100050266A1 Providing Extended Memory Protection 有权
标题翻译：提供扩展内存保护
公开(公告)号：US20100050266A1
公开(公告)日：2010-02-25
申请号：US12606408
申请日：2009-10-27
申请人： Antonio S. Cheng , Francis X. McKeen
发明人： Antonio S. Cheng , Francis X. McKeen
IPC分类号： G06F12/14 , G06F21/00 , G06F12/10
CPC分类号： G06F12/145 , G06F12/1063
摘要： In one embodiment, the present invention provides for extended memory protection for memory of a system. The embodiment includes a method for associating a protection indicator of a protection record maintained outside of an application's data space with a memory location, and preventing access to the memory location based on the status of the protection indicator. In such manner, more secure operation is provided, as malicious code or other malware is prevented from accessing protected memory locations. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明提供用于系统的存储器的扩展存储器保护。该实施例包括一种用于将维护在应用程序的数据空间外部的保护记录的保护指示符与存储器位置相关联的方法，以及基于保护指示符的状态来阻止对存储器位置的访问。以这种方式，提供更安全的操作，因为防止恶意代码或其他恶意软件访问受保护的存储器位置。描述和要求保护其他实施例。

3. 发明授权

US07389427B1 Mechanism to secure computer output from software attack using isolated execution 有权
标题翻译：使用隔离执行来保护软件攻击的计算机输出的机制
公开(公告)号：US07389427B1
公开(公告)日：2008-06-17
申请号：US09672367
申请日：2000-09-28
申请人： Francis X. McKeen , Ken Reneris , David W. Grawrock
发明人： Francis X. McKeen , Ken Reneris , David W. Grawrock
IPC分类号： G06F12/14
CPC分类号： G06F12/1433 , G06F21/78 , G06F2221/2105
摘要： A method and platform for maintaining the security of output data in an isolated execution environment. A system memory has an isolated output area readable only by secure output controllers having an isolated execution mode. The output controllers may make a request for access to the isolated output area, upon proper authentication if the request access is granted. The output device may either DMA the content of the isolated output area to an output end point, such as a display, or load it into local storage, the security of which is guaranteed by the controller.
摘要翻译：一种用于在独立执行环境中维护输出数据的安全性的方法和平台。系统存储器具有仅由具有隔离执行模式的安全输出控制器可读的隔离输出区域。如果请求访问被授权，输出控制器可以在进行适当认证时请求访问隔离的输出区域。输出设备可以将隔离输出区域的内容DMA传输到诸如显示器的输出端点，或将其加载到本地存储器中，其安全性由控制器保证。

4. 发明申请

US20080059711A1 Method and apparatus for preventing software side channel attacks 有权
标题翻译：防止软件侧信道攻击的方法和装置
公开(公告)号：US20080059711A1
公开(公告)日：2008-03-06
申请号：US11513871
申请日：2006-08-31
申请人： Francis X. McKeen , Leena K. Puthiyedath , Ernie Brickell , James B. Crossland
发明人： Francis X. McKeen , Leena K. Puthiyedath , Ernie Brickell , James B. Crossland
IPC分类号： G06F12/00
CPC分类号： G06F21/79 , G06F12/0804 , G06F12/0848 , G06F12/0891 , G06F12/126 , G06F12/1416 , G06F21/556
摘要： A method for managing a cache is disclosed. A context switch is identified. It is determined whether an application running after the context switch requires protection. Upon determining that the application requires protection the cache is partitioned. According to an aspect of the present invention, a partitioned section of the cache is completely over written with data associated with the application. Other embodiments are described and claimed.
摘要翻译：公开了一种用于管理高速缓存的方法。识别上下文切换。确定在上下文切换后运行的应用程序是否需要保护。在确定应用程序需要保护时，缓存被分区。根据本发明的一个方面，高速缓存的分区部分完全被写入与应用相关的数据。描述和要求保护其他实施例。

5. 发明授权

US07194634B2 Attestation key memory device and bus 有权
标题翻译：证明密钥存储设备和总线
公开(公告)号：US07194634B2
公开(公告)日：2007-03-20
申请号：US09672602
申请日：2001-02-26
申请人： Carl M. Ellison , Roger A. Golliver , Howard C. Herbert , Derrick C. Lin , Francis X. McKeen , Gilbert Neiger , Ken Reneris , James A. Sutton , Shreekant S. Thakkar , Millind Mittal
发明人： Carl M. Ellison , Roger A. Golliver , Howard C. Herbert , Derrick C. Lin , Francis X. McKeen , Gilbert Neiger , Ken Reneris , James A. Sutton , Shreekant S. Thakkar , Millind Mittal
IPC分类号： G06F11/30
CPC分类号： G06F12/1491 , G06F21/57 , G06F2221/2105
摘要： In an embodiment of the present invention, a technique is provided for remote attestation. An interface maps a device via a bus to an address space of a chipset in a secure environment for an isolated execution mode. The secure environment is associated with an isolated memory area accessible by at least one processor. The at least one processor operates in one of a normal execution mode and the isolated execution mode. A communication storage corresponding to the address space allows the device to exchange security information with the at least one processor in the isolated execution mode in a remote attestation.
摘要翻译：在本发明的实施例中，提供了用于远程证明的技术。接口将设备通过总线映射到安全环境中的芯片组的地址空间，用于隔离执行模式。安全环境与由至少一个处理器可访问的隔离存储器区域相关联。所述至少一个处理器以正常执行模式和隔离执行模式之一进行操作。对应于地址空间的通信存储器允许设备在远程证明中以隔离执行模式与至少一个处理器交换安全信息。

6. 发明授权

US06957332B1 Managing a secure platform using a hierarchical executive architecture in isolated execution mode 有权
标题翻译：在隔离执行模式下使用分层执行体系管理安全平台
公开(公告)号：US06957332B1
公开(公告)日：2005-10-18
申请号：US09539344
申请日：2000-03-31
申请人： Carl M. Ellison , Roger A. Golliver , Howard C. Herbert , Derrick C. Lin , Francis X. McKeen , Gilbert Neiger , Ken Reneris , James A. Sutton , Shreekant S. Thakkar , Milland Mittal
发明人： Carl M. Ellison , Roger A. Golliver , Howard C. Herbert , Derrick C. Lin , Francis X. McKeen , Gilbert Neiger , Ken Reneris , James A. Sutton , Shreekant S. Thakkar , Milland Mittal
IPC分类号： G06F12/14 , G06F15/00 , G06F21/00 , H04L9/00
CPC分类号： G06F12/1491 , G06F21/57 , G06F21/74
摘要： A processor executive (PE) handles an operating system executive (OSE) in a secure environment. The secure environment has a fused key (FK) and is associated with an isolated memory area in the platform. The OSE manages a subset of an operating system (OS) running on the platform. The platform has a processor operating in one of a normal execution mode and an isolated execution mode. The isolated memory area is accessible to the processor in the isolated execution mode. A PE supplement supplements the PE with a PE manifest representing the PE and a PE identifier to identify the PE. A PE handler handles the PE using the FK and the PE supplement.
摘要翻译：处理器执行（PE）在安全环境中处理操作系统执行程序（OSE）。安全环境具有融合密钥（FK），并且与平台中的隔离存储器区域相关联。 OSE管理在平台上运行的操作系统（OS）的子集。该平台具有以正常执行模式和隔离执行模式之一操作的处理器。在隔离的执行模式下，处理器可以访问隔离的内存区域。 PE补充用PE代替PE补充PE，PE标识符用于标识PE。 PE处理程序使用FK和PE补充来处理PE。

7. 发明授权

US06941458B1 Managing a secure platform using a hierarchical executive architecture in isolated execution mode 有权
标题翻译：在隔离执行模式下使用分层执行体系管理安全平台
公开(公告)号：US06941458B1
公开(公告)日：2005-09-06
申请号：US09668585
申请日：2000-09-22
申请人： Carl M. Ellison , Roger A. Golliver , Howard C. Herbert , Derrick C. Lin , Francis X. McKeen , Gilbert Neiger , Ken Reneris , James A. Sutton , Shreekant S. Thakkar , Milland Mittal
发明人： Carl M. Ellison , Roger A. Golliver , Howard C. Herbert , Derrick C. Lin , Francis X. McKeen , Gilbert Neiger , Ken Reneris , James A. Sutton , Shreekant S. Thakkar , Milland Mittal
IPC分类号： G06F12/14 , G06F15/00 , G06F21/00 , H04L9/00
CPC分类号： G06F12/1491 , G06F21/57 , G06F21/74
摘要： A processor executive (PE) handles an operating system executive (OSE) in a secure environment. The secure environment has a platform key (PK) and is associated with an isolated memory area in the platform. The OSE manages a subset of an operating system (OS) running on the platform. The platform has a processor operating in one of a normal execution mode and an isolated execution mode. The isolated memory area is accessible to the processor in the isolated execution mode. A PE supplement supplements the PE with a PE manifest representing the PE and a PE identifier to identify the PE. A PE handler handles the PE using the PK and the PE supplement.
摘要翻译：处理器执行（PE）在安全环境中处理操作系统执行程序（OSE）。安全环境具有平台密钥（PK），并且与平台中的隔离存储器区域相关联。 OSE管理在平台上运行的操作系统（OS）的子集。该平台具有以正常执行模式和隔离执行模式之一操作的处理器。在隔离的执行模式下，处理器可以访问隔离的内存区域。 PE补充用PE代替PE补充PE，PE标识符用于标识PE。 PE处理程序使用PK和PE补充来处理PE。

8. 发明授权

US06754815B1 Method and system for scrubbing an isolated area of memory after reset of a processor operating in isolated execution mode if a cleanup flag is set 有权
标题翻译：如果设置了清除标志，则在分离执行模式下操作的处理器复位后，擦除存储器隔离区域的方法和系统
公开(公告)号：US06754815B1
公开(公告)日：2004-06-22
申请号：US09618659
申请日：2000-07-18
申请人： Carl M. Ellison , Roger A. Golliver , Howard C. Herbert , Derrick C. Lin , Francis X. McKeen , Gilbert Neiger , Ken Reneris , James A. Sutton , Shreekant S. Thakkar , Millind Mittal
发明人： Carl M. Ellison , Roger A. Golliver , Howard C. Herbert , Derrick C. Lin , Francis X. McKeen , Gilbert Neiger , Ken Reneris , James A. Sutton , Shreekant S. Thakkar , Millind Mittal
IPC分类号： G06F15177
CPC分类号： G06F21/74 , G06F9/4401 , G06F21/62 , G06F2221/2143
摘要： The present invention provides a method, apparatus, and system for invoking a reset process in response to a processor being individually reset. The reset processor operates within a platform in an isolated execution mode and is associated with an isolated area of memory. An initialization process is invoked for an initializing processor. The initialization process determines whether or not a cleanup flag is set. If the cleanup flag is set, the isolated area of memory is scrubbed. In one embodiment, when a last processor operating in the platform is reset, it is reset without clearing the cleanup flag. Subsequently, an initializing processor invokes the initialization process. The initialization process determines that the cleanup flag is set. The initialization process invokes the execution of a processor nub loader. If the cleanup flag is set, the processor nub loader scrubs the isolated area of memory and invokes a controlled close for the initializing processor. The controlled close clears the cleanup flag. The initializing processor then re-performs the initialization process. Upon the second iteration of the initialization process, with the cleanup flag not set, a new isolated area of memory is created for the initializing processor.
摘要翻译：本发明提供了一种响应于处理器被单独复位来调用复位过程的方法，装置和系统。复位处理器在孤立执行模式的平台内运行，并与存储器的隔离区域相关联。初始化处理器调用初始化过程。初始化过程确定是否设置清除标志。如果清除标志置位，则清除隔离区的内存。在一个实施例中，当在平台中操作的最后一个处理器被重置时，它被重置而不清除清除标志。随后，初始化处理器调用初始化过程。初始化过程确定清除标志被设置。初始化过程调用处理器nub加载器的执行。如果清除标志置位，则处理器nub加载器将擦除存储器的隔离区域，并为初始化处理器调用受控关闭。受控关闭清除清除标志。初始化处理器然后重新执行初始化过程。在初始化过程的第二次迭代时，在清除标志未设置的情况下，为初始化处理器创建一个新的隔离区域。

9. 发明授权

US5285323A Integrated circuit chip having primary and secondary random access memories for a hierarchical cache 失效
标题翻译：集成电路芯片，具有用于分级高速缓存的主和次级随机存取存储器
公开(公告)号：US5285323A
公开(公告)日：1994-02-08
申请号：US61273
申请日：1993-05-13
申请人： Ricky C. Hetherington , Francis X. McKeen , Joseph D. Marci , Tryggve Fossum , Joel S. Emer
发明人： Ricky C. Hetherington , Francis X. McKeen , Joseph D. Marci , Tryggve Fossum , Joel S. Emer
IPC分类号： G06F12/08
CPC分类号： G06F12/0897 , Y02B60/1225
摘要： A hierarchical cache memory includes a high-speed primary cache memory and a lower speed secondary cache memory of greater storage capacity than the primary cache memory. To manage a huge number of data lines interconnecting the primary and secondary cache memories, the hierarchical cache memory is integrated on a plurality of integrated circuits which include all of the interconnecting data lines. Each integrated circuit includes a primary memory and a secondary memory for storing and retrieving data transferred over a first data input line and a first data output line that link the primary memory to a central processing unit. At any given time, a multi-bit word is addressed in the secondary memory, and a corresponding multi-bit word is addressed in the primary memory. The primary and secondary memories are interconnected by a first multi-line bus for transferring a multi-bit word read from the secondary memory to the primary memory, and by a second multi-line bus for transferring a multi-bit word read from the primary memory to the secondary memory. The secondary memory is linked to a main memory by a second data output line and a second data input line for sequential transmission of bits to exchange multi-bit words during a writeback and refill operation. In a preferred embodiment, data inputs of the primary memory and the secondary memory are wired in parallel to a serial-parallel shift register that is used as a common write buffer.
摘要翻译：分级缓存存储器包括高于主高速缓冲存储器的高速主缓存存储器和比主高速缓存存储器更大存储容量的较低速次级高速缓冲存储器。为了管理互连主要和次要高速缓冲存储器的大量数据线，分层高速缓冲存储器集成在包括所有互连数据线的多个集成电路上。每个集成电路包括主存储器和辅助存储器，用于存储和检索通过第一数据输入线传送的数据和将主存储器链接到中央处理单元的第一数据输出线。在任何给定的时间，多位字在二级存储器中寻址，并且在主存储器中寻址相应的多位字。主存储器和次存储器通过第一多行总线互连，用于将从副存储器读取的多位字传送到主存储器，以及用于传送从主存储器读取的多位字的第二多行总线内存到二级内存。次存储器通过第二数据输出线和第二数据输入线链接到主存储器，用于在写回和再填充操作期间顺序传输位以交换多位字。在优选实施例中，主存储器和次存储器的数据输入与用作公共写入缓冲器的串行 - 并行移位寄存器并联布线。

10. 发明授权

US5109495A Method and apparatus using a source operand list and a source operand pointer queue between the execution unit and the instruction decoding and operand processing units of a pipelined data processor 失效
标题翻译：使用源操作列表的方法和装置和执行单元之间的源操作指针和管道解码和操作处理单元的管理数据处理器
公开(公告)号：US5109495A
公开(公告)日：1992-04-28
申请号：US306843
申请日：1989-02-03
申请人： David B. Fite , Tryggve Fossum , William R. Grundmann , Dwight P. Manely , Francis X. McKeen , John E. Murray , Ronald M. Salett , Eileen Samberg , Daniel P. Stirling
发明人： David B. Fite , Tryggve Fossum , William R. Grundmann , Dwight P. Manely , Francis X. McKeen , John E. Murray , Ronald M. Salett , Eileen Samberg , Daniel P. Stirling
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30167 , G06F9/30145 , G06F9/3016 , G06F9/3824 , G06F9/3867
摘要： To execute variable-length instructions independently of instruction preprocessing, a central processing unit is provided with a set of queues in the data and control paths between an instruction unit and an execution unit. The queues include a "fork" queue, a source queue, a destination queue, and a program counter queue. The fork queue contains an entry of control information for each instruction processed by the instruction unit. This control information corresponds to the opcode for the instruction, and preferably it is a microcode "fork" address at which a microcode execution unit begins execution to execute the instruction. The source queue specifies the source operands for the instruction. Preferably the source queue stores source pointers and the operands themselves are included in a separate "source list" in the case of operands fetched from memory or immediate data from the instruction stream, or are the contents of a set of general purpose registers in the execution unit. The destination queue specifies the destination for the instruction, for example, either memory or general purpose registers. The program counter queue contains the starting value of the program counter for each of the instructions passed from the instruction unit to the execution unit. Preferably the queues are large enough to hold control information and data for up to six instructions. The queues therefore shield the execution unit and the instruction unit from each others complexities and provide a buffer to allow for an uneven processing rate in either of them.

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