专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2020108738A1 INSTRUCTION LIST GENERATION 审中-公开
公开(公告)号：WO2020108738A1
公开(公告)日：2020-06-04
申请号：PCT/EP2018/082661
申请日：2018-11-27
申请人： RENESAS ELECTRONICS CORPORATION , RENESAS ELECTRONICS EUROPE GMBH
发明人： TOSCHI, Bjoern
IPC分类号： G06T17/20 , G06T1/60
摘要： A system for and a method of generating an ordered list of instructions comprising a list of pixel coordinates which are vertices (53) of triangles (51) in a strip (50) of a reference input image (33'; Fig. 11) in a source coordinate system (30; Fig. 11) such that transformation of the vertices to a corresponding output image (33; Fig. 10) in a destination coordinate system (32; Fig.11) causes the triangles to be mapped to a block (47) of image data which maps to a block of line memory (or "texture cache"). The method comprises dividing the reference output image into a plurality of tiled sections (35; Fig. 11) in the destination coordinate system. The method comprises, for each section, defining first and second boundaries of an array of strips (50) of pixels (46) in the section by dividing the section into blocks of line memory. The method comprises, for each strip, dividing each set of pixels contained in each strip into a series of ordered triangles, generating a set of destination and source coordinates for each vertex of each triangle in the strip and storing the coordinates of the vertices (53) in source and destination coordinate system (30, 32), in the ordered list of instructions.

2. 发明申请

WO2020038899A1 OSCILLATOR FREQUENCY ADJUSTMENT 审中-公开
公开(公告)号：WO2020038899A1
公开(公告)日：2020-02-27
申请号：PCT/EP2019/072168
申请日：2019-08-19
申请人： RENESAS ELECTRONICS CORPORATION , RENESAS ELECTRONICS EUROPE GMBH
发明人： LANGER, Volker , KATTWINKEL, Thomas
IPC分类号： H03L7/181
摘要： Oscillator circuitry is disclosed. The oscillator circuitry comprises a free-running oscillator (8) for generating pulses at a frequency, and a frequency adjustment circuit for adaptively adjusting the frequency of the free-running oscillator. The frequency adjustment circuit comprises a counter (15) configured to count a number (24) of pulses (22) generated by the free-running oscillator and logic (26) configured to compare the number of pulses with an expected number (25) of pulses (corresponding to a target frequency) to determine a difference value (29) and to adjust the frequency of the free-running oscillator in dependence on the difference value. The frequency adjustment circuit is configured, in response to receiving a synchronisation pulse (4; Fig. 3), to trigger an update of the number of pulses to be compared.

3. 发明申请

WO2019145028A1 TIME-SENSITIVE NETWORKING 审中-公开
公开(公告)号：WO2019145028A1
公开(公告)日：2019-08-01
申请号：PCT/EP2018/051681
申请日：2018-01-24
申请人： RENESAS ELECTRONICS CORPORATION , RENESAS ELECTRONICS EUROPE GMBH
发明人： MARDMOELLER, Christian , HOFFLEIT, Thorsten
IPC分类号： H04L12/815 , H04L12/863
摘要： A network device (1) comprising a set of queues (2) and a time-aware shaper (3) which comprises a set of transmission gates (4) and gate control instructions (5; Fig. 5). The gate control list comprises a set of individual gate control lists (7), each individual gate control list configured to control a respective gate and which comprises a sequence of entries (10), each entry comprising a duration of time (11; Fig. 11).

4. 发明申请

WO2018014965A1 OPEN LOAD DIAGNOSIS 审中-公开
标题翻译：开放负载诊断
公开(公告)号：WO2018014965A1
公开(公告)日：2018-01-25
申请号：PCT/EP2016/067463
申请日：2016-07-21
申请人： RENESAS ELECTRONICS CORPORATION , RENESAS ELECTRONICS EUROPE GMBH
发明人： BRAUN, Hans-Juergen
IPC分类号： G01R27/16 , G01R31/02 , G01R31/04
摘要： A device (10) for open load diagnosis of a signal line (4) in a digital system in which a logic state is represented by a band of voltages (20, 21) lying between first and second voltage limits is described. The device is configured to cause the signal line to reach a first, stable voltage lying in the band, to apply a second, different voltage to the signal line lying in the band and without leaving the band, to perform a time constant dependent measurement so as to determine a value of a parameter which is or depends on resistance of a load between the signal line and a reference line, to compare the value of the parameter with a reference value of the parameter and, in dependence on comparison, to signal the result.
摘要翻译：一种用于数字系统中的信号线（4）的开路负载诊断的装置（10），其中逻辑状态由位于第一和第二之间的电压带（20,21）表示描述电压限制。该装置被配置为使信号线达到位于频带中的第一稳定电压，以向位于频带中且不离开频带的信号线施加第二不同电压以执行时间常数相关测量，以便以确定参数的值，该参数取决于信号线和参考线之间的负载的阻抗，将参数的值与参数的参考值进行比较，并且根据比较结果来将信号结果

5. 发明申请

WO2016157246A1 DATA TRANSFER APPARATUS AND MICROCOMPUTER 审中-公开
标题翻译：数据传输设备和微型计算机
公开(公告)号：WO2016157246A1
公开(公告)日：2016-10-06
申请号：PCT/JP2015/001808
申请日：2015-03-30
申请人： RENESAS ELECTRONICS CORPORATION
发明人： LIESKE, Hanno
IPC分类号： G06T1/20
CPC分类号： G06T1/20
摘要： A two-row buffer (3) stores first and second rows. An input buffer (2) stores a third row. A gradient calculator (4) calculates first and second gradient values. A vote calculator (5) calculates a vote amount value. A direction calculator (6) calculates a vote direction value. An output buffer (8) stores accumulated vote amount values. An adder (7) adds the vote amount value to the received accumulated vote amount value and replaces the accumulated vote amount value in the output buffer (8) with the added value. The first gradient value is a difference between values of two pixels in the first and third row. The second gradient value is a difference between values of two pixels in the second row. The four pixels are immediately adjacent to a target pixel in the second row. The output buffer (8) outputs all of the accumulated vote amount values to an outside processor.
摘要翻译：两行缓冲器（3）存储第一行和第二行。输入缓冲器（2）存储第三行。梯度计算器（4）计算第一和第二梯度值。投票计算器（5）计算投票金额值。方向计算器（6）计算投票方向值。输出缓冲器（8）存储累积投票数值。加法器（7）将投票金额值添加到接收到的累计投票金额值，并用附加值代替输出缓冲器（8）中的积累投票金额值。第一个梯度值是第一行和第三行中两个像素的值之间的差值。第二梯度值是第二行中两个像素的值之间的差值。四个像素紧邻第二行中的目标像素。输出缓冲器（8）将所有积累的投票数值输出到外部处理器。

6. 发明申请

WO2019145040A1 CONTROLLING A HIGH-SIDE SWITCHING ELEMENT USING A BOOTSTRAP CAPACITOR 审中-公开
公开(公告)号：WO2019145040A1
公开(公告)日：2019-08-01
申请号：PCT/EP2018/051888
申请日：2018-01-25
申请人： RENESAS ELECTRONICS CORPORATION , RENESAS ELECTRONICS EUROPE GMBH
发明人： BRAUN, Hans-Juergen
IPC分类号： H03K17/06
CPC分类号： H03K17/063
摘要： A monolithic integrated circuit (1) for controlling a high-side switching element (2) for a load (3) using a bootstrap capacitor is disclosed. The integrated circuit comprises a first supply voltage input (7) for receiving a first input supply voltage (V 1 ), a second supply voltage input (8) for receiving a second, current-limited input supply voltage (V CP ), a voltage-sensing input (14) for receiving a source voltage, a first output (15) for providing a drive signal (V G ) to the switching element (2), a second output ( 16) for providing a charging signal (V BS ) to a bootstrap capacitor (17), a pre-driver (18) for generating the drive signal, the pre-driver having a voltage input (20 ) and an output (22) which is coupled to the first output, and a power supply control section (25) comprising first and second switches (28,29). The first and second switches (28, 29) are arranged in series between the first input (7) and the second output ( 16), the second input ( 8 ) is coupled to a node (34) between the first and second switches (29), and the second node (34) is coupled to a voltage input (20 ) of the pre-driver. The first and second switches are selectively operable following switching of the switching element from an ON state to an OFF state and in response to a determination that the source voltage is below a predetermined level, to decouple the second output (16) and in response to determination that the source voltage is above the predetermined level to couple the second output (16) to the second output (16).

7. 发明申请

WO2019134762A1 DESIGN SUPPORT SYSTEM AND METHOD 审中-公开
公开(公告)号：WO2019134762A1
公开(公告)日：2019-07-11
申请号：PCT/EP2018/050384
申请日：2018-01-08
申请人： RENESAS ELECTRONICS CORPORATION , RENESAS ELECTRONICS EUROPE GMBH
发明人： CEFALO, Agostino , VINCELLI, Riccardo
IPC分类号： G06F11/00 , G06F17/50
摘要： A computer-implemented method of generating functional safety data for a design of an electronic component comprising a plurality of elements is disclosed. The method comprises receiving attribute data (12, 13, 17, 50) for a plurality of elements comprises in an electronic component, such as a microcontroller. The attribute data comprise element data (17) for the plurality of elements, wherein element data for a given element (130) include an identity (131) of the given element and a failure rate characteristic (135) for the given element. The attribute data comprise functionality data (50) for a plurality of element functionalities, wherein functionality data for a given element functionality (140) include an identity (142) of a use case, an identity (144) of an element, an identity (146) of a fault characterisation for providing information about one or more fault models and a configurable data (148) for controlling selection and use of the given functionality data when generating the functional safety data. The method also comprises generating the functional safety data (14; Fig. 1) using the attribute data and storing a report (6; Fig. 1) including the functional safety data.

8. 发明申请

WO2019024976A1 OFFSET CANCELLATION 审中-公开
公开(公告)号：WO2019024976A1
公开(公告)日：2019-02-07
申请号：PCT/EP2017/069333
申请日：2017-07-31
申请人： RENESAS ELECTRONICS CORPORATION , RENESAS ELECTRONICS EUROPE GMBH
发明人： NAGHED, Mohsen
IPC分类号： H03F1/30
摘要： Apparatus for performing offset cancellation is disclosed. The apparatus comprises a gating circuit (6) for receiving an analogue signal (3) from a source (2) and providing a gated analogue signal (9) to an analogue circuit (10), a gating controller (7; 14; Fig. 1) and a digital processor (14; Fig. 1) for receiving a digital signal (13) converted from an analogue output (11) from the analogue circuit (10). The gating circuit comprises at least one path (2), each path respectively comprising, an input terminal (22), an output terminal (23), a node (24) interposed between the input and output terminals, a first transistor (Q1) having a channel arranged between the input terminal and the node, and a second transistor (Q3) having channel arranged between the node and a fixed reference, such as ground (GND). The gating controller is configured, in a first time window (1A), to switch the first transistor so that the input terminal and the output terminal are decoupled and to switch the second transistor so that the node is coupled to the fixed reference. The gating controller is configured, in a second, different time window (1B), to switch the second transistor so that the node and the fixed reference are decoupled and to switch the first transistor so that the input terminal is coupled to the input terminal. The digital processor is configured, in the first time window, to take a first measurement of the digital signal, and, in the second, different time window, to take a second measurement of the digital signal. The digital processor configured to subtract the first measurement from the second measurement.

9. 发明申请

WO2018228658A1 ULTRASONIC FLOW MEASUREMENT 审中-公开
公开(公告)号：WO2018228658A1
公开(公告)日：2018-12-20
申请号：PCT/EP2017/064259
申请日：2017-06-12
申请人： RENESAS ELECTRONICS CORPORATION , RENESAS ELECTRONICS EUROPE GMBH
发明人： KLEINITZ, Axel , DALBY, Richard
IPC分类号： G01F1/66
摘要： An ultrasonic flow measurement system is disclosed. The system comprises a signal generator (32) configured to generate a first excitation signal (25) for a first ultrasonic transducer (9) and a second excitation signal (26) for a second, different ultrasonic transducer (10). The system comprises a phase differentiator (33) configured to generate a differential phase angle signal (34) indicative of a difference in phase angle between first and second receive signals (27, 28) received from the first and second transducers which is indicative of flow rate.

10. 发明申请

WO2020108731A1 PULSE-WIDTH MODULATION SIGNAL GENERATOR 审中-公开
公开(公告)号：WO2020108731A1
公开(公告)日：2020-06-04
申请号：PCT/EP2018/082562
申请日：2018-11-26
申请人： RENESAS ELECTRONICS CORPORATION , RENESAS ELECTRONICS EUROPE GMBH
发明人： LANGER, Volker
IPC分类号： H03L7/08 , H03K5/131
摘要： A pulse-width modulation signal generator (3) is described. The pulse-width modulation signal generator comprises an analogue delay-locked loop (7) which comprises a delay line (11) arranged to receive a clock signal (CLK SYS ), the delay line comprising a chain (12) of delay cells (13 1 , 13 2 , 13 3 , 13 4 , 13 n-1 , 13 n ) outputting a plurality of phases, a phase selector (17) for selecting a one of the plurality of phases as a selected phase signal (OUT PHASE ) in dependence upon a phase-selection signal (SEL PHASE ), and a delay controller (18) configured to compare respective phases of the clock signal and the last delay cell and to generate a delay control signal (Δ) for the delay cells in dependence thereon. The pulse-width modulation signal generator comprises a logic circuit (20) configured to receive the selected phase signal (OUT PHASE ) and a clock period-selecting signal (SEL PERIOD ) selecting a one clock period (8) in the clock period for a pulse-width modulation signal period, and to output the pulse-width modulation signal period having a rising edge or a falling edge (10) whose timing corresponds to an edge of the selected phase signal (OUT PHASE ) occurring in the one clock period.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式