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1. 发明授权

US08043947B2 Method to eliminate re-crystallization border defects generated during solid phase epitaxy of a DSB substrate 有权
标题翻译：消除在DSB衬底的固相外延期间产生的再结晶边界缺陷的方法
公开(公告)号：US08043947B2
公开(公告)日：2011-10-25
申请号：US11941187
申请日：2007-11-16
申请人： Angelo Pinto , Weize Xiong , Manfred Ramin
发明人： Angelo Pinto , Weize Xiong , Manfred Ramin
IPC分类号： H01L21/425
CPC分类号： H01L21/187 , H01L21/02532 , H01L21/02609 , H01L21/02667 , H01L21/76224
摘要： A method for semiconductor processing provides a DSB semiconductor body having a first crystal orientation, a second crystal orientation, and a border region disposed between the first and second crystal orientations. The border region further has a defect associated with an interface of the first crystal orientation and second the second crystal orientation, wherein the defect generally extends a distance into the semiconductor body from a surface of the body. A sacrificial portion of the semiconductor body is removed from the surface thereof, wherein removing the sacrificial portion at least partially removes the defect. The sacrificial portion can be defined by oxidizing the surface at low temperature, wherein the oxidation at least partially consumes the defect. The sacrificial portion can also be removed by CMP. An STI feature may be further formed over the defect after removal of the sacrificial portion, therein consuming any remaining defect.
摘要翻译：一种用于半导体处理的方法提供了具有第一晶体取向，第二晶体取向和设置在第一和第二晶体取向之间的边界区域的DSB半导体本体。边界区域还具有与第一晶体取向和第二晶体取向的界面相关联的缺陷，其中缺陷通常从身体的表面延伸到半导体本体中的距离。从其表面去除半导体本体的牺牲部分，其中去除牺牲部分至少部分地去除缺陷。牺牲部分可以通过在低温下氧化表面来限定，其中氧化至少部分地消耗缺陷。牺牲部分也可以通过CMP去除。在去除牺牲部分之后，可以在缺陷上进一步形成STI特征，其中消耗任何剩余的缺陷。

2. 发明授权

US07960234B2 Multiple-gate MOSFET device and associated manufacturing methods 有权
标题翻译：多栅MOSFET器件及相关制造方法
公开(公告)号：US07960234B2
公开(公告)日：2011-06-14
申请号：US11726516
申请日：2007-03-22
申请人： Craig Henry Huffman , Weize Xiong , Cloves Rinn Cleavelin
发明人： Craig Henry Huffman , Weize Xiong , Cloves Rinn Cleavelin
IPC分类号： H01L21/336
CPC分类号： H01L29/66795 , H01L29/785 , H01L29/7853
摘要： One embodiment of the present invention relates to a method of fabricating a multi-gate transistor. During the method a second gate electrode material is selectively removed from a semiconductor structure from which the multi-gate transistor is formed, thereby exposing at least one surface of a first gate electrode material. The exposed surface of the first gate electrode material is deglazed. Subsequently, the first gate electrode material is removed. Other methods and devices are also disclosed.
摘要翻译：本发明的一个实施例涉及一种制造多栅极晶体管的方法。在该方法期间，从形成多栅极晶体管的半导体结构中选择性地去除第二栅电极材料，从而暴露第一栅电极材料的至少一个表面。第一栅电极材料的暴露表面被去角质化。随后，去除第一栅电极材料。还公开了其它方法和装置。

3. 发明授权

US07683417B2 Memory device with memory cell including MuGFET and fin capacitor 有权
标题翻译：具有存储单元的存储器件包括MuGFET和鳍式电容器
公开(公告)号：US07683417B2
公开(公告)日：2010-03-23
申请号：US11924817
申请日：2007-10-26
申请人： Weize Xiong , Andrew Marshall , Cloves Rinn Cleavelin , Howard Lee Tigelaar
发明人： Weize Xiong , Andrew Marshall , Cloves Rinn Cleavelin , Howard Lee Tigelaar
IPC分类号： H01L27/108
CPC分类号： H01L29/94 , H01L27/10805 , H01L27/10823 , H01L27/10826 , H01L27/1085 , H01L28/60 , H01L29/785 , H01L29/7855
摘要： One embodiment of the present invention relates to a memory cell. The memory cell includes a multi-gate field effect transistor associated with a first region of a semiconductor fin. The memory cell also includes a fin capacitor coupled to a drain of the multi-gate field effect transistor and associated with a second region of the semiconductor fin, where the fin capacitor has an approximately degenerate doping concentration in the second region. Other devices and methods are also disclosed.
摘要翻译：本发明的一个实施例涉及一种存储单元。存储单元包括与半导体鳍片的第一区域相关联的多栅极场效应晶体管。存储单元还包括耦合到多栅极场效应晶体管的漏极并与半导体鳍片的第二区域相关联的散热片电容器，其中散热片电容器在第二区域中具有大致简并掺杂浓度。还公开了其它装置和方法。

4. 发明申请

US20090096055A1 METHOD TO FORM CMOS CIRCUITS WITH SUB 50NM STI STRUCTURES USING SELECTIVE EPITAXIAL SILICON POST STI ETCH 审中-公开
标题翻译：使用选择性外延硅片后蚀刻形成具有低于50Nm STI结构的CMOS电路的方法
公开(公告)号：US20090096055A1
公开(公告)日：2009-04-16
申请号：US12187958
申请日：2008-08-07
申请人： Clint L. Montgomery , Brian K. Kirkpatrick , Weize Xiong , Steven L. Prins
发明人： Clint L. Montgomery , Brian K. Kirkpatrick , Weize Xiong , Steven L. Prins
IPC分类号： H01L21/762 , H01L23/00
CPC分类号： H01L21/76232
摘要： An STI field oxide element in an IC which includes a layer of epitaxial semiconductor on sidewalls of the STI trench to increase the width of the active area adjacent to the STI trench and decrease a width of dielectric material in the STI trench is disclosed. STI etch residue is removed from the STI trench surface prior to growth of the epitaxial layer. The epitaxial semiconductor composition is matched to the composition of the adjacent active area. The epitaxial semiconductor may be undoped or doped to match the active area. The STI trench with the epitaxial layer is compatible with common STI passivation and fill processes. The thickness of the as-grown epitaxial semiconductor layer is selected to provide a desired active area width or a desired STI dielectric width.
摘要翻译：公开了一种IC中的STI场氧化物元件，其包括在STI沟槽的侧壁上的外延半导体层，以增加与STI沟槽相邻的有源区的宽度并减小STI沟槽中的介电材料的宽度。在外延层生长之前，STI蚀刻残留物从STI沟槽表面去除。外延半导体组合物与相邻有源区的组成相匹配。外延半导体可以是未掺杂的或掺杂的以匹配有源区。具有外延层的STI沟槽与常见的STI钝化和填充工艺兼容。选择生长的外延半导体层的厚度以提供期望的有源面积宽度或期望的STI电介质宽度。

5. 发明申请

US20080303095A1 VARYING MUGFET WIDTH TO ADJUST DEVICE CHARACTERISTICS 审中-公开
标题翻译：改变MUGFET宽度以调整设备特性
公开(公告)号：US20080303095A1
公开(公告)日：2008-12-11
申请号：US11759710
申请日：2007-06-07
申请人： Weize Xiong , Cloves Rinn Cleavelin
发明人： Weize Xiong , Cloves Rinn Cleavelin
IPC分类号： H01L29/76 , H01L21/8234
CPC分类号： H01L29/785 , H01L21/845 , H01L27/1211 , H01L2029/7857
摘要： One embodiment of the present invention relates to an integrated circuit that includes a first multi-gate transistor that has a first fin width and a first threshold voltage. The integrated circuit also includes a second multi-gate transistor that has a second fin width that is greater than the first width and a second threshold voltage that is less than the first threshold voltage. Other circuits and methods are also disclosed.
摘要翻译：本发明的一个实施例涉及一种集成电路，其包括具有第一鳍宽度和第一阈值电压的第一多栅极晶体管。集成电路还包括具有大于第一宽度的第二鳍宽度和小于第一阈值电压的第二阈值电压的第二多栅极晶体管。还公开了其它电路和方法。

6. 发明申请

US20070257319A1 INTEGRATING HIGH PERFORMANCE AND LOW POWER MULTI-GATE DEVICES 审中-公开
标题翻译：集成高性能和低功率多门设备
公开(公告)号：US20070257319A1
公开(公告)日：2007-11-08
申请号：US11381875
申请日：2006-05-05
申请人： Weize Xiong , Cloves Cleavelin
发明人： Weize Xiong , Cloves Cleavelin
IPC分类号： H01L21/84
CPC分类号： H01L27/1211 , H01L21/845 , H01L29/66795 , H01L29/785
摘要： A semiconductor device comprising a first multi-gate device and a second multi-gate device on a semiconductor substrate. The first multi-gate device comprising a first gate structure and the second multi-gate device comprises a second gate structure. An effective width of the first gate structure is greater than an effective width of the second gate structure.
摘要翻译：一种半导体器件，包括半导体衬底上的第一多栅极器件和第二多栅极器件。包括第一栅极结构和第二多栅极器件的第一多栅极器件包括第二栅极结构。第一栅极结构的有效宽度大于第二栅极结构的有效宽度。

7. 发明授权

US07238567B2 System and method for integrating low schottky barrier metal source/drain 有权
标题翻译：用于整合低肖特基势垒金属源/漏极的系统和方法
公开(公告)号：US07238567B2
公开(公告)日：2007-07-03
申请号：US10924079
申请日：2004-08-23
申请人： Weize Xiong
发明人： Weize Xiong
IPC分类号： H01L21/8242
CPC分类号： H01L29/1054 , H01L29/66643 , H01L29/78 , H01L29/78687
摘要： According to one embodiment of the invention, a method for integrating low Schottky barrier metal source/drain includes providing a substrate, forming an epitaxial SiGe layer outwardly from the substrate, forming an epitaxial Si layer outwardly from the SiGe layer, and forming a metal source and a metal drain.
摘要翻译：根据本发明的一个实施例，用于积分低肖特基势垒金属源极/漏极的方法包括提供衬底，从衬底向外形成外延SiGe层，从SiGe层向外形成外延Si层，以及形成金属源和金属排水管。

8. 发明授权

US07094650B2 Gate electrode for FinFET device 有权
标题翻译： FinFET器件用栅极
公开(公告)号：US07094650B2
公开(公告)日：2006-08-22
申请号：US11039173
申请日：2005-01-20
申请人： Nirmal Chaudhary , Thomas Schulz , Weize Xiong , Craig Huffman
发明人： Nirmal Chaudhary , Thomas Schulz , Weize Xiong , Craig Huffman
IPC分类号： H01L21/336
CPC分类号： H01L21/28123 , H01L29/66795 , H01L29/785
摘要： In a method of forming a semiconductor device, a self-planarizing conductive layer is formed over a substrate that includes a topography having sharp drop-offs. The self-planarizing conductive layer is characterized by a substantially flatter surface than the underlying topography. As a result of the self-planarizing layer, a masking layer having a more uniform thickness may be formed over the conductive layer. Because the masking layer has a more uniform thickness, the masking layer may easily be patterned without causing damage to the underlying materials. These techniques may be used to fabricate, among other things, a FinFET without parasitic spacers formed around the fins and the source/drain regions.
摘要翻译：在形成半导体器件的方法中，在包括具有锐利掉落的形貌的衬底上形成自平面化导电层。自平坦化导电层的特征在于比底层形貌基本上更平坦的表面。作为自平坦化层的结果，可以在导电层上形成具有更均匀厚度的掩模层。由于掩模层具有更均匀的厚度，所以掩蔽层可以容易地被图案化，而不会对下面的材料造成损害。除了别的以外，这些技术可以用于制造没有在鳍片和源极/漏极区域周围形成的寄生间隔物的FinFET。

9. 发明申请

US20120280324A1 SRAM STRUCTURE AND PROCESS WITH IMPROVED STABILITY 审中-公开
标题翻译：具有改进稳定性的SRAM结构和过程
公开(公告)号：US20120280324A1
公开(公告)日：2012-11-08
申请号：US13287737
申请日：2011-11-02
申请人： Weize Xiong , Gregory Charles Baldwin
发明人： Weize Xiong , Gregory Charles Baldwin
IPC分类号： H01L27/088 , H01L21/336
CPC分类号： H01L27/1104 , H01L21/823807 , H01L21/823814
摘要： An SRAM memory cell with reduced SiGe formation area using a gate extension (530) that extends over the STI/p-active interface (536). A process for forming an SRAM memory cell with reduced SiGe formation area. A process for forming an SRAM memory cell with improved read/write stability.
摘要翻译：使用在STI / p有源接口（536）上延伸的栅极延伸（530），SiGe形成区域减小的SRAM存储单元。用于形成具有降低的SiGe形成面积的SRAM存储单元的工艺。一种用于形成具有改善的读/写稳定性的SRAM存储单元的工艺。

10. 发明申请

US20120175710A1 INTEGRATED CIRCUITS WITH ALIGNED (100) NMOS AND (110) PMOS FINFET SIDEWALL CHANNELS 有权
标题翻译：具有对准（100）NMOS和（110）PMOS FinFET平台通道的集成电路
公开(公告)号：US20120175710A1
公开(公告)日：2012-07-12
申请号：US13425082
申请日：2012-03-20
申请人： Weize Xiong , Cloves Rinn Cleavelin , Angelo Pinto , Rick L. Wise
发明人： Weize Xiong , Cloves Rinn Cleavelin , Angelo Pinto , Rick L. Wise
IPC分类号： H01L27/092
CPC分类号： H01L27/0886 , G11C11/412 , H01L21/823807 , H01L21/823821 , H01L27/0207 , H01L27/092 , H01L27/11 , H01L27/1104 , H01L27/1116 , H01L29/045 , Y10S257/90 , Y10S438/973 , Y10S438/982
摘要： An integrated circuit device that includes a plurality of multiple gate FinFETs (MuGFETs) is disclosed. Fins of different crystal orientations for PMOS and NMOS MuGFETs are formed through amorphization and crystal regrowth on a direct silicon bonded (DSB) hybrid orientation technology (HOT) substrate. PMOS MuGFET fins are formed with channels defined by fin sidewall surfaces having (110) crystal orientations. NMOS MuGFET fins are formed with channels defined by fin sidewall surfaces having (100) crystal orientations in a Manhattan layout with the sidewall channels of the different PMOS and NMOS MuGFETs aligned at 0° or 90° rotations.
摘要翻译：公开了一种包括多个多栅极FinFET（MuGFET）的集成电路器件。通过在直接硅键合（DSB）混合取向技术（HOT）衬底上的非晶化和晶体再生长形成用于PMOS和NMOS MuGFET的不同晶体取向的晶片。 PMOS MuGFET翅片由具有（110）晶体取向的翅片侧壁表面限定的通道形成。 NMOS MuGFET翅片由曼哈顿布局具有（100）晶体取向的翅片侧壁表面限定的通道形成，其中不同PMOS和NMOS MuGFET的侧壁通道以0°或90°旋转对准。

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