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1. 发明授权

US07808301B2 Multiple-stage charge pump circuit with charge recycle circuit 有权
标题翻译：具有充电回收电路的多级电荷泵电路
公开(公告)号：US07808301B2
公开(公告)日：2010-10-05
申请号：US11878653
申请日：2007-07-26
申请人： Chung-Kuang Chen , Chun-Hsiung Hung , Yi-Te Shih
发明人： Chung-Kuang Chen , Chun-Hsiung Hung , Yi-Te Shih
IPC分类号： G05F1/10
CPC分类号： H02M3/073
摘要： A multiple-stage charge pump circuit includes first and second pump capacitors, a charge recycle circuit, and first and second transfer circuits. The charge recycle circuit includes first and second driving circuits and a switch circuit turning off to make a node floating and to couple first terminals of the first and second pump capacitors to the node in a first time period. The switch circuit and first and second driving circuits provide a specific voltage to the node and control voltages at the first terminals of the first and second pump capacitors in second and third time periods, respectively. The first and second transfer circuits provide a high voltage to a second terminal of the first pump capacitor in the second time period, and provide the voltage of the second terminal of the first pump capacitor to a second terminal of the second pump capacitor in the third time period.
摘要翻译：多级电荷泵电路包括第一和第二泵电容器，充电循环电路以及第一和第二传输电路。充电再循环电路包括第一和第二驱动电路，并且开关电路关闭以使节点浮动，并且在第一时间段内将第一和第二泵电容器的第一端子耦合到节点。开关电路和第一和第二驱动电路分别在第二和第三时间段中向节点提供特定电压并且在第一和第二泵电容器的第一端子处分别控制电压。第一和第二传送电路在第二时间段内向第一泵电容器的第二端提供高电压，并且将第一泵电容器的第二端的电压提供给第三泵电容器的第三端的第三端时间段。

2. 发明申请

US20090268543A1 MEMORY CONTROL CIRCUIT AND MEMORY ACCESSING METHOD 有权
标题翻译：存储器控制电路和存储器访问方法
公开(公告)号：US20090268543A1
公开(公告)日：2009-10-29
申请号：US12391351
申请日：2009-02-24
申请人： Chung-Kuang Chen , Yi-Te Shih , Chun-Hsiung Hung
发明人： Chung-Kuang Chen , Yi-Te Shih , Chun-Hsiung Hung
IPC分类号： G11C8/00
CPC分类号： G11C8/12 , G11C7/1006 , G11C7/1012 , G11C2207/002 , G11C2207/005
摘要： A control circuit applied in a memory that comprises a first memory block and a second memory block, and each of the first and the second memory blocks includes a boundary cell. The control circuit comprises an address decoder, a first Y-multiplexer, and a second Y-multiplexer. The address decoder provides a plurality of column selection signals capable of being a boundary value. The first Y-multiplexer corresponds to the first memory block and provides a first boundary data channel for a boundary cell of the first memory block. The second Y-multiplexer corresponds to the second memory block and provides a second boundary data channel for a boundary cell of the second memory block. The first and the second boundary data channels are enabled simultaneously in response to the boundary value for outputting boundary data stored in the boundary cell of the first memory block and that of the second memory block.
摘要翻译：一种应用于包括第一存储器块和第二存储器块的存储器中的控制电路，并且所述第一和第二存储器块中的每一个包括边界单元。控制电路包括地址解码器，第一Y多路复用器和第二Y复用器。地址解码器提供能够成为边界值的多个列选择信号。第一Y复用器对应于第一存储器块，并为第一存储器块的边界单元提供第一边界数据通道。第二Y多路复用器对应于第二存储器块，并为第二存储器块的边界单元提供第二边界数据通道。响应于用于输出存储在第一存储器块的边界单元中的边界数据的边界值和第二存储器块的边界单元，第一和第二边界数据通道同时被使能。

3. 发明授权

US08174898B2 Sense amplifier and data sensing method thereof 有权
标题翻译：感应放大器及其数据传感方法
公开(公告)号：US08174898B2
公开(公告)日：2012-05-08
申请号：US12726542
申请日：2010-03-18
申请人： Chung-Kuang Chen , Yi-Te Shih , Chun-Hsiung Hung
发明人： Chung-Kuang Chen , Yi-Te Shih , Chun-Hsiung Hung
IPC分类号： G11C11/34 , G11C7/02
CPC分类号： G11C7/14 , G11C7/062 , G11C7/1072
摘要： A data sensing method for sensing data stored in first and second memory cells includes the steps of: setting a first voltage according to a bit-line voltage corresponding to the first memory cell in response to an enabled level of a first clock signal; providing the first voltage as a sensing voltage in response to a disabled level of the first clock signal; comparing the sensing voltage with a reference voltage to generate a first output voltage; setting a second voltage according to a bit-line voltage corresponding to the second memory cell in response to an enabled level of a second clock signal, a phase difference between the first and second clock signals being 180 degrees; providing the second voltage as the sensing voltage in response to a disabled level of the second clock signal; and comparing the sensing voltage with the reference voltage to generate a second output voltage.
摘要翻译：用于感测存储在第一和第二存储单元中的数据的数据感测方法包括以下步骤：响应于第一时钟信号的使能电平，根据与第一存储器单元相对应的位线电压来设置第一电压; 响应于所述第一时钟信号的禁止电平，提供所述第一电压作为感测电压; 将感测电压与参考电压进行比较以产生第一输出电压; 响应于第二时钟信号的使能电平，根据与第二存储器单元相对应的位线电压设置第二电压，第一和第二时钟信号之间的相位差为180度; 响应于第二时钟信号的禁止电平，提供第二电压作为感测电压; 以及将感测电压与参考电压进行比较以产生第二输出电压。

4. 发明申请

US20100219881A1 Multiple-Stage Charge Pump with Charge Recycle Circuit 有权
标题翻译：具有充电回收电路的多级电荷泵
公开(公告)号：US20100219881A1
公开(公告)日：2010-09-02
申请号：US12770989
申请日：2010-04-30
申请人： Chung-Kuang Chen , Chun-Hsiung Hung , Yi-Te Shih
发明人： Chung-Kuang Chen , Chun-Hsiung Hung , Yi-Te Shih
IPC分类号： G05F3/02
CPC分类号： H02M3/073
摘要： A multiple-stage charge pump circuit comprises first and second pump capacitors, first and second transfer circuits, first and second driving circuits, and a charge recycle circuit. The first pump capacitor, the first transfer circuit, and the first driving circuit form a first stage circuit, and the second pump capacitor, the second transfer circuit and the second driving circuit form a second stage circuit. The first and the second stage circuits operate 180 degree out of phase with each other. The charge recycle circuit transfers the charge at the second end of the first pump capacitor to the second end of the second pump capacitor in a first time interval, and transferring the charge at the second end of the second pump capacitor to the second end of the first pump capacitor in a second time interval.
摘要翻译：多级电荷泵电路包括第一和第二泵电容器，第一和第二传输电路，第一和第二驱动电路以及电荷再循环电路。第一泵电容器，第一传输电路和第一驱动电路形成第一级电路，第二泵电容器，第二传输电路和第二驱动电路形成第二级电路。第一级和第二级电路彼此相位180度异相。充电再循环电路在第一时间间隔内将第一泵电容器的第二端处的电荷转移到第二泵电容器的第二端，并将第二泵电容器的第二端处的电荷转移到第二泵电容器的第二端第一个泵电容器在第二时间间隔。

5. 发明授权

US07777465B2 Output transient responsive voltage regulator controlling apparatus and method 有权
标题翻译：输出瞬态响应电压调节器控制装置及方法
公开(公告)号：US07777465B2
公开(公告)日：2010-08-17
申请号：US11940368
申请日：2007-11-15
申请人： Chung-Kuang Chen , Chun-Shiung Hung , Yi-Te Shih
发明人： Chung-Kuang Chen , Chun-Shiung Hung , Yi-Te Shih
IPC分类号： G05F1/575
CPC分类号： G05F1/56
摘要： A controlling method of a voltage regulator is provided. The voltage regulator at least includes a differential circuit and a pump high-voltage circuit which has a bias path, an output transistor and an output terminal. The controlling method includes steps of: providing at least a pre-charge path to the pump high-voltage circuit, closing the bias path and charging the output terminal with the pre-charge path when the output terminal is transient, detecting an output level of the output terminal, and closing the pre-charge path and open the bias path to bias the output transistor when the output level reaches a predetermined value.
摘要翻译：提供了一种电压调节器的控制方法。电压调节器至少包括差分电路和具有偏置路径的输出晶体管和输出端子的泵高压电路。所述控制方法包括以下步骤：在所述泵高压电路至少提供预充电路径时，当所述输出端子为瞬态时，关闭所述偏置通路并对所述输出端子充电所述预充电路径，检测所述预充电路径的输出电平输出端子，并且当输出电平达到预定值时，闭合预充电路径并打开偏置通路以偏置输出晶体管。

6. 发明申请

US20090273999A1 SENSE AMPLIFIER AND DATA SENSING METHOD THEREOF 有权
标题翻译：感应放大器及其数据传感方法
公开(公告)号：US20090273999A1
公开(公告)日：2009-11-05
申请号：US12114855
申请日：2008-05-05
申请人： Chung-Kuang Chen , Yi-Te Shih , Chun-Hsiung Hung
发明人： Chung-Kuang Chen , Yi-Te Shih , Chun-Hsiung Hung
IPC分类号： G11C7/02
CPC分类号： G11C7/14 , G11C7/062 , G11C7/1072
摘要： A data sensing method for sensing data stored in first and second memory cells includes the steps of: setting a first voltage according to a bit-line voltage corresponding to the first memory cell in response to an enabled level of a first clock signal; providing the first voltage as a sensing voltage in response to a disabled level of the first clock signal; comparing the sensing voltage with a reference voltage to generate a first output voltage; setting a second voltage according to a bit-line voltage corresponding to the second memory cell in response to an enabled level of a second clock signal, a phase difference between the first and second clock signals being 180 degrees; providing the second voltage as the sensing voltage in response to a disabled level of the second clock signal; and comparing the sensing voltage with the reference voltage to generate a second output voltage.
摘要翻译：用于感测存储在第一和第二存储单元中的数据的数据感测方法包括以下步骤：响应于第一时钟信号的使能电平，根据与第一存储器单元相对应的位线电压设置第一电压; 响应于所述第一时钟信号的禁止电平，提供所述第一电压作为感测电压; 将感测电压与参考电压进行比较以产生第一输出电压; 响应于第二时钟信号的使能电平，根据与第二存储器单元相对应的位线电压设置第二电压，第一和第二时钟信号之间的相位差为180度; 响应于第二时钟信号的禁止电平，提供第二电压作为感测电压; 以及将感测电压与参考电压进行比较以产生第二输出电压。

7. 发明授权

US07558149B2 Method and apparatus to control sensing time for nonvolatile memory 有权
标题翻译：控制非易失性存储器的检测时间的方法和装置
公开(公告)号：US07558149B2
公开(公告)日：2009-07-07
申请号：US11614791
申请日：2006-12-21
申请人： Chung Kuang Chen , Ful-Long Ni , Yi-Te Shih
发明人： Chung Kuang Chen , Ful-Long Ni , Yi-Te Shih
IPC分类号： G11C8/00
CPC分类号： G11C29/02 , B82Y10/00 , G11C7/08 , G11C7/1006 , G11C7/1051 , G11C7/106 , G11C7/20 , G11C11/406 , G11C11/4091 , G11C11/56 , G11C16/3418 , G11C16/3431 , G11C16/3436 , G11C16/3445 , G11C16/3459 , G11C29/026 , G11C29/028 , G11C2029/0407 , G11C2207/2254 , G11C2211/5621 , G11C2211/5634 , G11C2216/06
摘要： One or more clock signals are used to control sense amplifier measurements. For example, multiple threshold voltage measurement types characterize the multiple clock signals, and selecting the appropriate clock signal selects the appropriate measurement type. In another example, multiple clock signals control multiple measurements of a particular location of nonvolatile memory, so that one of multiple clock signals is selected or the appropriate clock signal is generated to apply an appropriate threshold voltage window sensitivity.
摘要翻译：一个或多个时钟信号用于控制读出放大器的测量。例如，多个阈值电压测量类型表征多个时钟信号，并选择适当的时钟信号选择适当的测量类型。在另一示例中，多个时钟信号控制非易失性存储器的特定位置的多个测量，使得选择多个时钟信号中的一个或产生适当的时钟信号以施加适当的阈值电压窗口灵敏度。

8. 发明申请

US20090121780A1 MULTIPLE-STAGE CHARGE PUMP WITH CHARGE RECYCLE CIRCUIT 审中-公开
标题翻译：带充电回路电路的多级充电泵
公开(公告)号：US20090121780A1
公开(公告)日：2009-05-14
申请号：US11938314
申请日：2007-11-12
申请人： Chung-Kuang Chen , Chun-Hsiung Hung , Yi-Te Shih
发明人： Chung-Kuang Chen , Chun-Hsiung Hung , Yi-Te Shih
IPC分类号： G05F1/10
CPC分类号： H02M3/073
摘要： A multiple-stage charge pump circuit comprises first and second pump capacitors, first and second transfer circuits, first and second driving circuits, and a charge recycle circuit. The first pump capacitor, the first transfer circuit, and the first driving circuit form a first stage circuit and the second pump capacitor, the second transfer circuit, and the second driving circuit form a second stage circuit. The first and the second stage circuits operate 180 degree out of phase with each other. The charge recycle circuit transfers the charge at the second end of the first pump capacitor to the second end of the second pump capacitor in a first time interval, and transferring the charge at the second end of the second pump capacitor to the second end of the first pump capacitor in a second time interval.
摘要翻译：多级电荷泵电路包括第一和第二泵电容器，第一和第二传输电路，第一和第二驱动电路以及电荷再循环电路。第一泵电容器，第一传输电路和第一驱动电路形成第一级电路，第二泵电容器，第二传输电路和第二驱动电路形成第二级电路。第一级和第二级电路彼此相位180度异相。充电再循环电路在第一时间间隔内将第一泵电容器的第二端处的电荷转移到第二泵电容器的第二端，并将第二泵电容器的第二端处的电荷转移到第二泵电容器的第二端第一个泵电容器在第二时间间隔。

9. 发明申请

US20090027108A1 Multiple-stage charge pump circuit with charge recycle circuit 有权
标题翻译：具有充电回收电路的多级电荷泵电路
公开(公告)号：US20090027108A1
公开(公告)日：2009-01-29
申请号：US11878653
申请日：2007-07-26
申请人： Chung-Kuang Chen , Chun-Hsiung Hung , Yi-Te Shih
发明人： Chung-Kuang Chen , Chun-Hsiung Hung , Yi-Te Shih
IPC分类号： G05F3/02
CPC分类号： H02M3/073
摘要： A multiple-stage charge pump circuit includes first and second pump capacitors, a charge recycle circuit, and first and second transfer circuits. The charge recycle circuit includes first and second driving circuits and a switch circuit turning off to make a node floating and to couple first terminals of the first and second pump capacitors to the node in a first time period. The switch circuit and first and second driving circuits provide a specific voltage to the node and control voltages at the first terminals of the first and second pump capacitors in second and third time periods, respectively. The first and second transfer circuits provide a high voltage to a second terminal of the first pump capacitor in the second time period, and provide the voltage of the second terminal of the first pump capacitor to a second terminal of the second pump capacitor in the third time period.
摘要翻译：多级电荷泵电路包括第一和第二泵电容器，充电循环电路以及第一和第二传输电路。充电再循环电路包括第一和第二驱动电路，并且开关电路关闭以使节点浮动，并且在第一时间段内将第一和第二泵电容器的第一端子耦合到节点。开关电路和第一和第二驱动电路分别在第二和第三时间段中向节点提供特定电压并且在第一和第二泵电容器的第一端子处分别控制电压。第一和第二传送电路在第二时间段内向第一泵电容器的第二端提供高电压，并且将第一泵电容器的第二端的电压提供给第三泵电容器的第三端的第三端时间段。

10. 发明授权

US06512697B1 Circuit and method for speed and stability enhancement for a sense amplifier 有权
标题翻译：用于读出放大器的速度和稳定性增强的电路和方法
公开(公告)号：US06512697B1
公开(公告)日：2003-01-28
申请号：US10023714
申请日：2001-12-21
申请人： Hsiang-Pang Li , Yi-Te Shih
发明人： Hsiang-Pang Li , Yi-Te Shih
IPC分类号： G11C1606
CPC分类号： G11C7/067 , G11C7/062 , G11C2207/063
摘要： A circuit and method for speed and stability enhancement for a sense amplifier comprises an offset current apparatus and a discharge current apparatus connected to a data node on one side of a transmission transistor that has another side with a sense node connected to a charge current apparatus and a leakage current apparatus with the leakage current mirrored from the offset current. The offset current ensures the transmission transistor not shut down and the voltage on the data node below a specific level, thereby enhancing the speed of the sense amplifier. The leakage current enhances the stability of the sense amplifier. Mirroring the leakage current from the offset current results good control of the operation and performance of the sense amplifier.
摘要翻译：用于感测放大器的速度和稳定性增强的电路和方法包括偏移电流装置和连接到传输晶体管一侧上的数据节点的放电电流装置，该传输晶体管具有另一侧，感测节点连接到充电电流装置，具有从偏移电流镜像的泄漏电流的泄漏电流装置。偏移电流确保传输晶体管不关闭，数据节点上的电压低于特定电平，从而提高读出放大器的速度。漏电流增强了读出放大器的稳定性。从偏移电流镜像漏电流可以很好地控制读出放大器的工作和性能。

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