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1. 发明公开

KR20200136489A 오프셋 3D 구조를 갖는 멀티-칩 패키지 审中-公开
公开(公告)号：KR20200136489A
公开(公告)日：2020-12-07
申请号：KR20207033690
申请日：2019-03-29
申请人： ADVANCED MICRO DEVICES INC
发明人： BHAGAVAT MILIND S , AGARWAL RAHUL , LOH GABRIEL H
IPC分类号： H01L25/065 , H01L23/00 , H01L23/498 , H01L25/07
摘要： 다양한반도체칩 디바이스및 이를제조하는방법이개시된다. 하나의양태에서, 제1 측부및 대향하는제2 측부및 상기제1 측부상의금속배선스택(145)을갖는인터포저(125), 상기금속배선스택상에있고상기금속배선스택상의유전체층(165)에의해적어도부분적으로감싸이는제1 반도체칩(25), 및상기제1 반도체칩 위에위치하고이와적어도부분적으로측방으로겹쳐지는복수의반도체칩(40, 45)을포함하는재구성반도체칩 패키지(115)를갖는반도체칩 디바이스가제공된다.

2. 发明公开

KR20180052753A 레일 프레임을 구비한 회로 기판 소켓 审中-公开
公开(公告)号：KR20180052753A
公开(公告)日：2018-05-18
申请号：KR20187010858
申请日：2016-09-15
申请人： ADVANCED MICRO DEVICES INC
发明人： HENG STEPHEN F , HARDIKAR MAHESH S , DANDIA SANJAY
IPC分类号： H01R12/51 , H01R4/64 , H01R12/00 , H01R13/518
CPC分类号： H05K3/32 , H01R12/7076 , H01R12/88 , H01R43/205 , H05K7/1007
摘要： 패키징된집적회로(30)를회로기판(20)에전기적으로연결하는다양한장치및 방법이개시된다. 일양태에서, 장치(10)는회로기판(20) 상에장착되고제1 단부를갖는제1 프레임(40)을포함한다. 절연하우징(60)은회로기판상에장착되고제1 프레임내에위치되도록구성된다. 제2 프레임(80)은제1 프레임에피벗식으로결합된다. 제2 프레임은 2개의이격된레일부재(760, 770), 및제2 프레임의제1 단부에대향하여레일부재들사이에서레일부재들에결합된크로스부재(810)를포함한다. 레일부재는패키징된집적회로(30)를수용하도록동작할수 있다. 제2 프레임은, 이제2 프레임이절연하우징을향하여피벗팅될때에절연하우징의제1 부분과맞물리게하기위한적어도하나의맞물림부재(862)를갖는다. 제3 프레임(90)은패키징된집적회로에힘을인가하기위해제1 프레임에피벗식으로결합된다.

3. 发明公开

KR20200139812A 네트워크 스위치에서의 큐 审中-公开
公开(公告)号：KR20200139812A
公开(公告)日：2020-12-14
申请号：KR20207032316
申请日：2019-04-09
申请人： ADVANCED MICRO DEVICES INC
发明人： SMITH ALAN DODSON , KALYANASUNDHARAM VYDHYANATHAN , BROUSSARD BRYAN P , DONLEY GREGGORY D , PATEL CHINTAN S
IPC分类号： H04L12/877 , H04L12/841 , H04L12/861 , H04L12/863 , H04L12/873 , H04L12/875 , H04L12/879
摘要： 컴퓨팅시스템은데이터를저장하기위한메모리, 네트워크트래픽을생성하기위한하나이상의클라이언트들및 네트워크스위치들과의통신패브릭을사용한다. 네트워크스위치들은별개의입력및 출력저장구조들보다는, 집중화된저장구조들을포함한다. 네트워크스위치들은패킷들의에이지가큐 엔트리위치에대응하는단일의, 집중화된접이형큐에수신된패킷들에대응하는특정한메타데이터를저장한다. 패킷들의페이로드데이터는별개의메모리에저장되며, 따라서비교적많은양의데이터가네트워크스위치에서패킷의수명동안시프트되지않는다. 네트워크스위치들은접이식큐에서희소큐 엔트리들을선택하고, 선택된큐 엔트리들을할당해제하며, 네트워크스위치들의기수에비례하는지연을갖고큐의제 1 단부를향해남아있는할당된큐 엔트리들을시프트시킨다.

4. 发明公开

KR20200134281A 추계학적 반올림 로직 审中-公开
公开(公告)号：KR20200134281A
公开(公告)日：2020-12-01
申请号：KR20207030287
申请日：2019-03-18
申请人： ADVANCED MICRO DEVICES INC
发明人： LOH GABRIEL H
IPC分类号： G06F7/499 , G06F7/58 , G06N20/00
摘要： 추계학적반올림을위한기술들및 회로들이제공된다. 일실시예에서, 회로는세 개이상의 CSA 입력, CSA 합출력및 CSA 자리올림출력을갖는자리올림보존가산기(CSA) 로직을포함한다. 세개 이상의 CSA 입력중 하나는난수값으로제시되는한편, 다른 CSA 입력들은합산될입력값들로제시된다. 상기회로는가산기입력들및 합출력을갖는가산기로직을더 포함한다. 상기 CSA 로직의상기 CSA 자리올림출력은상기가산기로직의상기가산기입력들중 하나와연결되고, 상기 CSA 로직의상기 CSA 합출력은상기가산기로직의상기가산기입력들의다른입력과연결된다. 상기가산기로직의상기합 출력의최상위비트들의특정수는상기입력값들의추계학적으로반올림된합을나타낸다.

5. 发明专利

JP2015092756A 多重キャリア変調受信機におけるチャネル推定及びピーク対平均電力比低減有权
公开(公告)号：JP2015092756A
公开(公告)日：2015-05-14
申请号：JP2015006231
申请日：2015-01-15
申请人： ADVANCED MICRO DEVICES INC
发明人： RAVIKIRAN RAJAGOPA
IPC分类号： H04J11/00
摘要：【課題】直交周波数分割多重化(OFDM)信号においてチャネル推定を実行するための方法を提供する。【解決手段】受信したトーンチャネルキャリアの使用に基いてチャネル推定を実行する。先ず第2のグループ内のキャリア種類に対して任意の非ゼロ値を選択し、次いで予め定められたPAPRスレッショルドに基いて第2のグループ内のキャリア種類に対して非ゼロ値を最適に決定することによって、キャリアの2つ以上のグループを含む多重キャリア変調信号のためのピーク対平均電力比(PAPR)を低減する。第1のグループ内のキャリア種類は、データキャリア、連続的なパイロット、及び分散パイロットの少なくとも1つを含み、第2のグループ内のキャリア種類は、リザーブされたトーンを含む。【選択図】図3

6. 发明专利

JP2010213331A Method and apparatus for buffering data samples in software based adsl modem 有权
标题翻译：用于在基于软件的ADSL调制解调器中缓冲数据样本的方法和装置
公开(公告)号：JP2010213331A
公开(公告)日：2010-09-24
申请号：JP2010103622
申请日：2010-04-28
申请人： Advanced Micro Devices Inc , アドバンスト・マイクロ・ディバイシズ・インコーポレイテッドAdvanced Micro Devices Incorporated
发明人： COLE TERRY LYNN , BOSWELL CHARLES RAY JR
IPC分类号： H04L13/08 , H04L27/26 , H04M11/00
CPC分类号： H04L27/2647 , H04L27/261
摘要： PROBLEM TO BE SOLVED: To provide an apparatus and a method for stably transferring data when processing of a host computer executing a software routine of an ADSL modem is delayed in modem communication using the ADSL modem.
SOLUTION: The invention relates to a method and an apparatus for buffering data samples in a software-based ADSL modem. The method includes the steps of receiving samples of a buffer and determining if the received samples of data will exceed the storage capacity of the buffer. Selected samples of data from the buffer are deleted or compressed in response to the storage capacity being exceeded. The selected samples of data that were deleted are then reconstituted or decompressed.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于在使用ADSL调制解调器的调制解调器通信中延迟执行ADSL调制解调器的软件程序的主机的处理时稳定地传送数据的装置和方法。解决方案：本发明涉及用于在基于软件的ADSL调制解调器中缓冲数据样本的方法和装置。该方法包括以下步骤：接收缓冲器的样本并确定所接收的数据样本是否将超过缓冲器的存储容量。响应于超过的存储容量，删除或压缩来自缓冲器的所选数据样本。然后将所选删除的数据样本重组或解压缩。版权所有（C）2010，JPO＆INPIT

7. 发明专利

JP2006049926A 3-d nonvolatile memory 有权
标题翻译： 3-D非易失性存储器
公开(公告)号：JP2006049926A
公开(公告)日：2006-02-16
申请号：JP2005273676
申请日：2005-09-21
申请人： Advanced Micro Devices Inc , アドバンスト・マイクロ・ディバイシズ・インコーポレイテッドAdvanced Micro Devices Incorporated
发明人： LIU YOWJUANG W , HADDAD SAMEER S
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/115 , H01L29/7885
摘要： PROBLEM TO BE SOLVED: To make it possible to manufacture a bit transistor of a smaller geometric shape without using an advanced costly lithographic tool.
SOLUTION: The strip of a semiconductor material (e.g. P-type silicon) is oxidized, and the strip of oxide obtained as a result is removed. Then, depressions are left on the upper frontal surface of the semiconductor material having a sidewall of steep slope. There is no significant damage by ion bombardment on the sidewall of steep slope. It is because these are formed by oxidation and not by performing reactive ion etching on the semiconductor material. Therefore, a high-quality tunnel oxide can be formed on the sidewall of steep slope. Next, a floating gate 124 is formed on the tunnel oxide, and the corresponding word line is formed on the floating gate. After that, a conductive region (e.g. N-type silicon) is formed inside the bottom of the depressions. Finally, several conductive regions 150 (e.g. N-type silicon) corresponding to the floating gate are formed at the upper part of the edge of the depressions.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了使得可以制造更小几何形状的位晶体管而不使用先进的昂贵的光刻工具。解决方案：半导体材料（例如P型硅）的条被氧化，并且结果获得的氧化物条被去除。然后，在具有斜坡侧壁的半导体材料的上表面上留下凹陷。陡坡边缘离子轰击没有明显的破坏。这是因为这些是通过氧化形成的，而不是通过在半导体材料上进行反应离子蚀刻。因此，可以在陡坡的侧壁上形成高质量的隧道氧化物。接下来，在隧道氧化物上形成浮栅124，并且在浮栅上形成对应的字线。之后，在凹部的底部形成有导电区域（例如N型硅）。最后，在凹陷的边缘的上部形成对应于浮动栅极的几个导电区域150（例如N型硅）。版权所有（C）2006，JPO＆NCIPI

8. 发明专利

JP2004095910A Semiconductor memory device and its manufacturing method 有权
公开(公告)号：JP2004095910A
公开(公告)日：2004-03-25
申请号：JP2002256120
申请日：2002-08-30
申请人： Advanced Micro Devices Inc , Fasl Japan Ltd , Fasl Japan 株式会社 , Fujitsu Ltd , アドバンスト・マイクロ・ディバイシズ・インコーポレイテッドAdvanced Micro Devices Incorporated , 富士通株式会社
发明人： KOMORI HIDEKI , SHIMADA HISAYUKI , SUN YU , KINOSHITA HIROYUKI
IPC分类号： H01L21/8234 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , H01L21/823425 , H01L21/823468 , H01L27/115 , H01L27/11568 , Y10S257/90
摘要： PROBLEM TO BE SOLVED: To provide a high reliability semiconductor memory device which can increase a drain breakdown voltage, while satisfying two contradictory requirements for enhancing programming efficiency by improving a short channel effect and reduction in drain contact resistance. SOLUTION: A low-concentration shallow impurity region 7a formed so as to align with a control panel, and a high-concentration deep impurity region 7b formed so as to align with a sidewall film 8 and formed at a concentration higher than that of the low-concentration shallow impurity region 7a are formed at a drain 7. The programing efficiency is thus improved by forming the low-concentration impurity region 7a at the drain, resulting in the improvement of a short-channel effect, and the contact resistance of the drain can be reduced by forming a drain contact hole formation region 70 at the high concentration deep impurity region 7b. COPYRIGHT: (C)2004,JPO

9. 发明专利

JP2000332008A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JP2000332008A
公开(公告)日：2000-11-30
申请号：JP14034699
申请日：1999-05-20
申请人： FUJITSU LTD , ADVANCED MICRO DEVICES INC , FUJITSU AMD SEMICONDUCTOR KK
发明人： INOUE RIICHI , KINOSHITA TADASHI , MOCHIZUKI KAZUHISA , FUKUYAMA SHUNICHI , SHIOBARA MORIO
IPC分类号： H01L21/312 , H01L21/316 , H01L21/768 , H01L23/532
摘要： PROBLEM TO BE SOLVED: To easily and surely increase degree of integration of, particularly a semiconductor device by meeting both requirements of improving the reliability of fine content holes and the suppression of wiring delays. SOLUTION: A semiconductor device utilizes the fact that a threshold, at which it is considered that an abrupt change occurs in the degassing quantity from a hydrogen silses quioxane(HSQ) film 12, when the quantity of hygroscopic SiH contained in the HSQ film 12 fluctuates exists in the relation between the quantity SiH and the degassing quantity. More specifically, the linear defect which is considered to occur in an insulating film 13 formed on the HSQ film 12 due to the desorption of a hygroscopic component is suppressed by reducing the hygroscopic property of the HSQ film 12, by using the HSQ film 12 containing a relative quantity of SiH or an absolute quantity of H as one insulating layer of an interlayer insulating film.

10. 发明专利

JP2000066749A REFERENCE VOLTAGE GENERATION CIRCUIT 失效
公开(公告)号：JP2000066749A
公开(公告)日：2000-03-03
申请号：JP19981399
申请日：1999-07-14
申请人： ADVANCED MICRO DEVICES INC , FUJITSU LTD
发明人： YON K KIM , RYU SEI
IPC分类号： H01L27/04 , G05F3/16 , G05F3/24 , G05F3/26 , H01L21/822
摘要： PROBLEM TO BE SOLVED: To provide an improved reference voltage generation circuit for generating the output reference voltage of about 700 mV compensated for the fluctuation of a temperature and a power supply voltage by using the extremely low power supply voltage of about 1 V. SOLUTION: The extremely low power supply voltage VCC is used, first and second gate bias voltages are supplied to two P channel transistors P1, P2; P3, P4; P5, P6; P7 and P8 respectively provided in parallelly connected first-forth circuit branches and a current I1 flowing to the first circuit branch is kept constant when the fluctuation is generated in a power supply potential VCC. Thus, a further low reference output voltage Vref compensated for the fluctuation of the temperature and the power supply voltage is generated.

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