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1. 发明专利

DE112022000031T5 Implementierungen und Verfahren zum Verarbeiten eines neuronalen Netzes in Halbleiter-Hardware 未知
公开(公告)号：DE112022000031T5
公开(公告)日：2023-01-19
申请号：DE112022000031
申请日：2022-04-29
申请人： UNIQUIFY INC
发明人： LEE JOSHUA
IPC分类号： G06N3/063 , G06F5/08 , G11C19/00
摘要： Aspekte der vorliegenden Offenbarung umfassen Systeme, Verfahren, Computerbefehle und Verarbeitungselemente künstlicher Intelligenz (AlPEs), die eine Schieberschaltung oder eine ihr entsprechende Schaltungsanordnung/ihr entsprechende Hardware/ihr entsprechende Computerbefehle umfassen, die konfiguriert ist zum Aufnehmen einer verschiebbaren Eingabe, die aus Eingangsdaten für eine Operation eines neuronalen Netzes hergeleitet ist; Aufnehmen eines Verschiebungsbefehls, der aus einem entsprechenden logarithmisch quantisierten Parameter des neuronalen Netzes oder einem konstanten Wert hergeleitet ist; und Verschieben der verschiebbaren Eingabe in einer Linksrichtung oder einer Rechtsrichtung gemäß dem Verschiebungsbefehl, um eine verschobene Ausgabe zu bilden, die eine Multiplikation der Eingangsdaten mit dem entsprechenden logarithmisch quantisierten Parameter des neuronalen Netzes repräsentiert.

2. 发明专利

FR3122797A1 SYSTEMES ET PROCEDES IMPLIQUANT INTELLIGENCE ARTIFICIELLE ET LA TECHNOLOGIE EN NUAGE POUR SYSTEME DE SERVEUR SUR PUCE 未知
公开(公告)号：FR3122797A1
公开(公告)日：2022-11-11
申请号：FR2204216
申请日：2022-05-04
申请人： UNIQUIFY INC
发明人： LEE JOSHUA , KIM SAMJUNG
IPC分类号： H04N21/23 , G06N3/02 , G06V20/40 , H04N21/80
摘要： Des exemples d'implémentations décrits ici ont trait à des systèmes et procédés pour un dispositif concentrateur serveur qui est configuré pour exécuter des modèles d'intelligence artificielle/de réseau neuronal via traitement de données d'entrée et génération de métadonnées ou d'instructions vers des dispositifs périphériques. Dans des exemples d'implémentations, les opérations d’IA/de RN sont menées en exécutant des décalages logiques (par ex. par des circuits décaleurs) sur des paramètres quantifiés logarithmiquement correspondant à de telles opérations.

3. 发明申请

WO2014165214A2 CONTINUOUS ADAPTIVE TRAINING FOR DATA INTERFACE TIMING CALIBRATION 审中-公开
标题翻译：用于数据接口时序校准的连续自适应训练
公开(公告)号：WO2014165214A2
公开(公告)日：2014-10-09
申请号：PCT/US2014/024818
申请日：2014-03-12
申请人： UNIQUIFY, INC.
发明人： IYER, Venkat , LEE, Jung , JOSHI, Prashant
IPC分类号： H03L7/10
CPC分类号： G06F13/3625 , G06F13/1689 , G06F13/4256 , G11C8/18 , G11C29/022 , G11C29/023 , G11C29/028 , H03K5/133 , H03K5/14 , H03K2005/00019 , H03L7/08 , H03L7/0812 , H03L7/10
摘要： Circuits and methods for implementing a continuously adaptive timing calibration training function in an integrated circuit interface are disclosed. A mission data path is established where a data bit is sampled by a strobe. A similar reference data path is established for calibration purposes only. At an initialization time both paths are calibrated and a delta value between them is established. During operation of the mission path, the calibration path continuously performs calibration operations to determine if its optimal delay has changed by more than a threshold value. If so, the new delay setting for the reference path is used to change the delay setting for the mission path after adjustment by the delta value. Circuits and methods are also disclosed for performing multiple parallel calibrations for the reference path to speed up the training process.
摘要翻译：公开了用于在集成电路接口中实现连续自适应定时校准训练功能的电路和方法。建立通过闪光灯对数据位进行采样的任务数据通路。建立类似的参考数据路径用于校准目的。在初始化时间，两个路径被校准，并且它们之间的增量值被建立。在任务路径的操作期间，校准路径连续执行校准操作，以确定其最佳延迟是否已经改变超过阈值。如果是这样，则使用参考路径的新延迟设置，将调整后的任务路径的延迟设置改变为delta值。还公开了用于对参考路径执行多个并行校准以加速训练过程的电路和方法。

4. 发明申请

WO2022235550A1 SYSTEMS AND METHODS INVOLVING ARTIFICIAL INTELLIGENCE AND CLOUD TECHNOLOGY FOR SERVER SOC 审中-公开
公开(公告)号：WO2022235550A1
公开(公告)日：2022-11-10
申请号：PCT/US2022/027242
申请日：2022-05-02
申请人： UNIQUIFY, INC.
发明人： LEE, Joshua , KIM, Samjung
IPC分类号： H06N3/04 , G06N3/08 , G06Q30/02 , G06T7/00
摘要： Example implementations described herein are directed to systems and methods for a server hub device that is configured to execute artificial intelligence/neural network models through processing input data and generating metadata or instructions to edge devices. In example implementations, the AI/NN operations are conducted through executing logical shifts (e.g., by shifter circuits) on log-quantized parameters corresponding to such operations.

5. 发明申请

WO2022235517A2 IMPLEMENTATIONS AND METHODS FOR PROCESSING NEURAL NETWORK IN SEMICONDUCTOR HARDWARE 审中-公开
公开(公告)号：WO2022235517A2
公开(公告)日：2022-11-10
申请号：PCT/US2022/027035
申请日：2022-04-29
申请人： UNIQUIFY, INC.
发明人： LEE, Joshua
IPC分类号： G06N3/02 , G06F5/01 , G06F7/44 , G06N3/063
摘要： Aspects of the present disclosure involve systems, methods, computer instructions, and artificial intelligence processing elements (AIPEs) involving a shifter circuit or equivalent circuitry/hardware/computer instructions thereof configured to intake shiftable input derived from input data for a neural network operation; intake a shift instruction derived from a corresponding log quantized parameter of a neural network or a constant value; and shift the shiftable input in a left direction or a right direction according to the shift instruction to form shifted output representative of a multiplication of the input data with the corresponding log quantized parameter of the neural network.

6. 发明申请

WO2014165169A3 DYNAMICALLY ADAPTIVE BIT-LEVELING FOR DATA INTERFACES 审中-公开
公开(公告)号：WO2014165169A3
公开(公告)日：2014-10-09
申请号：PCT/US2014/024637
申请日：2014-03-12
申请人： UNIQUIFY, INC.
发明人： GOPALAN, Mahesh
IPC分类号： H04L7/00
摘要： A circuit and method for implementing a adaptive bit-leveling function in an integrated circuit interface is disclosed. During a calibration operation, a pre-loaded data bit pattern is continuously sent from a sending device and is continuously read from an external bus by a receiving device. A programmable delay line both advances and delays each individual data bit relative to a sampling point in time, and delay counts relative to a reference point in time are recorded for different sampled data bit values, enabling a delay to be determined that best samples a data bit at its midpoint. During the advancing and delaying of a data bit, jitter on the data bit signal may cause an ambiguity in the determination of the midpoint, and solutions are disclosed for detecting jitter and for resolving a midpoint for sampling a data bit even in the presence of the jitter.

7. 发明申请

WO2014165169A9 DYNAMICALLY ADAPTIVE BIT-LEVELING FOR DATA INTERFACES 审中-公开
标题翻译：用于数据接口的动态自适应位移
公开(公告)号：WO2014165169A9
公开(公告)日：2015-06-04
申请号：PCT/US2014024637
申请日：2014-03-12
申请人： UNIQUIFY INC
发明人： GOPALAN MAHESH
IPC分类号： H04L7/00
CPC分类号： H04L7/0337 , G06F1/08 , G06F11/0763 , G06F11/0793 , H03K5/00 , H03K19/01806 , H04L1/205
摘要： A circuit and method for implementing a adaptive bit-leveling function in an integrated circuit interface is disclosed. During a calibration operation, a pre-loaded data bit pattern is continuously sent from a sending device and is continuously read from an external bus by a receiving device. A programmable delay line both advances and delays each individual data bit relative to a sampling point in time, and delay counts relative to a reference point in time are recorded for different sampled data bit values, enabling a delay to be determined that best samples a data bit at its midpoint. During the advancing and delaying of a data bit, jitter on the data bit signal may cause an ambiguity in the determination of the midpoint, and solutions are disclosed for detecting jitter and for resolving a midpoint for sampling a data bit even in the presence of the jitter.
摘要翻译：公开了一种用于在集成电路接口中实现自适应位调平功能的电路和方法。在校准操作期间，从发送设备连续地发送预加载的数据位模式，并且由接收设备从外部总线连续读取。可编程延迟线都相对于采样点在时间上推进和延迟每个单独的数据位，并且针对不同的采样数据位值记录相对于参考点的延迟计数，使得能够确定最佳采样数据的延迟位在它的中点。在数据位的推进和延迟期间，数据位信号的抖动可能导致确定中点的模糊性，并且公开了用于检测抖动和解决用于采样数据位的中点的解决方案，即使存在抖动。

8. 发明申请

WO2014165214A3 CONTINUOUS ADAPTIVE TRAINING FOR DATA INTERFACE TIMING CALIBRATION 审中-公开
标题翻译：数据接口定时校准的连续适应性训练
公开(公告)号：WO2014165214A3
公开(公告)日：2014-11-27
申请号：PCT/US2014024818
申请日：2014-03-12
申请人： UNIQUIFY INC
发明人： IYER VENKAT , LEE JUNG , JOSHI PRASHANT
IPC分类号： G11C7/10
CPC分类号： G06F13/3625 , G06F13/1689 , G06F13/4256 , G11C8/18 , G11C29/022 , G11C29/023 , G11C29/028 , H03K5/133 , H03K5/14 , H03K2005/00019 , H03L7/08 , H03L7/0812 , H03L7/10
摘要： Circuits and methods for implementing a continuously adaptive timing calibration training function in an integrated circuit interface are disclosed. A mission data path is established where a data bit is sampled by a strobe. A similar reference data path is established for calibration purposes only. At an initialization time both paths are calibrated and a delta value between them is established. During operation of the mission path, the calibration path continuously performs calibration operations to determine if its optimal delay has changed by more than a threshold value. If so, the new delay setting for the reference path is used to change the delay setting for the mission path after adjustment by the delta value. Circuits and methods are also disclosed for performing multiple parallel calibrations for the reference path to speed up the training process.
摘要翻译：公开了用于在集成电路接口中实现连续自适应定时校准训练功能的电路和方法。任务数据路径建立在通过选通脉冲对数据位进行采样的地方。仅为校准目的建立类似的参考数据路径。在初始化时，两个路径都被校准并且它们之间的增量值被建立。在任务路径的操作期间，校准路径连续执行校准操作以确定其最佳延迟是否已经改变超过阈值。如果是，则参考路径的新延迟设置用于在由增量值调整之后改变任务路径的延迟设置。还公开了用于对参考路径执行多个平行校准以加速训练过程的电路和方法。

9. 发明申请

WO2022235685A1 SYSTEMS AND METHODS INVOLVING ARTIFICIAL INTELLIGENCE AND CLOUD TECHNOLOGY FOR EDGE AND SERVER SOC 审中-公开
公开(公告)号：WO2022235685A1
公开(公告)日：2022-11-10
申请号：PCT/US2022/027496
申请日：2022-05-03
申请人： UNIQUIFY, INC.
发明人： LEE, Joshua
IPC分类号： H04N21/40
摘要： Aspects of the present disclosure involve systems, methods, computer instructions, and an edge system involving a memory configured to store an object detection/classification model in a form of a trained neural network represented by one or more log quantized parameter values, the object detection/classification model configured to classify one or more objects on image data through one or more neural network operations according to the log quantized parameter values of the trained neural network; and a system on chip (SoC) or equivalent circuitry/hardware/computer instructions thereof configured to intake the image data; execute one or more trained neural network models through the one or more neural network operations in connection with the image data; add one or more overlays to the image data based on the classified one or more objects from the image data; and provide the image data with the added overlays as output.

10. 发明申请

WO2014165169A2 DYNAMICALLY ADAPTIVE BIT-LEVELING FOR DATA INTERFACES 审中-公开
标题翻译：动态自适应位平面数据接口
公开(公告)号：WO2014165169A2
公开(公告)日：2014-10-09
申请号：PCT/US2014024637
申请日：2014-03-12
申请人： UNIQUIFY INC
发明人： GOPALAN MAHESH
IPC分类号： G06F11/07
CPC分类号： H04L7/0337 , G06F1/08 , G06F11/0763 , G06F11/0793 , H03K5/00 , H03K19/01806 , H04L1/205
摘要： A circuit and method for implementing a adaptive bit-leveling function in an integrated circuit interface is disclosed. During a calibration operation, a pre-loaded data bit pattern is continuously sent from a sending device and is continuously read from an external bus by a receiving device. A programmable delay line both advances and delays each individual data bit relative to a sampling point in time, and delay counts relative to a reference point in time are recorded for different sampled data bit values, enabling a delay to be determined that best samples a data bit at its midpoint. During the advancing and delaying of a data bit, jitter on the data bit signal may cause an ambiguity in the determination of the midpoint, and solutions are disclosed for detecting jitter and for resolving a midpoint for sampling a data bit even in the presence of the jitter.
摘要翻译：公开了用于在集成电路接口中实现自适应比特均衡功能的电路和方法。在校准操作期间，预先加载的数据位模式被连续地从发送设备发送并且由接收设备连续地从外部总线读取。可编程延迟线路相对于采样时间点前进和延迟每个单独的数据比特，并且针对不同的采样数据比特值记录相对于参考时间点的延迟计数，使得能够确定最佳采样数据的延迟位于中点。在数据位的前进和延迟期间，数据位信号上的抖动可能导致确定中点时的模糊性，并且公开了用于检测抖动和解决用于采样数据位的中点的解决方案，即使存在抖动。

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