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81. 发明专利

JPS63113491A MEMORY 失效
公开(公告)号：JPS63113491A
公开(公告)日：1988-05-18
申请号：JP19590086
申请日：1986-08-21
申请人： ASCII CORP
发明人： ISHII TAKATOSHI
IPC分类号： G11C11/401 , G06F12/00 , G09G1/02 , G09G5/00 , G11C11/34

82. 发明专利

JPS6352247A MEMORY DEVICE 失效
公开(公告)号：JPS6352247A
公开(公告)日：1988-03-05
申请号：JP19590386
申请日：1986-08-21
申请人： ASCII CORP
发明人： ISHII TAKATOSHI
IPC分类号： G06F12/00 , G06F12/04 , G06F12/06 , G06T1/60 , G09G5/00 , G09G5/02
摘要： PURPOSE:To decrease the access frequency and to shorten the data transfer time by using an access data switching means which selects plural parts after changing the selecting positions. CONSTITUTION:Each of memory devices #0M-#3M of the same constitution consists of memories M0-M7, bit interfaces BTI0-BTI7, a pixel interface PXI-0, and a timing command control TCC including a timing control TC and a command control CC. The control CC receives the line selection reading commands from address buses A0-A7 by the control signals CSW, CAS and WE and outputs these signals to the control TC. The control TC actuates the access data switching means in the interfaces BTI0-BTI7 and advances successively the present data access addresses of memories M0-M7 to output successively the data on the memories M0-M7 to output buses IO0-IO7.

83. 发明专利

JPS62210796A VIDEO MEMORY SYSTEM 失效
公开(公告)号：JPS62210796A
公开(公告)日：1987-09-16
申请号：JP5259786
申请日：1986-03-12
申请人： ASCII CORP
发明人： ISHII TAKATOSHI
IPC分类号： H04N11/04 , G09G1/02 , G09G1/28 , G09G5/02 , G09G5/06 , G09G5/36
摘要： PURPOSE:To easily perform an processing by a computer, and to improve displaying picture quality, by setting one plane or one bit in a video memory as an attribute bit, and deciding whether a data stored on the memory is a composite data, or a logical color code data, corresponding to the attribute bit. CONSTITUTION:In the output time of the composite data by a video RAM10, the most significant bit (attribute) of a display data register 20 goes to '0'. And the composite data is converted to an analog signal at a D/A conversion circuit 50, and through a selector 70, it is composite-outputted, and the waveform of composite is accumulated at the RAM10, thereby a beautiful natural picture can be displayed. Also, when a logical color code is used, the most significant bit (attribute) of the display data register 20 goes to '1'. The logical color code outputted from the display data register 20 is converted to the analog signal by a D/A conversion circuit 51, and is RGB-outputted through a selector 71, then being RGB-displayed.

84. 发明专利

JPS62175855A INPUT/OUTPUT INTERFACE 失效
公开(公告)号：JPS62175855A
公开(公告)日：1987-08-01
申请号：JP1739286
申请日：1986-01-29
申请人： ASCII CORP
发明人： ISHII TAKATOSHI
IPC分类号： G06F13/42
摘要： PURPOSE:To maintain the interchangeability between an I/O interface and a conventional printer interface and also to attain the transfer of data on a scanner, by using an instructing means for transfer direction of data to instruct the direction of data transferred between a center and an I/O device. CONSTITUTION:A center 10 sets the direction signal DIR at 1 when it transfers data to an I/O peripheral device 20. Then the center 10 gives the trailing to the strobing signal after confirming that no busy signal is delivered. The device 20 outputs the busy signal by the trailing of the strobing signal and receives data while this strobing signal is delivered. While the center 10 sets the signal DIR at 0 and outputs the strobing signal for reception request. Thus the device 20 outputs temporarily the busy signal in response to said reception request and sends the first data to the center 10. As a result, a data bus is enabled to output the data.

85. 发明专利

JPS62135887A DISPLAY CONTROLLER 失效
公开(公告)号：JPS62135887A
公开(公告)日：1987-06-18
申请号：JP27736785
申请日：1985-12-10
申请人： ASCII CORP
发明人： ISHII TAKATOSHI
IPC分类号： G09G5/06 , G09G1/28

86. 发明专利

JPS6291053A TELEPHONE EXCHANGE SYSTEM 失效
公开(公告)号：JPS6291053A
公开(公告)日：1987-04-25
申请号：JP23040785
申请日：1985-10-16
申请人： ASCII CORP
发明人： FUJIWARA HIROSHI , NISHI KAZUHIKO , TAKAHASHI KENICHI
IPC分类号： H04M3/42
摘要： PURPOSE:To dial automatically a telephone set at a moved location by referring to a telephone number corresponding to the user number from a corresponding table storage means when a user number is dialed and sending a signal by the telephone number. CONSTITUTION:Readers R1-Rn provided in correspondence to telephone sets D1-Dn respectively read a user number from a prescribed card. A management equipment 4 has a corresponding table storage means and a corresponding table updating means, and the corresponding table is a table where each telephone number of the plural telephone sets D1-Dn and the corresponding table storage means stores the corresponding table. Further, the corresponding table updating means revises the user number read by the readers R1-Rn corresponding to the telephone number of the telephone set corresponding to the read reader. Thus, even when a user to which a telephone call is given moves to other location than a normal place, the telephone system offers the telephone call to a telephone set at the moved location.

87. 发明专利

JPS6249458A MEMORY DEVICE 失效
公开(公告)号：JPS6249458A
公开(公告)日：1987-03-04
申请号：JP18742185
申请日：1985-08-28
申请人： ASCII CORP
发明人： ISHII TAKATOSHI
IPC分类号： G11C7/00 , G06F12/00
摘要： PURPOSE:To obtain a memory device that can make an image memory and a program memory coexist by adding chip selecting function. CONSTITUTION:In a memory array 50, word is constituted by lateral combination of memories M and 1 pick cell is constituted by longitudinal combination of memories M. A chip select mask register 67 holding information that selects chip of the memory array 50 is provided in a word controlling circuit 60W. A read plane mask register 63, a read control selector 63s and a read pane gate 64 are provided as a read inhibition mask device for word direction that inhibits and masks reading of a specified memory M that exists in word direction in the memory array 50. Further, a write plane mask register 65, a write control selector 65s and a write plane gate 66 are provided as a write inhibition mask device for word direction.

88. 发明专利

JPS6249457A STORAGE UNIT 失效
公开(公告)号：JPS6249457A
公开(公告)日：1987-03-04
申请号：JP18742085
申请日：1985-08-28
申请人： ASCII CORP
发明人： ISHII TAKATOSHI
IPC分类号： G11C7/00 , G06F12/00 , G11C11/401
摘要： PURPOSE:To obtain a multifunction storage unit by giving command function to a storage unit and realizing various modes, constitution and operation basing on the command. CONSTITUTION:The unit consists of a memory array 50, a word control circuit 60W, a bit control circuit 60B and a timing control circuit 70 that controls timing of each circuit. The word control circuit 60W is a circuit that controls a control line of word direction or face direction of the memory array 50, and the circuit exists corresponding to bit number (i) that constitutes the word. The bit control circuit 60B is a circuit that controls a control line of bit direction or pixel direction of the memory array 50, and the circuit exists corresponding to bit number (j) that constitutes the pixel A data bus and a data line are made in common by one of data bus and the address line is supplied to whole of the memory array 50.

89. 发明专利

JPS61296386A MEMORY INTERFACE 失效
公开(公告)号：JPS61296386A
公开(公告)日：1986-12-27
申请号：JP13830585
申请日：1985-06-25
申请人： ASCII CORP
发明人： ISHII TAKATOSHI
IPC分类号： G09G5/36 , G06F12/00 , G06F12/06 , G06T1/60 , G09G1/02 , G09G5/39 , G11C7/00

90. 发明专利

JPS61287328A AD CONVERTING CIRCUIT 失效
公开(公告)号：JPS61287328A
公开(公告)日：1986-12-17
申请号：JP12805785
申请日：1985-06-14
申请人： ASCII CORP
发明人： ISHII TAKATOSHI
IPC分类号： H03M1/12
摘要： PURPOSE:To obtain an inexpensive AD conversion circuit by fluctuating periodicall the entire reference voltage, allowing an output buffer to hold a preceding output signal of a signal conversion circuit and adding an output signal of the signal conversion circuit and the preceding output signal by an adder circuit. CONSTITUTION:The AD conversion circuit 100 has the signal conversion circuit 20, a reference voltage fluctuation circuit 30, a buffer 40 and the adder circuit 50. The signal conversion circuit 20 converts an analog input signal into a digital signal of the number prescribed bits based on the reference voltage. The refrence voltage fluctuation circuit 30 fulctuates the entire reference voltage of the signal conversion circuit 20 at each sampling. The buffer 40 fetches the preceding output signal in the signal conversion circuit 20. The adder circuit 50 adds the output signal of the signal conversion circuit 20 and the output signal of the buffer 40 and outputs a signal having bits more than the number of output bits of the signal conversion circuit 20 by one bit.

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