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1. 发明公开

US20240282726A1 SEMICONDUCTOR DEVICE WITH PAD CONTACT FEATURE AND METHOD THEREFOR 审中-公开
公开(公告)号：US20240282726A1
公开(公告)日：2024-08-22
申请号：US18170581
申请日：2023-02-17
申请人： NXP USA, INC.
发明人： Trent Uehling
IPC分类号： H01L23/00
CPC分类号： H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/0345 , H01L2224/03464 , H01L2224/03912 , H01L2224/0392 , H01L2224/05022 , H01L2224/05027 , H01L2224/05082 , H01L2224/05124 , H01L2224/05155 , H01L2224/05582 , H01L2224/05647 , H01L2224/05666 , H01L2224/05681 , H01L2224/05686 , H01L2224/11462 , H01L2224/11849 , H01L2224/13082 , H01L2224/13111 , H01L2224/13139 , H01L2224/13147 , H01L2924/014 , H01L2924/04953
摘要： A method of manufacturing a semiconductor device is provided. The method includes forming a conductive probe plug on an exposed portion of a die pad of a semiconductor die by way of an electroless plating process. A top surface of the conductive probe plug extends above a top surface of a top passivation layer of the semiconductor die. A copper pillar is formed over the conductive probe plug by way of an electrolytic plating process. Outer sidewalls of the copper pillar surround the top surface of the conductive probe plug. A top surface of the copper pillar is plated with a solder plate material and reflowed to form a solder cap on the top of the copper pillar.

2. 发明授权

US12063057B2 Signal coupler 有权
公开(公告)号：US12063057B2
公开(公告)日：2024-08-13
申请号：US17648967
申请日：2022-01-26
申请人： NXP USA, INC.
发明人： Yi Yin , Birama Goumballa
IPC分类号： H01P5/18 , H04B1/18 , H04B3/56 , H04L25/02
CPC分类号： H04B1/18 , H04B3/56 , H04L25/0226
摘要： A signal coupler (100) comprising: a main-transmission-line (114) that extends in a longitudinal direction within a substrate (102) between an input port and an output port; and a coupled-transmission-line (116) that extends in the longitudinal direction within the substrate (102) between a coupled port and a termination port. The coupled-transmission-line (116) is in a second layer (110). The main-transmission-line (114) comprises a first-portion (120) in a first layer (108), a second-portion (122) in a second layer (110), and a third-portion (124) in a third layer (112). At least part of the first-portion (120) is spaced apart from the coupled-transmission-line (116) in a depth direction. At least part of the second-portion (122) is spaced apart from the coupled-transmission-line (116) in the depth direction. At least part of the third-portion (124) is spaced apart from the coupled-transmission-line (116) in the depth direction.

3. 发明授权

US12058615B2 Device and method for multi-link communications 有权
公开(公告)号：US12058615B2
公开(公告)日：2024-08-06
申请号：US17510222
申请日：2021-10-25
申请人： NXP USA, Inc.
发明人： Young Hoon Kwon , Liwen Chu , Hongyuan Zhang
IPC分类号： H04W52/02 , H04W48/10 , H04W84/12
CPC分类号： H04W52/0216 , H04W48/10 , H04W84/12
摘要： Embodiments of a device and a method for multi-link communications are disclosed. In an embodiment, a device includes a processor configured to identify that an update event has occurred on a first link of an access point (AP) multi-link device (MLD), and transmit a management frame on a second link, where the management frame includes a Change Sequence field and a multi-link (ML) element that indicates the update event.

4. 发明授权

US12055568B2 Dual current sensing 有权
公开(公告)号：US12055568B2
公开(公告)日：2024-08-06
申请号：US17874163
申请日：2022-07-26
申请人： NXP USA, Inc.
发明人： Giuseppe Luciano
IPC分类号： G01R19/00
CPC分类号： G01R19/0092
摘要： Provided is a current-sensing circuit that includes a power-supply line providing electrical power to a high side of a load, a high-side field-effect transistor (FET) component between the power-supply line and the high side of the load, and a low-side FET component coupled to a low side of the load. Gate signals continually repeat a cycle that includes: a first part in which the high-side FET component is turned on and the low-side FET component is turned off, and a second part in which the high-side FET component is turned off and the low-side FET component is turned on. In addition, a single transconductance stage is configured to: input signals indicating a voltage drop across whichever one of the high-side FET component or the low-side FET component currently is on, and output a signal indicating a current flow that corresponds to such voltage drop.

5. 发明公开

US20240251442A1 MULTI-AP TRANSMISSION WITH INTERFERENCE ALIGNMENT 审中-公开
公开(公告)号：US20240251442A1
公开(公告)日：2024-07-25
申请号：US18417459
申请日：2024-01-19
申请人： NXP USA, Inc.
发明人： Hari Ram Balakrishnan , Sudhir Srinivasa
IPC分类号： H04W74/0816 , H04L5/00 , H04L25/02 , H04W16/28
CPC分类号： H04W74/0816 , H04L5/0053 , H04L25/0204 , H04W16/28
摘要： Embodiments of a method and apparatus for wireless communications are disclosed. In an embodiment, a wireless device includes a controller configured to generate a trigger packet indicating that wireless access points (APs) can join coordinated transmission with the wireless device and a wireless transceiver configured to transmit the trigger packet to the wireless APs.

6. 发明授权

US12047100B2 System and method for digital predistortion 有权
公开(公告)号：US12047100B2
公开(公告)日：2024-07-23
申请号：US18085303
申请日：2022-12-20
申请人： NXP USA, Inc.
发明人： Mir Adeel Masood , Peter Zahariev Rashev
IPC分类号： H04B1/04
CPC分类号： H04B1/0475 , H04B2001/0425
摘要： Systems and methods for digital predistortion (DPD) are disclosed herein. In an example embodiment, a digital front-end circuit includes a DPD block, power amplifier, and transmitter. The DPD block is configured to receive an input signal and to provide a first output signal, and includes a nonlinear model that is configured to generate a nonlinear model output signal based upon the input signal. The DPD block additionally includes a first mixing module that is configured to generate a mixing module output signal based upon the input signal and the nonlinear model output signal. The DPD block further includes a summation block that is configured to generate the first output signal at least in part as a first sum of the nonlinear model output signal and the mixing module output signal, and the first mixing module includes a plurality of first finite impulse response (FIR) filters.

7. 发明公开

US20240243529A1 COMPACT CONNECTORS WITH INTEGRATED WIRELESS COMMUNICATION ELEMENTS 审中-公开
公开(公告)号：US20240243529A1
公开(公告)日：2024-07-18
申请号：US18154009
申请日：2023-01-12
申请人： NXP USA, Inc.
发明人： Jinbang Tang
IPC分类号： H01R13/66 , G08B21/18 , H04M1/02
CPC分类号： H01R13/6691 , G08B21/18 , H04M1/0274 , H01R24/60
摘要： An electrical connector port disposed within a mobile device such as a smart phone is provided with a wireless antenna coupled to the electrical connector port which. A housing of the connector port, together with the antenna, defines a directional antenna gain pattern enabling the wireless antenna to be used for directional communication between the mobile device and another device.

8. 发明公开

US20240241780A1 CENTRAL PROCESSING UNIT SYSTEM AND METHOD WITH IMPROVED SELF-CHECKING 审中-公开
公开(公告)号：US20240241780A1
公开(公告)日：2024-07-18
申请号：US18191616
申请日：2023-03-28
申请人： NXP USA, Inc.
发明人： Iani Bogdan Almajan , Julien Olivain , Joseph Charles Circello
IPC分类号： G06F11/07 , G06F9/38
CPC分类号： G06F11/079 , G06F9/3802 , G06F11/0721
摘要： Self-checking central processing unit (CPU) systems and methods are provided, in which the self-checking CPU systems include a core monitor that performs checking functions to monitor and verify the executions of a primary CPU. The primary CPU has a primary processor pipeline, and the core monitor has a checker pipeline that is parallel to the primary processor pipeline. The core monitor performs checking functions during each stage of the primary processor pipeline, where the type of each checking function is based on a corresponding type of function being performed by the primary CPU. For example, the core monitor may perform parity checking for data transfers and logical operations performed by the primary CPU, and residue checking for arithmetic instruction execution logic performed by the primary CPU.

9. 发明授权

US12040754B2 Amplifier circuit with an output limiter 有权
公开(公告)号：US12040754B2
公开(公告)日：2024-07-16
申请号：US17349096
申请日：2021-06-16
申请人： NXP USA, INC.
发明人： Pierre Pascal Savary , Stephane Damien Thuriés
IPC分类号： H03F1/02 , G01S7/03 , H03F1/56 , H03F3/195 , H03F3/45 , G01S13/931
CPC分类号： H03F1/565 , G01S7/03 , H03F1/0233 , H03F3/195 , H03F3/45475 , G01S13/931 , H03F2200/129 , H03F2200/451
摘要： An amplifier circuit comprising:

an amplifier;
an output limiter for providing a variable impedance comprising:

a first and second limiter terminal; a transistor comprising a conduction channel; a first resistor coupled in parallel with the conduction channel; and a capacitor coupled in series with the conduction channel between the conduction channel and the first or second limiter terminal; and

a feedback control unit comprising a comparator block configured to provide a control signal to the output limiter based on a comparison of the amplifier output signal and a setting voltage;
wherein: the first limiter terminal is coupled to the amplifier input or output; the second limiter terminal receives a reference voltage; and wherein receipt of the control signal at the transistor provides for a variable impedance for the amplifier circuit dependent on the amplifier output signal.

10. 发明授权

US12032088B2 Device for radar sensor, IC for a radar sensor and a radar sensor 有权
公开(公告)号：US12032088B2
公开(公告)日：2024-07-09
申请号：US16879476
申请日：2020-05-20
申请人： NXP USA, Inc.
发明人： Maik Brett , Ryan Haoyun Wu , Arunesh Roy
IPC分类号： G01S13/34 , G01S7/00 , G01S7/02 , G01S13/931 , G01S7/03 , H04B1/04 , H04B1/16 , H04B1/69 , H04W4/38
CPC分类号： G01S7/006 , G01S7/023 , G01S7/0232 , G01S7/0235 , G01S13/345 , G01S13/931 , G01S7/022 , G01S7/032 , G01S13/343 , G01S2013/9316 , H04B1/04 , H04B1/16 , H04B1/69 , H04B2001/6912 , H04W4/38
摘要： A device for a radar sensor is disclosed, the device comprising: transmission circuitry configured to generate transmission signals with a linear frequency chirp modulation in a predetermined frequency band for output to a radar antenna; reception circuitry configured to receive reflection signals corresponding to reflection of the transmitted radar signals from one or more physical objects; and control circuitry configured to select a frequency range within said predetermined frequency band and/or a timing pattern for said transmission signals; wherein said device is configured to: receive a further signal from a further radar sensor; determine, from said further signal, a frequency range and/or timing pattern in use by said further radar sensor for transmission of further transmission signals; and select a frequency range within said predetermined frequency band and/or a timing pattern for said transmission signals which does not conflict with the frequency range and/or timing pattern of said further transmission signals.

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