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91. 发明授权

US08772157B2 Method of forming Cu interconnects 有权
标题翻译：形成铜互连的方法
公开(公告)号：US08772157B2
公开(公告)日：2014-07-08
申请号：US13667492
申请日：2012-11-02
申请人： Jingxun Fang
发明人： Jingxun Fang
IPC分类号： H01L21/768
CPC分类号： H01L21/7684 , H01L21/32115 , H01L21/3212
摘要： The present invention provides a method of forming Cu interconnects. The method comprises depositing an etch stop layer and an insulating layer subsequently; forming vias and trenches in the insulating layer; depositing a diffusion barrier layer and a copper seed layer using PVD; applying electroplating process to form the copper interconnects; depositing a layer of filling materials and reflowing the filling materials to eliminate the uneven surface topography of the copper interconnection layer; and applying annealing and CMP to planarize the top surface of the copper interconnects, and rinsing. According to the method of forming Cu interconnects, the uneven surface topography after electroplating can be reduced, and the surface topography after CMP can be planarized.
摘要翻译：本发明提供一种形成Cu互连的方法。该方法包括随后沉积蚀刻停止层和绝缘层; 在绝缘层中形成通孔和沟槽; 使用PVD沉积扩散阻挡层和铜籽晶层; 应用电镀工艺形成铜互连; 沉积一层填充材料并回流填充材料以消除铜互连层的不平坦表面形貌; 并且对退火和CMP进行平坦化以使铜互连的顶表面平坦化，并进行漂洗。根据形成Cu互连的方法，可以减少电镀后的不平坦表面形貌，并且CMP之后的表面形貌可以平坦化。

92. 发明申请

US20140153000A1 APPARATUS FOR DETECTING THE FLATNESS OF WAFER AND THE METHOD THEREOF 有权
标题翻译：用于检测波形平坦度的装置及其方法
公开(公告)号：US20140153000A1
公开(公告)日：2014-06-05
申请号：US14092056
申请日：2013-11-27
申请人： Shanghai Huali Microelectronics Corporation
发明人： WenLiang Li , LiJun Chen , Jun Zhu , HsuSheng Chang
IPC分类号： G01B11/30
CPC分类号： G01B11/306 , B24B37/042 , B24B37/105 , B24B37/30 , G01B11/303
摘要： An apparatus for detecting the flatness of a top surface of a wafer includes a plurality of detector elements, a metal sink and a plurality of injection pipes. Each detector element comprises: a metal tube body, jet pipes, a light receiver and a light emitter. The method comprises: injecting ultra-pure water into the detector elements by injection pipes; emitting parallel beams along an upward-oblique direction, a preset Angle θ being formed between the beams and the vertical direction. The radiated beams above the water surface are incident on a receiver. The intensity of the beams received by the light receiver is used to calculate the height of the detecting point of the surface of the silicon wafer to determine the flatness condition of the wafer surface. The flatness of the photo-resist covered on the wafer surface can also be accurately measured by this method.
摘要翻译：用于检测晶片的顶面的平坦度的装置包括多个检测器元件，金属槽和多个注入管。每个检测器元件包括：金属管体，喷射管，光接收器和发光器。该方法包括：通过注射管将超纯水注入检测器元件; 沿着向上倾斜的方向发射平行光束，预设的角度和角度; 形成在梁和垂直方向之间。水面以上的辐射光束入射到接收器上。由光接收器接收的光束的强度用于计算硅晶片表面的检测点的高度，以确定晶片表面的平坦度状态。也可以通过该方法精确地测量覆盖在晶片表面上的光致抗蚀剂的平坦度。

93. 发明申请

US20140077343A1 DUMMY WAFER STRUCTURE AND METHOD OF FORMING THE SAME 有权
标题翻译：疏水结构及其形成方法
公开(公告)号：US20140077343A1
公开(公告)日：2014-03-20
申请号：US13730576
申请日：2012-12-28
申请人： SHANGHAI HUALI MICROELECTRONICS CORPORATION
发明人： Chuan REN , Zhi WANG , HsuSheng CHANG
IPC分类号： H01L29/06 , H01L21/02
CPC分类号： H01L29/0603 , C23C16/345 , C23C16/402 , H01L21/02164 , H01L21/0217 , H01L21/022 , H01L21/02271 , H01L21/3205 , H01L21/32055
摘要： A dummy wafer structure and a method of forming the same are disclosed. The dummy wafer structure includes: a silicon substrate; a silicon nitride layer over the silicon substrate; and a silicon dioxide layer over the silicon nitride layer. The method includes: a first step of forming a silicon nitride layer over a silicon substrate so as to form a silicon-silicon nitride structure; and a second step of forming a silicon dioxide layer over the silicon-silicon nitride structure obtained in the first step so as to form a silicon-silicon nitride-silicon dioxide structure. Dummy wafers with this special structure are able to avoid deposition rate inconsistency in a polysilicon deposition process and are capable of avoiding conventional dummy wafers' adverse effect on deposit layer thicknesses of process wafers and hence providing the process wafers with deposit layers having a high inter-wafer uniformity.
摘要翻译：公开了一种虚设晶片结构及其形成方法。虚设晶片结构包括：硅衬底; 硅衬底上的氮化硅层; 以及氮化硅层上的二氧化硅层。该方法包括：在硅衬底上形成氮化硅层以形成硅 - 氮化硅结构的第一步骤; 以及在第一步骤中获得的硅 - 氮化硅结构上形成二氧化硅层以形成硅 - 氮化硅 - 二氧化硅结构的第二步骤。具有这种特殊结构的虚拟晶片能够避免多晶硅沉积工艺中的沉积速率不一致，并且能够避免常规的虚设晶片对工艺晶片的沉积层厚度的不利影响，并且因此为工艺晶片提供具有高间隔的沉积层，晶圆均匀性。

94. 发明授权

US08645879B2 Algorithm of Cu interconnect dummy inserting 有权
标题翻译：铜互连虚拟插入算法
公开(公告)号：US08645879B2
公开(公告)日：2014-02-04
申请号：US13731128
申请日：2012-12-31
申请人： Shanghai Huali Microelectronics Corporation
发明人： Jingxun Fang , Hsusheng Chang , Yungchieh Fan
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： The present invention disclosed an algorithm of Cu interconnect dummy inserting, including: divide the surface of semiconductor chip into several square windows with an area of A, each of which is non-overlap; perform a logic operation on each square window; and divide the window into two parts: {circle around (1)} the area to-be-inserted; {circle around (2)} the non-inserting area; determine the metal density of the dummy pattern that should be inserted to each square window and the line width; determine the dummy pattern that should be inserted to the windows according to the metal density, line width, the pre-set dummy pattern and the layouting rules. The beneficial effects of the present invention is: avoided the shortcomings of fill density maximization in the rule-based filling method by using reasonable metal density and line width. And with a combination of the influence of line width and density to the copper plating process and chemical mechanical polishing morphology in model-based filling method, it can achieve a better planarization effect.
摘要翻译：本发明公开了一种Cu互连虚拟插入算法，包括：将半导体芯片的表面划分成几个方形窗口，其面积为A，每个窗口不重叠; 对每个方形窗口执行逻辑运算; 并将窗口分为两部分：{circle around（1）}要插入的区域; {round around（2）}非插入区域; 确定应插入每个正方形窗口的虚拟图案的金属密度和线宽度; 根据金属密度，线宽，预设的伪图案和布局规则确定应插入窗口的虚拟图案。本发明的有益效果是：通过使用合理的金属密度和线宽，避免了基于规则的填充方法中填充密度最大化的缺点。并结合线宽和密度对铜电镀工艺和化学机械抛光形态的影响，在基于模型的填充方法中，可以实现更好的平坦化效果。

95. 发明申请

US20130316470A1 METHOD WHICH CAN FORM CONTACT HOLES IN WAFER OF SEMICONDUCTOR 审中-公开
标题翻译：可以形成半导体波形接触孔的方法
公开(公告)号：US20130316470A1
公开(公告)日：2013-11-28
申请号：US13707485
申请日：2012-12-06
申请人： SHANGHAI HUALI MICROELECTRONICS CORPORATION
发明人： Jun ZHOU
IPC分类号： H01L21/66
CPC分类号： H01L22/26 , H01L21/3086 , H01L21/76816 , H01L22/12 , H01L22/20
摘要： The present invention relates to the field of semiconductor integrated circuits, and particularly relates to a method which can form a contact hole in a wafer of semiconductor material. The invention has proposed a method which can form a contact hole in a wafer of semiconductor: measuring and comparing a Critical Dimension (CD) of a position corresponding to the contact hole in the hard mask with the CD required in the technology, and then, based on the measurement, adjusting the CD of the position corresponding to the contact hole in the hard mask, by conformal deposition or etching technology, to fit a requirement of the technology; the method can reduce process costs while improving production capacity.
摘要翻译：本发明涉及半导体集成电路领域，特别涉及能够在半导体材料的晶片中形成接触孔的方法。本发明提出了一种可以在半导体晶片中形成接触孔的方法：测量并比较与硬掩模中的接触孔相对应的位置的临界尺寸（CD）与该技术中所需的CD，基于测量，通过适形沉积或蚀刻技术调整与硬掩模中的接触孔相对应的位置的CD，以适应该技术的要求; 该方法可以在提高生产能力的同时降低工艺成本。

96. 发明申请

US20130273742A1 METHOD OF FORMING CONNECTION HOLES 有权
标题翻译：形成连接孔的方法
公开(公告)号：US20130273742A1
公开(公告)日：2013-10-17
申请号：US13721070
申请日：2012-12-20
申请人： SHANGHAI HUALI MICROELECTRONICS CORPORATION
发明人： Yushu YANG , Cheng LI , Yuwen CHEN
IPC分类号： H01L21/306
CPC分类号： H01L21/30604 , H01L21/31116 , H01L21/76816
摘要： The present invention provides a method of forming connection holes. The method utilizes two different gases to perform two etching processes for the interlayer dielectric layer so as to form connection holes. The etching rate of the interlayer dielectric layer in the first etching process using the first etching gas is proportional to the size of the openings which defines the connection hole while the etching rate of the interlayer dielectric layer in the second etching process using the second etching gas is inversely related with size of the openings. According to the present invention, the first etching gas and the second etching gas compensate for each other to eliminate the loading effect, thus the connection holes are formed with almost the same depth. Therefore the damage of the etching stopper layer due to the high etching rate in the larger connection holes can be avoided, which prevents the excessive variation of the connecting resistance and expands the process window.
摘要翻译：本发明提供一种形成连接孔的方法。该方法利用两种不同的气体对层间电介质层进行两次蚀刻处理，形成连接孔。使用第一蚀刻气体的第一蚀刻工艺中的层间电介质层的蚀刻速率与限定连接孔的开口的尺寸成比例，而在使用第二蚀刻气体的第二蚀刻工艺中的层间电介质层的蚀刻速率与开口的尺寸成反比。根据本发明，第一蚀刻气体和第二蚀刻气体彼此补偿以消除负载效应，因此连接孔形成有几乎相同的深度。因此，可以避免由于较大的连接孔中的高蚀刻速率导致的蚀刻阻挡层的损伤，这防止了连接电阻的过度变化并扩大了工艺窗口。

97. 发明授权

US08541307B2 Treatment method for reducing particles in dual damascene silicon nitride process 有权
标题翻译：双镶嵌氮化硅工艺中还原颗粒的处理方法
公开(公告)号：US08541307B2
公开(公告)日：2013-09-24
申请号：US13339400
申请日：2011-12-29
申请人： Meimei Gu , Duoyuan Hou , Jun Xu , Ke Wang
发明人： Meimei Gu , Duoyuan Hou , Jun Xu , Ke Wang
IPC分类号： H01L21/44
CPC分类号： H01L21/76883 , H01L21/02074 , H01L21/0217 , H01L21/02301 , H01L21/02315 , H01L21/76834
摘要： A treatment method for reducing particles in a Dual Damascene Silicon Nitride (DDSN) process, including the following steps: forming a seed layer of copper on a silicon wafer; depositing a deposition layer of copper to cover the seed layer of copper; planarizing the deposition layer of copper; providing the silicon wafer into a reaction chamber and performing a pre-treatment on a surface of the deposition layer of copper using NH3 gas under a plasma condition so as to reduce copper oxide (CuO) to copper (Cu) formed on the deposition layer of copper; in the reaction chamber, generating an etching block layer on the deposition layer of copper using a DDSN deposition process; cleaning the reaction chamber using NF3 gas; and directing N2O gas into the reaction chamber and removing the remaining hydrogen (H) and fluorine (F) in the reaction chamber using the N2O gas under the plasma condition.
摘要翻译：一种用于减少双镶嵌氮化硅（DDSN）工艺中的颗粒的处理方法，包括以下步骤：在硅晶片上形成铜种子层; 沉积铜沉积层以覆盖铜的籽晶层; 平坦化铜的沉积层; 将硅晶片提供到反应室中，并且在等离子体条件下使用NH 3气体在铜的沉积层的表面上进行预处理，以将氧化铜（CuO）还原成形成在沉积层上的铜（Cu）铜; 在反应室中，使用DDSN沉积工艺在铜的沉积层上产生蚀刻阻挡层; 使用NF3气体清洗反应室; 并在等离子体条件下使用N2O气体将N 2 O气体引入反应室并除去反应室中剩余的氢（H）和氟（F）。

98. 发明授权

US08518825B1 Method to manufacture trench-first copper interconnection 有权
标题翻译：制造沟槽第一铜互连的方法
公开(公告)号：US08518825B1
公开(公告)日：2013-08-27
申请号：US13726532
申请日：2012-12-24
申请人： Zhibiao Mao
发明人： Zhibiao Mao
IPC分类号： H01L21/44 , H01L21/00 , H01L21/4763 , H01L21/31 , H01L21/469 , H01L23/48 , H01L23/52
CPC分类号： H01L21/0273 , H01L21/31144 , H01L21/76811 , H01L21/76816 , H01L2924/0002
摘要： The present invention relates to manufacturing technology of damascene copper interconnection in the semiconductor manufacturing field, and especially relates to a method to manufacture by trench-first copper interconnection. The method to manufacture trench-first copper interconnection forms metal trench and VIA hole structures in the photoresist which can form a hard mask through exposure and development processes, and then forms metal interconnection lines via etching metal trench and VIA hole in one etch process. The above method replaces the existing.
摘要翻译：本发明涉及半导体制造领域的镶嵌铜互连的制造技术，特别涉及通过沟槽第一铜互连制造的方法。制造沟槽第一铜互连的方法在光致抗蚀剂中形成金属沟槽和VIA孔结构，其可以通过曝光和显影工艺形成硬掩模，然后在一个蚀刻工艺中通过蚀刻金属沟槽和VIA孔形成金属互连线。上述方法取而代之。

99. 发明授权

US08426288B2 Method for improving capacitance uniformity in a MIM device 有权
标题翻译：用于改善MIM器件中的电容均匀性的方法
公开(公告)号：US08426288B2
公开(公告)日：2013-04-23
申请号：US13339406
申请日：2011-12-29
申请人： Qiang Xu , Wenguang Zhang , Chunsheng Zheng , Yuwen Chen
发明人： Qiang Xu , Wenguang Zhang , Chunsheng Zheng , Yuwen Chen
IPC分类号： H01L21/02
CPC分类号： H01L28/40 , C23C16/345 , C23C16/45523 , C23C16/505 , C23C16/56
摘要： A method for improving capacitance uniformity in a MIM device, mainly for the purpose of improving uniformity of a thin film within the MIM device, includes eight steps in order and step S2-step S6 may be repeated for several times as needed. According to the method for improving capacitance uniformity in a MIM device of the present invention, a certain quantity of defects in the thin film are removed by means of several times of deposition/plasma processes based on the current PECVD, and uniformity of the deposited thin film is increased, thereby improving uniformity in wet etching rate of the thin film and further improving capacitance uniformity in the MIM device.
摘要翻译：主要用于提高MIM器件内的薄膜均匀性的MIM器件中的电容均匀性的改善方法包括8个步骤，并且步骤S2的步骤S6可根据需要重复多次。根据本发明的MIM器件中的电容均匀性的提高方法，通过基于当前PECVD的多次沉积/等离子体处理，去除薄膜中的一定量的缺陷，并且沉积的薄膜膜增加，从而提高了薄膜的湿蚀刻速度的均匀性，并且进一步提高了MIM器件中的电容均匀性。

100. 发明申请

US20120276820A1 Method for Adjusting Metal Polishing Rate and Reducing Defects Arisen in a Polishing Process 审中-公开
标题翻译：调整金属抛光速率和减少抛光过程中出现的缺陷的方法
公开(公告)号：US20120276820A1
公开(公告)日：2012-11-01
申请号：US13339538
申请日：2011-12-29
申请人： Shoulong Zhang , Yingying Bai , Yuwen Chen
发明人： Shoulong Zhang , Yingying Bai , Yuwen Chen
IPC分类号： B24B1/00
CPC分类号： H01L21/7684 , B24B37/046 , B24B37/22 , B24B37/24 , H01L21/32125
摘要： The invention discloses a method for adjusting metal polishing rate and reducing defects arisen in a polishing process, in which a electric conduction system is additionally provided to a polishing apparatus to electrify the polishing fluid; in the polishing process, the polishing fluid flows through the polishing pad and the wafer to be polished, such that the polished metal surface of the wafer is electrically charged so as to control the oxidation of the polished metal surface of the wafer. The invention has solved the problem that the dishing and erosion defects are prone to be formed in the existing polishing process, the potential of the polishing fluid is changed by means of the additional electric conduction system and thus the polishing rate of the polished metal is controlled so as to reduce the dishing and erosion defects occurred in the polishing process.
摘要翻译：本发明公开了一种用于调整金属抛光速率并减少在抛光工艺中产生的缺陷的方法，其中将电传导系统附加地提供给抛光装置以使抛光液带电; 在抛光过程中，抛光液流过待研磨的抛光垫和晶片，使得抛光的晶片的金属表面被带电，以便控制晶片抛光的金属表面的氧化。本发明解决了在现有的抛光工艺中容易形成凹陷和侵蚀缺陷的问题，通过附加的导电系统改变抛光液的电位，从而控制抛光金属的抛光速度以减少抛光过程中发生的凹陷和侵蚀缺陷。

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