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91. 发明授权

US07800091B2 Nonvolatile semiconductor memory device and manufacturing method thereof 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US07800091B2
公开(公告)日：2010-09-21
申请号：US12108783
申请日：2008-04-24
申请人： Takeshi Kamigaichi , Hirofumi Inoue
发明人： Takeshi Kamigaichi , Hirofumi Inoue
IPC分类号： H01L29/04
CPC分类号： H01L27/2409 , H01L27/2436 , H01L27/249 , H01L45/04 , H01L45/1226 , H01L45/146 , H01L45/147
摘要： A nonvolatile semiconductor memory device includes a first stacked structure in which a plurality of electrode layers are stacked on a substrate via insulating layers, a first resistance changing layer provided on a side surface of the first stacked structure and in contact with the first electrode layers, the first resistance changing layer having a resistance value changing on the basis of an applied voltage, a second electrode layer provided on a side surface of the first resistance changing layer, and a bit line provided on the first stacked structure and electrically connected to the second electrode layer.
摘要翻译：非易失性半导体存储器件包括：第一堆叠结构，其中多个电极层经由绝缘层堆叠在衬底上;第一电阻改变层，设置在第一堆叠结构的侧表面上并与第一电极层接触; 所述第一电阻变化层具有基于施加电压而变化的电阻值，设置在所述第一电阻变化层的侧面上的第二电极层和设置在所述第一堆叠结构上并与所述第二电阻变化层电连接的位线电极层。

92. 发明申请

US20100186996A1 THERMOSETTING RESIN COMPOSITION 有权
标题翻译：热固性树脂组合物
公开(公告)号：US20100186996A1
公开(公告)日：2010-07-29
申请号：US12669416
申请日：2008-07-11
申请人： Tomokazu Umezawa , Tetsuo Wada , Hirofumi Inoue
发明人： Tomokazu Umezawa , Tetsuo Wada , Hirofumi Inoue
IPC分类号： H05K1/02 , C08L75/04
CPC分类号： H05K3/285 , C08G59/4246 , H01L23/293 , H01L2924/0002 , H05K2203/124 , Y10T428/31551 , Y10T428/31605 , Y10T428/31609 , H01L2924/00
摘要： The thermosetting resin composition according to the present invention includes a resin (A) containing two or more carboxyl groups and having a polyurethane structure, a strongly basic nitrogen-containing heterocyclic compound having pKa of 10.0 to 14.0 as a curing accelerator (B) and a curing agent (C). A cured product of the thermosetting resin composition is used as an insulating protective film for printed wiring boards, flexible printed wiring boards, chip-on-films, etc. The thermosetting resin composition of the invention has improved low-temperature curability and instantaneous curability, can realize tack-free property, can simultaneously realize low warpage property and electrical insulation property, does not contaminate a curing oven and the like by outgassing during heating, has a sufficient pot life, can form excellent cured products and insulating protective films, and can form solder resists and insulating protective films at low cost with good productivity.
摘要翻译：根据本发明的热固性树脂组合物包含含有两个或更多个羧基并具有聚氨酯结构的树脂（A），作为固化促进剂（B）的pKa为10.0〜14.0的强碱性含氮杂环化合物和固化剂（C）。热固性树脂组合物的固化物用作印刷线路板，柔性印刷电路板，片上胶片等的绝缘保护膜。本发明的热固性树脂组合物具有改善的低温固化性和瞬时固化性，可实现无粘性，可同时实现低翘曲性和电绝缘性，加热时除气不会污染固化炉等，具有足够的使用期限，可形成优良的固化产物和绝缘保护膜，并可以低成本形成阻焊和绝缘保护膜，生产率高。

93. 发明申请

US20100038616A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND PRODUCING METHOD THEREOF 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20100038616A1
公开(公告)日：2010-02-18
申请号：US12540092
申请日：2009-08-12
申请人： Hiroyuki NAGASHIMA , Hirofumi Inoue , Hideyuki Tabata , Masanori Komura , Eiji Ito
发明人： Hiroyuki NAGASHIMA , Hirofumi Inoue , Hideyuki Tabata , Masanori Komura , Eiji Ito
IPC分类号： H01L47/00
CPC分类号： H01L27/1116 , H01L27/0207 , H01L27/0688 , H01L27/101 , H01L27/105 , H01L27/115 , H01L27/2409 , H01L27/2418 , H01L27/2481 , H01L45/085 , H01L45/1233 , H01L45/147 , H01L45/1675
摘要： A cell array includes a memory cell region in which memory cells are formed and a peripheral region that is provided around the memory cell region. In the memory cell region, first lines are extended in parallel with a first direction, and the first lines are repeatedly formed at first intervals in a second direction orthogonal to the first direction. In the peripheral region, each of the first lines located at (4n−3)-th (n is a positive integer) and (4n−2)-th positions in the second direction from a predetermined position has a contact connecting portion on one end side in the first direction of the first line. In the peripheral region, each of the first lines located at (4n−1)-th and 4n-th positions in the second direction from the predetermined position has the contact connecting portion on the other end side in the first direction of the first line. The contact connecting portion is formed so as to contact a contact plug extended in a laminating direction.
摘要翻译：单元阵列包括其中形成存储器单元的存储单元区域和设置在存储单元区域周围的外围区域。在存储单元区域中，第一线与第一方向平行地延伸，并且第一线在与第一方向正交的第二方向上以第一间隔重复形成。在外围区域中，位于第（4n-3）（n为正整数）的第一线和从预定位置起的第二方向的第（4n-2）个位置中的每一个在一个上具有接触连接部在第一行的第一个方向的端部。在周边区域中，位于距规定位置的第二方向（4n-1）和第4n位置的第一线的第一线在第一线的第一方向的另一端侧具有接触连接部。接触连接部形成为与层叠方向延伸的接触插塞接触。

94. 发明授权

US07628050B2 Press-working method 失效
标题翻译：新闻工作方式
公开(公告)号：US07628050B2
公开(公告)日：2009-12-08
申请号：US11519187
申请日：2006-09-11
申请人： Toshio Nishi , Hirofumi Inoue
发明人： Toshio Nishi , Hirofumi Inoue
IPC分类号： B21D28/00 , B21D31/02
CPC分类号： B21D5/01 , B21D53/84 , Y10T29/49789 , Y10T29/4998
摘要： A press-working method comprises: cutting out a member with a predetermined shape from a sheet material, the member having a longitudinal direction; bending the member with the predetermined shape to form a bottom portion and a wall portion extending at an angle from the bottom portion as seen in a direction along the longitudinal direction such that the bottom portion has an arched surface as seen in a side view, using at least one plunger and at least one die, wherein an edge of the wall portion is allowed to expand along the plunger and the die while changes in a thickness of the wall portion is controlled by the plunger and the die, and wherein the step of cutting out a member is performed such that the wall portion has an edge with a preset shape after the bending step.
摘要翻译：压制加工方法包括：从片材切割具有预定形状的构件，所述构件具有纵向方向; 以预定形状弯曲构件以形成底部和从沿着纵向的方向观察时从底部以一定角度延伸的壁部，使得底部具有如侧视图所示的拱形表面，使用至少一个柱塞和至少一个模具，其中所述壁部分的边缘允许沿着所述柱塞和所述模具膨胀，同时所述壁部分的厚度的变化由所述柱塞和所述模具控制，并且其中所述步骤执行切割部件，使得壁部在弯曲步骤之后具有预定形状的边缘。

95. 发明申请

US20090122598A1 RESISTANCE CHANGE MEMORY DEVICE 有权
标题翻译：电阻变化存储器件
公开(公告)号：US20090122598A1
公开(公告)日：2009-05-14
申请号：US12266879
申请日：2008-11-07
申请人： Haruki TODA , Hirofumi Inoue , Hiroto NAKAI
发明人： Haruki TODA , Hirofumi Inoue , Hiroto NAKAI
IPC分类号： G11C11/21 , G11C7/06
CPC分类号： G11C13/00 , G11C5/063 , G11C8/14 , G11C11/56 , G11C13/0028 , G11C13/004 , G11C2013/0054 , G11C2213/71 , G11C2213/72
摘要： A resistance change memory device includes: a memory cell array with memory cells arranged therein, the memory cell having a variable resistance element for storing a rewritable resistance value; a reference cell formed of the same memory cells as those set in a high resistance state in the memory cell array, the reference cell being trimmed with selection of the number of parallel-connected memory cells to have a reference current value used for detecting data in the memory cell array; and a sense amplifier configured to compare a cell current value of a memory cell selected in the memory cell array with the reference current value of the reference cell.
摘要翻译：电阻变化存储器件包括：存储单元阵列，其中布置有存储单元，所述存储单元具有用于存储可重写电阻值的可变电阻元件; 由与存储单元阵列中的高电阻状态相同的存储单元形成的参考单元，通过选择并联连接的存储单元的数量来修整参考单元以具有用于检测数据的参考电流值存储单元阵列; 以及读出放大器，被配置为将存储单元阵列中选择的存储单元的单元电流值与参考单元的参考电流值进行比较。

96. 发明授权

US07525142B2 Semiconductor device including a conductive layer buried in an opening and method of manufacturing the same 失效
标题翻译：包括埋在开口中的导电层的半导体器件及其制造方法
公开(公告)号：US07525142B2
公开(公告)日：2009-04-28
申请号：US11638492
申请日：2006-12-14
申请人： Hirofumi Inoue , Masahito Shinohe
发明人： Hirofumi Inoue , Masahito Shinohe
IPC分类号： H01L27/108
CPC分类号： H01L21/76877 , H01L21/76849 , H01L27/10867
摘要： A trench capacitor is formed in a semiconductor substrate with a capacitor insulating film. The trench has a conductive layer as storage node electrode buried in a trench. The conductive layer includes a first, a second, and third conductive layer. The first conductive layer is buried in a lower portion of the trench. The second conductive layer is buried in a recess on the upper surface of the first conductive layer. The third conductive layer is buried to contact with the first and second conductive layers.
摘要翻译：在具有电容器绝缘膜的半导体衬底中形成沟槽电容器。沟槽具有作为存储节点电极的导电层，埋入沟槽中。导电层包括第一，第二和第三导电层。第一导电层被埋在沟槽的下部。第二导电层被埋在第一导电层的上表面上的凹部中。掩埋第三导电层以与第一和第二导电层接触。

97. 发明申请

US20080315280A1 SEMICONDUCTOR MEMORY DEVICE HAVING MEMORY CELL UNIT AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：具有存储单元的半导体存储器件及其制造方法
公开(公告)号：US20080315280A1
公开(公告)日：2008-12-25
申请号：US12142274
申请日：2008-06-19
申请人： Shinichi WATANABE , Fumitaka Arai , Makoto Mizukami , Hirofumi Inoue , Masaki Kondo
发明人： Shinichi WATANABE , Fumitaka Arai , Makoto Mizukami , Hirofumi Inoue , Masaki Kondo
IPC分类号： H01L29/423 , H01L21/336
CPC分类号： H01L27/115 , H01L27/11526 , H01L27/11529
摘要： A semiconductor memory device includes a silicon substrate including a first region which has a buried insulating layer below a single-crystal silicon layer and a second region which does not have the buried insulating layer below the single-crystal silicon layer, at least one memory cell transistor which has a first gate electrode, the first gate electrode being provided on the single-crystal silicon layer in the first region, and at least one selective gate transistor which has a second gate electrode and is provided on the single-crystal silicon layer in the first region. The one selective gate transistor is provided in such a manner that a part of the second gate electrode is placed on the single-crystal silicon layer in the second region.
摘要翻译：一种半导体存储器件包括：硅衬底，其包括在单晶硅层下方具有掩埋绝缘层的第一区域和在单晶硅层下方不具有掩埋绝缘层的第二区域;至少一个存储单元晶体管，其具有第一栅极电极，第一栅电极设置在第一区域中的单晶硅层上，以及至少一个选择栅极晶体管，其具有第二栅电极，并设置在单晶硅层上第一个地区。一个选择栅极晶体管被设置成使得第二栅电极的一部分被放置在第二区域中的单晶硅层上。

98. 发明申请

US20080265235A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20080265235A1
公开(公告)日：2008-10-30
申请号：US12108783
申请日：2008-04-24
申请人： Takeshi Kamigaichi , Hirofumi Inoue
发明人： Takeshi Kamigaichi , Hirofumi Inoue
IPC分类号： H01L47/00 , H01L21/00
CPC分类号： H01L27/2409 , H01L27/2436 , H01L27/249 , H01L45/04 , H01L45/1226 , H01L45/146 , H01L45/147
摘要： A nonvolatile semiconductor memory device includes a first stacked structure in which a plurality of electrode layers are stacked on a substrate via insulating layers, a first resistance changing layer provided on a side surface of the first stacked structure and in contact with the first electrode layers, the first resistance changing layer having a resistance value changing on the basis of an applied voltage, a second electrode layer provided on a side surface of the first resistance changing layer, and a bit line provided on the first stacked structure and electrically connected to the second electrode layer.
摘要翻译：非易失性半导体存储器件包括：第一堆叠结构，其中多个电极层经由绝缘层堆叠在衬底上;第一电阻改变层，设置在第一堆叠结构的侧表面上并与第一电极层接触; 所述第一电阻变化层具有基于施加电压而变化的电阻值，设置在所述第一电阻变化层的侧面上的第二电极层和设置在所述第一堆叠结构上并与所述第二电阻变化层电连接的位线电极层。

99. 发明申请

US20070209190A1 Press-working method 失效
标题翻译：新闻工作方式
公开(公告)号：US20070209190A1
公开(公告)日：2007-09-13
申请号：US11519187
申请日：2006-09-11
申请人： Toshio Nishi , Hirofumi Inoue
发明人： Toshio Nishi , Hirofumi Inoue
IPC分类号： B21B1/46
CPC分类号： B21D5/01 , B21D53/84 , Y10T29/49789 , Y10T29/4998
摘要： A press-working method comprises: cutting out a member with a predetermined shape from a sheet material, the member having a longitudinal direction; bending the member with the predetermined shape to form a bottom portion and a wall portion extending at an angle from the bottom portion as seen in a direction along the longitudinal direction such that the bottom portion has an arched surface as seen in a side view, using at least one plunger and at least one die, wherein an edge of the wall portion is allowed to expand along the plunger and the die while changes in a thickness of the wall portion is controlled by the plunger and the die, and wherein the step of cutting out a member is performed such that the wall portion has an edge with a preset shape after the bending step.
摘要翻译：压制加工方法包括：从片材切割具有预定形状的构件，所述构件具有纵向方向; 以预定形状弯曲构件以形成底部和从沿着纵向的方向观察时从底部以一定角度延伸的壁部，使得底部具有如侧视图所示的拱形表面，使用至少一个柱塞和至少一个模具，其中所述壁部分的边缘允许沿着所述柱塞和所述模具膨胀，同时所述壁部分的厚度的变化由所述柱塞和所述模具控制，并且其中所述步骤执行切割部件，使得壁部在弯曲步骤之后具有预定形状的边缘。

100. 发明申请

US20070108474A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US20070108474A1
公开(公告)日：2007-05-17
申请号：US11616707
申请日：2006-12-27
申请人： Itaru Kawabata , Hirofumi Inoue
发明人： Itaru Kawabata , Hirofumi Inoue
IPC分类号： H01L29/76
CPC分类号： H01L27/1087 , H01L27/10867
摘要： A semiconductor device includes a semiconductor substrate formed with a plurality of trenches, a plurality of trench capacitor type DRAM unit cells including capacitors formed in the trenches and cell transistors formed to be adjacent to the trenches respectively, a plurality of impurity doped regions including boundaries connecting the trenches and the cell transistors and formed in outer peripheries of the trenches, respectively, and a plurality of reverse conduction type impurity regions formed by doping regions of the substrate under the cell transistors with impurity of a reverse conduction type relative to the impurity doped regions, respectively.
摘要翻译：半导体器件包括形成有多个沟槽的半导体衬底，包括形成在沟槽中的电容器和形成为与沟槽相邻的单元晶体管的多个沟槽电容器型DRAM单位单元，多个杂质掺杂区域，包括边界连接沟槽和单元晶体管分别形成在沟槽的外周边，以及多个反向导电型杂质区域，该多个反向导电型杂质区域通过在单元晶体管的下方掺杂具有相对于杂质掺杂区域的反向导电类型的杂质的区域而形成，分别。

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