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91. 发明授权

US06392456B1 Analog mixed digital DLL 有权
标题翻译：模拟混合数字DLL
公开(公告)号：US06392456B1
公开(公告)日：2002-05-21
申请号：US09427272
申请日：1999-10-26
申请人： Hong Beom Pyeon , Kyung Hoon Chang , Ju Han Kim
发明人： Hong Beom Pyeon , Kyung Hoon Chang , Ju Han Kim
IPC分类号： H03L706
CPC分类号： H03L7/0814 , Y10S331/02
摘要： An analog mixed digital DLL includes a digital mode controller and an analog mode controller. The digital mode controller compares phases of delay clock signals outputted from a plurality of delay blocks and a first clock signal, detects an initial locking point, selects one delay clock signal at the detected initial locking point and controls the operation of the delay clocks. The analog mode controller compares the phase of the delay clock signal selected by the digital mode controller and the phase of a first clock signal. The analog mixed digital DLL can provide an externally inputted first control voltage or a second control voltage to the delay blocks in accordance with the digital and analog operation modes and implements a wide band frequency operation, has a short duration of jitters, prevents a multi-locking during a wide band frequency operation and decreases a current consumption.
摘要翻译：模拟混合数字DLL包括数字模式控制器和模拟模式控制器。数字模式控制器比较从多个延迟块输出的延迟时钟信号和第一时钟信号的相位，检测初始锁定点，在检测到的初始锁定点选择一个延迟时钟信号，并控制延迟时钟的操作。模拟模式控制器比较由数字模式控制器选择的延迟时钟信号的相位和第一时钟信号的相位。模拟混合数字DLL可以根据数字和模拟操作模式向延迟块提供外部输入的第一控制电压或第二控制电压，并且实现宽带频率操作，具有短暂的抖动持续时间，在宽带频率操作期间锁定并且减少电流消耗。

92. 发明授权

US08904046B2 Apparatus and method for capturing serial input data 有权
标题翻译：用于捕获串行输入数据的装置和方法
公开(公告)号：US08904046B2
公开(公告)日：2014-12-02
申请号：US12879543
申请日：2010-09-10
申请人： Hong Beom Pyeon , HakJune Oh
发明人： Hong Beom Pyeon , HakJune Oh
IPC分类号： G06F3/00 , G11C7/10 , G06F13/28 , G11C5/06 , G06F13/16
CPC分类号： G11C5/066 , G06F13/1673 , G06F13/28 , G11C7/10 , G11C7/1078 , G11C7/1093 , G11C2207/107
摘要： A serial input processing apparatus provides how to capture serial data without loss of a single bit while command interpretation is being performed in a command decoder at high frequency. Individual bytes of serial bits of a pre-defined sequence are latched and bit streams are temporarily stored with multiple clocks. The temporary store is conducted before transferring byte information to assigned address registers to register the address. The address registration and the data registration are performed by latching all bit streams of the serial input at the leading edges of clocks. While at a high frequency operation (e.g., 1 GHz or 1 ns cycle time), no additional registers are required for storing bit data during command interpretation with enough time margins between the command bit stream interpretation and next bit data stream.
摘要翻译：串行输入处理装置提供如何在命令解码器中以高频执行命令解释时捕获串行数据而不丢失单个位。预定义序列的串行位的单个字节被锁存，并且使用多个时钟临时存储位流。在将字节信息传送到分配的地址寄存器之前进行临时存储，以注册地址。地址注册和数据登记是通过在时钟的前沿锁存串行输入的所有比特流来执行的。在高频操作（例如，1GHz或1ns周期时间）期间，在命令解释期间，在命令比特流解释和下一个比特数据流之间具有足够的时间余量，不需要额外的寄存器来存储比特数据。

93. 发明授权

US08880780B2 Apparatus and method for using a page buffer of a memory device as a temporary cache 有权
标题翻译：使用存储器件的页缓冲器作为临时缓存的装置和方法
公开(公告)号：US08880780B2
公开(公告)日：2014-11-04
申请号：US13215789
申请日：2011-08-23
申请人： Hong Beom Pyeon , Kin-Ki Kim , HakJune Oh
发明人： Hong Beom Pyeon , Kin-Ki Kim , HakJune Oh
IPC分类号： G06F13/00 , G06F13/28 , G06F13/42
CPC分类号： G06F13/4243 , G06F13/4247
摘要： An apparatus and method are provided for using a page buffer of a memory device as a temporary cache for data. A memory controller writes data to the page buffer and later reads out the data without programming the data into the memory cells of the memory device. This allows the memory controller to use the page buffer as temporary cache so that the data does not have to occupy space within the memory controller's local data storage elements. Therefore, the memory controller can use the space in its own storage elements for other operations.
摘要翻译：提供了一种使用存储器件的页缓冲器作为数据的临时缓存的装置和方法。存储器控制器将数据写入页缓冲器，并且随后读出数据而不将数据编程到存储器件的存储单元中。这允许存储器控制器使用页面缓冲器作为临时缓存，使得数据不必占用存储器控制器的本地数据存储元件内的空间。因此，存储器控制器可以将其自己的存储元件中的空间用于其他操作。

94. 发明授权

US08626958B2 Apparatus and method for producing device identifiers for serially interconnected devices of mixed type 失效
标题翻译：用于生产混合型串联互连设备的设备标识符的设备和方法
公开(公告)号：US08626958B2
公开(公告)日：2014-01-07
申请号：US13077168
申请日：2011-03-31
申请人： Hong Beom Pyeon , HakJune Oh , Jin-Ki Kim , Shuji Sumi
发明人： Hong Beom Pyeon , HakJune Oh , Jin-Ki Kim , Shuji Sumi
IPC分类号： G06F3/00
CPC分类号： G11C16/20 , G11C8/12
摘要： A plurality of memory devices of mixed type (e.g., DRAMs, SRAMs, MRAMs and NAND-, NOR- and AND-type Flash memories) are serially interconnected. Each device has device type information on its device type. A specific device type (DT) and a device identifier (ID) contained in a serial input (SI) are fed to one device of the serial interconnection. The device determines whether the fed DT matches the DT of the device. In a case of match, a calculator included in the device performs calculation to generate an ID for another device and the fed ID is latched in a register of the device. The generated ID is transferred to another device of the serial interconnection. In a case of no match, the ID generation is skipped and no ID is generated for another device. Such a device type match determination and ID generation or skip are performed in all devices of the serial interconnection. In cases of different device types being separately provided to the interconnected devices, sequential IDs are generated in each of the different device types and also the total number of each device type are recognized. In a case of a “don't care” code is provided to the interconnected devices, sequential IDs are generated and also, the total number of the interconnected devices is recognized, regardless of the type differences.
摘要翻译：多个混合型存储器件（例如，DRAM，SRAM，MRAM以及NAND，NOR和AND型闪存）串联连接。每个设备都有其设备类型的设备类型信息。包含在串行输入（SI）中的特定设备类型（DT）和设备标识符（ID）被馈送到串行互连的一个设备。设备确定馈送的DT是否匹配设备的DT。在匹配的情况下，包含在该设备中的计算器执行计算以生成另一设备的ID，并且将馈送的ID锁存在设备的寄存器中。生成的ID被传送到串行互连的另一个设备。在不匹配的情况下，跳过ID生成，并且不会为其他设备生成ID。在串行互连的所有设备中执行这样的设备类型匹配确定和ID生成或跳过。在将不同设备类型分别提供给互连设备的情况下，在不同设备类型中的每一种中生成顺序ID，并且还识别每种设备类型的总数。在向互连设备提供“不关心”代码的情况下，生成顺序ID，并且还识别互连设备的总数，而不管类型差异。

95. 发明授权

US08570828B2 Memory programming using variable data width 失效
标题翻译：使用可变数据宽度的内存编程
公开(公告)号：US08570828B2
公开(公告)日：2013-10-29
申请号：US13008522
申请日：2011-01-18
申请人： Hong Beom Pyeon
发明人： Hong Beom Pyeon
IPC分类号： G11C8/00
CPC分类号： G11C7/1015 , G11C7/1006 , G11C13/0004 , G11C13/0069 , G11C2013/0085 , G11C2013/0088
摘要： A memory system comprises a memory including a plurality of bits arranged as one or more words. Each bit in each word is capable of being programmed either to a particular logical state or to another logical state. A variable data width controller is in communication with the memory. The variable data width controller comprises an adder to determine a programming number of bits in a word to be programmed into a memory. Each bit to be programmed is in the particular logical state. A partitioning block divides the word in to two or more sub-words when the programming number exceeds a maximum number. A switch is in communication with the partitioning block. The switch sequentially provides one or more write pulses. Each write pulse enables a separate communication path between the memory and one of the word and the sub-words.
摘要翻译：存储器系统包括存储器，该存储器包括排列成一个或多个单词的多个位。每个单词中的每个位都能够被编程到特定的逻辑状态或另一个逻辑状态。可变数据宽度控制器与存储器通信。可变数据宽度控制器包括加法器，用于确定要编程到存储器中的一个字中的位的编程位数。要编程的每个位处于特定的逻辑状态。当编程号码超过最大数量时，划分块将字分成两个或多个子字。开关与分区块通信。开关依次提供一个或多个写入脉冲。每个写入脉冲使得存储器与字和子字中的一个之间的单独通信路径成为可能。

96. 发明授权

US08504789B2 Bridging device having a frequency configurable clock domain 失效
标题翻译：桥接装置具有频率可配置的时钟域
公开(公告)号：US08504789B2
公开(公告)日：2013-08-06
申请号：US12823472
申请日：2010-06-25
申请人： Hong Beom Pyeon , Hunsam Jung , Peter B. Gillingham
发明人： Hong Beom Pyeon , Hunsam Jung , Peter B. Gillingham
IPC分类号： G06F12/00
CPC分类号： G06F1/08 , G06F3/0676 , G06F12/0246 , G06F13/1689 , G11C7/04
摘要： A composite memory device including discrete memory devices and a bridge device for controlling the discrete memory devices. A configurable clock controller receives a system clock and generates a memory clock having a frequency that is a predetermined ratio of the system clock. The system clock frequency is dynamically variable between a maximum and a minimum value, and the ratio of the memory clock frequency relative to the system clock frequency is set by loading a frequency register with a Frequency Divide Ratio (FDR) code any time during operation of the composite memory device. In response to the FDR code, the configurable clock controller changes the memory clock frequency.
摘要翻译：一种复合存储器件，包括分立存储器件和用于控制分立存储器件的桥接器件。可配置的时钟控制器接收系统时钟并产生具有系统时钟的预定比率的频率的存储器时钟。系统时钟频率在最大和最小值之间动态变化，并且存储器时钟频率相对于系统时钟频率的比率通过在运行期间的任何时间加载具有频率分频比（FDR）代码的频率寄存器来设置复合存储器件。响应于FDR代码，可配置的时钟控制器改变存储器时钟频率。

97. 发明授权

US08285960B2 Independent link and bank selection 失效
标题翻译：独立链接和银行选择
公开(公告)号：US08285960B2
公开(公告)日：2012-10-09
申请号：US13077122
申请日：2011-03-31
申请人： Hong Beom Pyeon , Hakjune Oh , Jin-Ki Kim
发明人： Hong Beom Pyeon , Hakjune Oh , Jin-Ki Kim
IPC分类号： G06F12/00
CPC分类号： G06F13/4022 , G11C7/1048 , G11C7/18 , G11C11/408
摘要： Provided is a memory system that has a plurality of memory banks and a plurality of link controllers. For each memory bank, there is first switching logic for receiving output for each link controller, and for passing on the output of only one of the link controllers to the memory bank. For each link controller, there is second switching logic for receiving an output of each memory bank, and for passing on the output of only one of the memory banks to the link controller. According to an embodiment of the invention, there is switch controller logic for controlling operation of both the first switching logic and the second switching logic to prevent simultaneous or overlapping access by multiple link controllers to the same memory bank, and for preventing simultaneous or overlapping access to multiple banks by the same link controller.
摘要翻译：提供了具有多个存储体和多个链接控制器的存储器系统。对于每个存储体，存在用于接收每个链路控制器的输出并且仅将一个链路控制器的输出传递到存储体的第一切换逻辑。对于每个链路控制器，存在用于接收每个存储体的输出并且仅将一个存储体的输出传递到链路控制器的第二切换逻辑。根据本发明的实施例，存在用于控制第一开关逻辑和第二开关逻辑的操作的开关控制器逻辑，以防止多个链路控制器同时或重叠地访问同一存储体，并且用于防止同时或重叠访问通过相同的链路控制器到多个银行。

98. 发明授权

US08271758B2 Apparatus and method for producing IDS for interconnected devices of mixed type 失效
标题翻译：混合型互连设备IDS的设备和方法
公开(公告)号：US08271758B2
公开(公告)日：2012-09-18
申请号：US11622828
申请日：2007-01-12
申请人： Hong Beom Pyeon , HakJune Oh , Jin-Ki Kim
发明人： Hong Beom Pyeon , HakJune Oh , Jin-Ki Kim
IPC分类号： G06F12/00 , G06F3/00
CPC分类号： G06F13/4243 , G06F12/0676
摘要： A plurality of memory devices of mixed type (e.g., DRAMs, SRAMs, MRAMs, and NAND-, NOR-, AND-type Flash memories) are serially interconnected. Each device has device type information on its device type. A specific device type (DT) and a device identifier (ID) contained in a serial input are fed to one device of the serial interconnection configuration. The device determines whether the fed DT matches the DT of the device. In a case of match, a calculator included in the device performs calculation to generate an ID for another device and the fed ID is latched in a register of the device. The generated ID is transferred to another device of the serial interconnection. In a case of no match, the ID generation is skipped and no ID is generated for another device. Such a device type match determination and ID generation or skip are performed in all devices of the serial interconnection.
摘要翻译：多个混合型存储器件（例如，DRAM，SRAM，MRAM和NAND-，NOR-，AND-型闪存）被串联连接。每个设备都有其设备类型的设备类型信息。串行输入中包含的特定设备类型（DT）和设备标识符（ID）被馈送到串行互连配置的一个设备。设备确定馈送的DT是否匹配设备的DT。在匹配的情况下，包含在该设备中的计算器执行计算以生成另一设备的ID，并且将馈送的ID锁存在设备的寄存器中。生成的ID被传送到串行互连的另一个设备。在不匹配的情况下，跳过ID生成，并且不会为其他设备生成ID。在串行互连的所有设备中执行这样的设备类型匹配确定和ID生成或跳过。

99. 发明授权

US08230147B2 Apparatus and method for communicating with semiconductor devices of a serial interconnection 失效
标题翻译：用于与串行互连的半导体器件通信的装置和方法
公开(公告)号：US08230147B2
公开(公告)日：2012-07-24
申请号：US12784238
申请日：2010-05-20
申请人： HakJune Oh , Hong Beom Pyeon , Jin-Ki Kim
发明人： HakJune Oh , Hong Beom Pyeon , Jin-Ki Kim
IPC分类号： G06F13/00 , G06F1/12 , G06F12/00 , G11C7/00
CPC分类号： G11C7/10 , G06F13/1689
摘要： A system controller communicates with devices in a serial interconnection. The system controller sends a read command, a device address identifying a target device in the serial interconnection and a memory location. The target device responds to the read command to read data in the location identified by the memory location. Read data is provided as an output signal that is transmitted from a last device in the serial interconnection to a data receiver of the controller. The data receiver establishes acquisition instants relating to clocks in consideration of a total flow-through latency in the serial interconnection. Where each device has a clock synchronizer, a propagated clock signal through the serial interconnection is used for establishing the acquisition instants. The read data is latched in response to the established acquisition instants in consideration of the flow-through latency, valid data is latched in the data receiver.
摘要翻译：系统控制器与串行互连中的设备通信。系统控制器发送读取命令，标识串行互连中的目标设备的设备地址和存储器位置。目标设备响应读取命令以读取由存储器位置识别的位置中的数据。读取数据被提供为从串行互连中的最后一个设备发送到控制器的数据接收器的输出信号。考虑到串行互连中的总流通延迟，数据接收器建立与时钟有关的采集时刻。在每个设备具有时钟同步器的情况下，通过串行互连的传播时钟信号用于建立采集时刻。考虑到流通延迟，响应于建立的采集时刻来读取数据被锁存，有效数据被锁存在数据接收器中。

100. 发明授权

US08222930B2 Power up circuit with low power sleep mode operation 失效
标题翻译：通过低功耗睡眠模式操作启动电路
公开(公告)号：US08222930B2
公开(公告)日：2012-07-17
申请号：US12552040
申请日：2009-09-01
申请人： Hong Beom Pyeon , Peter Vlasenko
发明人： Hong Beom Pyeon , Peter Vlasenko
IPC分类号： H03L7/00
CPC分类号： G06F1/24 , G06F1/3203 , H02J9/005
摘要： A power up circuit that having reduced power consumption during power saving modes, while maintaining an active flag signal indicating that the power supply voltage is satisfactory. This is achieved by turning off the power up circuit during the power saving mode, and using a status holding circuit to maintain the active flag signal in response to the power down signal. The status holding circuit is responsive to an internal node of the power up circuit for generating the active flag signal when the internal node has reached a predetermined level. The power down signal can be one or both a sleep mode signal and a deep power down signal. The status holding comprises an override circuit for maintaining the active flag signal in the power saving mode, and a restore circuit for rapidly resetting at least the internal node of the power up circuit upon exit of the power saving mode.
摘要翻译：一种在省电模式下降低功耗的上电电路，同时保持表示电源电压令人满意的有效标志信号。这是通过在省电模式期间关闭上电电路并且使用状态保持电路来响应于掉电信号来维持有效标志信号来实现的。状态保持电路响应于上电电路的内部节点，以在内部节点达到预定电平时产生有效标志信号。掉电信号可以是睡眠模式信号和深度掉电信号中的一个或两个。状态保持包括用于将有效标志信号保持在省电模式中的超控电路，以及用于在省电模式退出时至少快速复位上电电路的内部节点的恢复电路。

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