专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

91. 发明申请

US20080067583A1 Nonvolatile semiconductor memory device and manufacturing method thereof 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20080067583A1
公开(公告)日：2008-03-20
申请号：US11898746
申请日：2007-09-14
申请人： Masaru Kidoh , Ryota Katsumata , Hiroyasu Tanaka , Hideaki Aochi , Masaru Kito
发明人： Masaru Kidoh , Ryota Katsumata , Hiroyasu Tanaka , Hideaki Aochi , Masaru Kito
IPC分类号： H01L29/792 , H01L21/4763
CPC分类号： H01L27/105 , G11C16/0483 , H01L21/8221 , H01L27/0688 , H01L27/115 , H01L27/11529 , H01L27/11556 , H01L27/11568 , H01L27/11582 , H01L29/66825 , H01L29/7881
摘要： A nonvolatile semiconductor memory device includes a substrate, and a plurality of memory strings, the memory string including a first selection transistor including a first pillar shaped semiconductor formed perpendicular to the substrate, a first gate insulating film formed around the first pillar shaped semiconductor, and a first gate electrode formed around the first gate insulating film, and a plurality of memory cells including a second pillar shaped semiconductor formed on the first pillar shaped semiconductor, the diameter of the first pillar shaped semiconductor being larger than the diameter of the second pillar shaped semiconductor at the part where the second pillar shaped semiconductor is connected to the first pillar shaped semiconductor, a first insulating film formed around the second pillar shaped semiconductor, a charge storage layer formed around the first insulating film, a second insulating film formed around the charge storage layer, and first to nth electrodes formed around the second insulating film (n is a natural number not less than 2), the first to nth electrodes being plate shaped, the first to nth electrodes being first to nth conductor layers spread in two dimensions, and a second selection transistor including a third pillar shaped semiconductor formed on the second pillar shaped semiconductor, a second gate insulating film formed around the third pillar shaped semiconductor and a second gate electrode formed around the second gate insulating film.
摘要翻译：非易失性半导体存储器件包括衬底和多个存储器串，所述存储器串包括第一选择晶体管，所述第一选择晶体管包括垂直于所述衬底形成的第一柱状半导体，围绕所述第一柱状半导体形成的第一栅极绝缘膜，以及形成在第一栅极绝缘膜周围的第一栅电极和形成在第一柱状半导体上的包括第二柱状半导体的多个存储单元，第一柱状半导体的直径大于第二柱状半导体的直径在第二柱状半导体与第一柱状半导体连接的部分处的半导体，形成在第二柱状半导体周围的第一绝缘膜，形成在第一绝缘膜周围的电荷存储层，形成在电荷周围的第二绝缘膜存储层和第一至第n电极fo 围绕第二绝缘膜（n是不小于2的自然数），第一至第n电极是板状的，第一至第n电极是第一至第n导体层在二维上扩展，第二选择晶体管包括形成在第二柱状半导体上的第三柱状半导体，围绕第三柱状半导体形成的第二栅极绝缘膜和形成在第二栅极绝缘膜周围的第二栅电极。

92. 发明申请

US20080048245A1 Semiconductor device and manufacturing methods thereof 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080048245A1
公开(公告)日：2008-02-28
申请号：US11889863
申请日：2007-08-17
申请人： Masaru Kito , Hideaki Aochi
发明人： Masaru Kito , Hideaki Aochi
IPC分类号： H01L29/04 , H01L21/336 , H01L27/115
CPC分类号： H01L27/115 , G11C16/0416 , G11C16/0483 , H01L21/8221 , H01L27/0688 , H01L27/11568 , H01L27/11578
摘要： A semiconductor device includes: a substrate having a main surface, a first main electrode formed on the main surface of the substrate, a pillar shaped semiconductor layer formed on the first main electrode and having poly crystal, a second main electrode formed on the pillar shaped semiconductor layer, an insulation layer formed on the side of the pillar shaped semiconductor layer, a control electrode formed on the side of the pillar shaped semiconductor layer interposed by said insulation layer and, a tunnel insulation layer which intersects a main current pathway in the pillar shaped semiconductor layer.
摘要翻译：半导体器件包括：具有主表面的基板，形成在基板的主表面上的第一主电极，形成在第一主电极上并具有多晶体的柱状半导体层，形成在柱状的第二主电极半导体层，形成在柱状半导体层一侧的绝缘层，形成在由所述绝缘层插入的柱状半导体层侧的控制电极和与柱状半导体层中的主电流通路相交的隧道绝缘层形半导体层。

93. 发明申请

US20060189070A1 Semiconductor device and method of manufacturing the same 失效
公开(公告)号：US20060189070A1
公开(公告)日：2006-08-24
申请号：US11117337
申请日：2005-04-29
申请人： Masaru Kidoh , Hideaki Aochi , Ryota Katsumata , Masaru Kito , Hitomi Yasutake
发明人： Masaru Kidoh , Hideaki Aochi , Ryota Katsumata , Masaru Kito , Hitomi Yasutake
IPC分类号： H01L21/8242
CPC分类号： H01L27/10841 , H01L27/10867 , H01L27/10882
摘要： A semiconductor device includes a semiconductor substrate, a trench formed in the semiconductor substrate, an island-like element region formed in the semiconductor substrate, having an upper surface, first to third side surfaces, an upper portion, a middle portion and a lower portion, a gate insulating film formed on the first to third side surfaces in the upper portion of the element region, a gate electrode having first and second bottom surfaces, a first diffusion layer formed along the upper surface of the element region, a second diffusion layer formed along the first side surface in the middle portion of the element region, a channel region having first to third regions formed along the first to third side surfaces in the upper portion of the element region, a capacitor formed in the trench, and a bit line electrically connected to the first diffusion layer.

94. 发明授权

US07091546B2 Semiconductor memory with trench capacitor and method of fabricating the same 失效
标题翻译：具有沟槽电容器的半导体存储器及其制造方法
公开(公告)号：US07091546B2
公开(公告)日：2006-08-15
申请号：US11038173
申请日：2005-01-21
申请人： Mitsuru Sato , Hirofumi Inoue , Masaru Kito
发明人： Mitsuru Sato , Hirofumi Inoue , Masaru Kito
IPC分类号： H01L29/772
CPC分类号： H01L27/10867
摘要： A semiconductor device includes semiconductor substrate, a trench capacitor formed in the semiconductor substrate, a cell transistor formed so as to the trench capacitor and having a gate electrode formed on the semiconductor substrate and a source/drain region formed in a surface of the semiconductor substrate, an impurity diffusion region formed in the semiconductor substrate so as to be electrically connected between the trench capacitor and the source/drain region, and a Ge inclusion region formed between the impurity diffusion region and the trench capacitor.
摘要翻译：半导体器件包括半导体衬底，形成在半导体衬底中的沟槽电容器，形成为沟槽电容器的单元晶体管，并且具有形成在半导体衬底上的栅极电极和形成在半导体衬底的表面中的源极/漏极区域形成在半导体衬底中以便电连接在沟槽电容器和源极/漏极区之间的杂质扩散区域和形成在杂质扩散区域和沟槽电容器之间的Ge包含区域。

95. 发明申请

US20060145228A1 Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：US20060145228A1
公开(公告)日：2006-07-06
申请号：US11311268
申请日：2005-12-20
申请人： Masaru Kito , Ryota Katsumata , Hideaki Aochi , Nobutoshi Aoki , Masaki Kondo , Sanae Ito
发明人： Masaru Kito , Ryota Katsumata , Hideaki Aochi , Nobutoshi Aoki , Masaki Kondo , Sanae Ito
IPC分类号： H01L29/94
CPC分类号： H01L29/66651 , H01L27/1087 , H01L27/10873 , H01L27/10894 , H01L29/1037 , H01L29/945
摘要： A semiconductor memory device comprising a semiconductor substrate, element isolating regions formed on the semiconductor substrate, an element forming region provided between the element isolating regions on the semiconductor substrate, the element forming region having a protruding portion, a transistor having a channel formed in the protruding portion of the element forming region, and a capacitor formed in or on the semiconductor substrate to be connected to the transistor, wherein the protruding portion in the element forming region includes first and second inclined and opposed planes arranged along a channel width direction of the transistor, and an upper plane provided between the first and second inclined planes.
摘要翻译：一种半导体存储器件，包括半导体衬底，形成在半导体衬底上的元件隔离区域，设置在半导体衬底上的元件隔离区域之间的元件形成区域，具有突出部分的元件形成区域，所述元件形成区域的突出部分和形成在所述半导体衬底中或与所述晶体管连接的电容器，其中所述元件形成区域中的所述突出部分包括沿着所述晶体管的沟道宽度方向布置的第一和第二倾斜和相对的平面晶体管，以及设置在第一和第二倾斜平面之间的上平面。

96. 发明授权

US06917064B2 Trench capacitor and a method for manufacturing the same 失效
公开(公告)号：US06917064B2
公开(公告)日：2005-07-12
申请号：US10752503
申请日：2004-01-08
申请人： Masaru Kito , Hideaki Aochi
发明人： Masaru Kito , Hideaki Aochi
IPC分类号： H01L27/108 , H01L21/8242 , H01L29/94
CPC分类号： H01L27/10867 , H01L29/945
摘要： A trench capacitor comprises a semiconductor substrate, a trench, formed in the semiconductor substrate, having upper and lower portions, a first doped polysilicon layer filled in the lower portion through a first dielectric film and doped with a first impurity having a first conductivity type, at least a second doped polysilicon layer filled in the upper portion through a second dielectric film and doped with a second impurity different from the first impurity, the second impurity having the first conductivity type, and a buried strap layer provided on the second doped polysilicon layer and composed of the first doped polysilicon layer.

97. 发明申请

US20050110067A1 Semiconductor memory device and method of manufacturing the same 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20050110067A1
公开(公告)日：2005-05-26
申请号：US10901996
申请日：2004-07-30
申请人： Toshiharu Tanaka , Masaru Kito
发明人： Toshiharu Tanaka , Masaru Kito
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L27/10867 , H01L27/10829
摘要： A semiconductor memory device includes a trench formed in the semiconductor substrate, a diffusion layer for a first electrode formed within the semiconductor substrate so as to be in contact with an inner surface of the trench, a capacitor insulating film formed on the diffusion layer, a conductive layer for a second electrode formed so as to bury a lower portion of the trench, a first insulating film formed on the conductive layer and along a side surface of the trench, a first conductive layer formed so as to bury an intermediate portion of the trench, a first contact layer formed so as to bury an upper portion of the trench, and a second contact layer formed on the surface of the semiconductor substrate so as to be in contact with the first contact layer.
摘要翻译：半导体存储器件包括形成在半导体衬底中的沟槽，形成在半导体衬底内的与第一沟槽的内表面接触的第一电极的扩散层，形成在扩散层上的电容器绝缘膜，用于第二电极的导电层，其形成为埋入沟槽的下部，形成在导电层上并沿着沟槽的侧表面的第一绝缘膜，形成为将第二绝缘膜的中间部分沟槽，形成为埋入沟槽的上部的第一接触层和形成在半导体衬底的表面上以与第一接触层接触的第二接触层。

98. 发明授权

US09025377B2 Method of operating semiconductor memory device 有权
标题翻译：操作半导体存储器件的方法
公开(公告)号：US09025377B2
公开(公告)日：2015-05-05
申请号：US13052195
申请日：2011-03-21
申请人： Kunihiro Yamada , Hideaki Aochi , Masaru Kito , Tomoko Fujiwara , Yoshiaki Fukuzumi , Ryouhei Kirisawa , Yoshimasa Mikajiri , Kaori Kawasaki
发明人： Kunihiro Yamada , Hideaki Aochi , Masaru Kito , Tomoko Fujiwara , Yoshiaki Fukuzumi , Ryouhei Kirisawa , Yoshimasa Mikajiri , Kaori Kawasaki
IPC分类号： G11C16/22 , G11C16/04 , H01L27/115
CPC分类号： G11C16/0483 , G11C16/22 , H01L27/11578 , H01L27/11582
摘要： According to one embodiment, a method of operating a semiconductor memory device is disclosed. The method can include storing read-only data in at least one selected from a memory cell of an uppermost layer and a memory cell of a lowermost layer of a plurality of memory cells connected in series via a channel body. The channel body extends upward from a substrate to intersect a plurality of electrode layers stacked on the substrate. The method can include prohibiting a data erase operation of the read-only memory cell having the read-only data stored in the read-only memory cell.
摘要翻译：根据一个实施例，公开了一种操作半导体存储器件的方法。该方法可以包括将至少一个从通过主体连接的多个存储单元的最上层的存储单元和最下层的存储单元中选出的至少一个存储在只读数据中。通道体从衬底向上延伸以与堆叠在衬底上的多个电极层交叉。该方法可以包括禁止具有存储在只读存储器单元中的只读数据的只读存储器单元的数据擦除操作。

99. 发明授权

US08786008B2 Nonvolatile semiconductor memory device and method for manufacturing the same 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US08786008B2
公开(公告)日：2014-07-22
申请号：US13420745
申请日：2012-03-15
申请人： Megumi Ishiduki , Masaru Kidoh , Mitsuru Sato , Masaru Kito , Ryota Katsumata
发明人： Megumi Ishiduki , Masaru Kidoh , Mitsuru Sato , Masaru Kito , Ryota Katsumata
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/7926 , H01L21/28282 , H01L27/11582 , H01L29/42344
摘要： According to one embodiment, a nonvolatile semiconductor memory device includes: a first stacked body; a memory film; a first channel body layer provided inside the memory film; an interlayer insulating film provided on the first stacked body; a second stacked body having a select gate electrode layer, and a second insulating layer; a gate insulating film provided on a side wall of a second hole communicating with the first hole and penetrating the second stacked body and the interlayer insulating film in a stacking direction of the second stacked body; and a second channel body layer provided inside the gate insulating film in the second hole. A first pore diameter of the second hole at an upper end of the select gate electrode layer is smaller than a second pore diameter of the second hole at an lower end of the select gate electrode layer.
摘要翻译：根据一个实施例，一种非易失性半导体存储器件包括：第一层叠体; 记忆膜; 设置在记忆膜内部的第一通道体层; 设置在所述第一层叠体上的层间绝缘膜; 具有选择栅电极层的第二层叠体和第二绝缘层; 栅极绝缘膜，设置在与所述第一孔连通的第二孔的侧壁上，并且在所述第二层叠体的层叠方向上贯通所述第二层叠体和所述层间绝缘膜; 以及设置在第二孔中的栅极绝缘膜内部的第二沟道体层。选择栅电极层的上端的第二孔的第一孔径比选择栅电极层的下端的第二孔的第二孔径小。

100. 发明授权

US08767452B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08767452B2
公开(公告)日：2014-07-01
申请号：US13418651
申请日：2012-03-13
申请人： Masaru Kito , Tomoko Fujiwara , Hideaki Aochi
发明人： Masaru Kito , Tomoko Fujiwara , Hideaki Aochi
IPC分类号： G11C11/14 , G11C11/00
CPC分类号： H01L27/11565 , G11C5/025 , H01L27/11582 , H01L29/7926
摘要： According to one embodiment, a semiconductor memory device includes a stacked body, a semiconductor pillar, a charge storage layer, a tunneling layer, a dividing trench and a first heating unit. The stacked body includes a plurality of first insulating films stacked alternately with a plurality of electrode films. The semiconductor pillar pierces the stacked body. The charge storage layer is provided between the electrode films and the semiconductor pillar. The tunneling layer is provided between the charge storage layer and the semiconductor pillar. The dividing trench is provided between the semiconductor pillars in one direction orthogonal to a stacking direction of the stacked body to divide the electrode films. The first heating unit is provided in an interior of the dividing trench.
摘要翻译：根据一个实施例，半导体存储器件包括堆叠体，半导体柱，电荷存储层，隧道层，分隔沟槽和第一加热单元。层叠体包括与多个电极膜交替堆叠的多个第一绝缘膜。半导体柱穿透层叠体。电荷存储层设置在电极膜和半导体柱之间。隧道层设置在电荷存储层和半导体柱之间。在与层叠体的堆叠方向正交的一个方向上的半导体柱之间设置分割沟槽，以分割电极膜。第一加热单元设置在分隔沟槽的内部。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式