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91. 发明授权

US09337352B1 Floating gate flash memory device and compilation method thereof 有权
标题翻译：浮栅闪存器及其编译方法
公开(公告)号：US09337352B1
公开(公告)日：2016-05-10
申请号：US14753220
申请日：2015-06-29
申请人： Shanghai Huali Microelectronics Corporation
发明人： Jinglun Gu
IPC分类号： H01L29/788 , G11C16/06 , H01L29/78 , H01L29/423 , H01L29/10 , H01L29/08
CPC分类号： H01L29/7885 , G11C16/06 , G11C2216/02 , H01L29/0847 , H01L29/1033 , H01L29/42324 , H01L29/42364 , H01L29/66484 , H01L29/7831 , H01L29/7887
摘要： The present invention discloses a floating gate flash memory device, comprising: a P-type substrate which has a source and a drain, and a first polysilicon gate, a first control gate and a second polysilicon gate and a second control gate which are respectively located in parallel on the upper and lower sides of the substrate, first and second polysilicon floating gates being respectively provided between the first and second control gates and the substrate; the floating gate flash memory device of the present invention utilizes a double-gate structure, can solve the problems such as the poor programming efficiency of the floating gate flash memory and the high programming current power consumption, by using the compilation mechanism of source side injection.
摘要翻译：本发明公开了一种浮栅闪存器件，包括：具有源极和漏极的P型衬底，以及分别位于第一多晶硅栅极，第一控制栅极和第二多晶硅栅极和第二控制栅极的P型衬底平行于基板的上侧和下侧，第一和第二多晶硅浮动栅极分别设置在第一和第二控制栅极与基板之间; 本发明的浮栅闪存器件利用双栅结构，可以通过使用源极侧注入的编译机构来解决浮栅闪存的编程效率差和编程电流功耗高的问题。

92. 发明授权

US09291794B2 Temperature balancing device of projection objective of lithography machine and method thereof 有权
标题翻译：光刻机投影物镜温度平衡装置及其方法
公开(公告)号：US09291794B2
公开(公告)日：2016-03-22
申请号：US13682069
申请日：2012-11-20
申请人： Shanghai Huali Microelectronics Corporation
发明人： Jun Zhu , Lijun Chen
IPC分类号： G02B7/00 , G02B7/02 , G03F7/20
CPC分类号： G02B7/008 , G02B7/028 , G03F7/70891
摘要： The invention provides a temperature balancing device for a projection objective of a lithography machine. The device comprises at least one temperature sensor, at least one heat-absorbing light-transmitting layer and an objective temperature balancing control unit, wherein the temperature sensor is disposed adjacent to the projection objective for sensing the temperature difference of the projection objective in different areas; the heat-absorbing light-transmitting layer is positioned below the projection objective for absorbing radiation energy in the laser beams transmitted from the lithography machine and transmitting the laser beams; and the objective temperature balancing control unit is used for controlling the absorption degree and light transmission degree of the heat-absorbing light-transmitting layer according to the temperature difference sensed by the temperature sensor. The invention also discloses a method for balancing temperature of a projection objective of a lithography machine.
摘要翻译：本发明提供了一种用于光刻机的投影物镜的温度平衡装置。该装置包括至少一个温度传感器，至少一个吸热透光层和物镜温度平衡控制单元，其中温度传感器邻近投影物镜放置，用于感测不同区域中投影物镜的温差 ; 吸收透光层位于投影物体下方，用于吸收从光刻机传输的激光束中的辐射能量并传输激光束; 并且目标温度平衡控制单元用于根据由温度传感器感测的温度差来控制吸热透光层的吸收度和透光度。本发明还公开了一种用于平衡光刻机的投影物镜的温度的方法。

93. 发明授权

US09150963B2 Method for depositing phosphosilicate glass 有权
标题翻译：磷硅玻璃的沉积方法
公开(公告)号：US09150963B2
公开(公告)日：2015-10-06
申请号：US13728743
申请日：2012-12-27
申请人： SHANGHAI HUALI MICROELECTRONICS CORPORATION
发明人： Meimei Gu , Duoyuan Hou , Huijun Zhang , ChienWei Chen
IPC分类号： C23C14/10 , C23C14/34 , C23C16/40 , C23C16/04
CPC分类号： C23C16/401 , C23C16/045
摘要： A method of depositing phosphosilicate glass (PSG) is disclosed. The method includes a first deposition step for depositing a first PSG layer with a sputtering deposition ratio of 0.10 to 0.16, and a second deposition step for depositing a second PSG layer with a sputtering deposition ratio of 0.18 to 0.22 after the first deposition step. The first PSG layer has a thickness smaller than that of the second PSG layer. With such two-step deposition method, flower pattern having a dramatically reduced size can be formed without occurrence of clipping or formation of sidewall voids in the resultant gate patterns. Specifically, the formed flower pattern has a height reduced by about 50% and a thickness reduced by about 30%.
摘要翻译：公开了一种沉积磷硅玻璃（PSG）的方法。该方法包括用于沉积溅射沉积比为0.10至0.16的第一PSG层的第一沉积步骤和用于在第一沉积步骤之后沉积溅射沉积比为0.18至0.22的第二PSG层的第二沉积步骤。第一PSG层的厚度小于第二PSG层的厚度。通过这种两步沉积方法，可以形成具有显着减小的尺寸的花纹，而不会在所得到的栅极图案中产生夹持或形成侧壁空隙。具体地说，形成的花纹图案的高度减小了大约50％，厚度减少了大约30％。

94. 发明申请

US20150064930A1 PROCESS OF MANUFACTURING THE GATE OXIDE LAYER 审中-公开
标题翻译：制造氧化铝层的工艺
公开(公告)号：US20150064930A1
公开(公告)日：2015-03-05
申请号：US14082310
申请日：2013-11-18
申请人： Shanghai Huali Microelectronics Corporation
发明人： ZHONGPING LI , ZHI WANG , JINMING SU , HSUSHENG CHANG
IPC分类号： H01L21/02 , H01L21/28
CPC分类号： H01L21/28167 , H01L21/022 , H01L21/02238 , H01L21/02255 , H01L21/28202 , H01L21/28211
摘要： A process of manufacturing the gate oxide layer, which uses the wet oxidation by deuterium to form gate oxide layer, wherein the nitriding treatment is applied to formed gate oxide layer by high temperature annealing process, the stable Si-D bonds is formed on surface of the gate oxide layer to reduce silicon dangling bonds, which reduce the defect of the gate oxide interface and lower the interface defect density of the gate oxide layer and the charge density effectively to avoid NBTI, is provided.
摘要翻译：制造栅极氧化层的方法，其通过氘的湿式氧化形成栅极氧化层，其中通过高温退火工艺将氮化处理施加到形成的栅极氧化物层上，稳定的Si-D键形成在提供了减少硅悬空键的栅极氧化层，其减少了栅极氧化物界面的缺陷，并且有效降低了栅极氧化物层的界面缺陷密度和电荷密度以避免NBTI。

95. 发明授权

US08822348B2 Dummy wafer structure and method of forming the same 有权
标题翻译：晶片晶圆结构及其形成方法
公开(公告)号：US08822348B2
公开(公告)日：2014-09-02
申请号：US13730576
申请日：2012-12-28
申请人： Shanghai Huali Microelectronics Corporation
发明人： Chuan Ren , Zhi Wang , HsuSheng Chang
IPC分类号： H01L21/31 , H01L21/3205 , H01L21/02 , H01L29/06
CPC分类号： H01L29/0603 , C23C16/345 , C23C16/402 , H01L21/02164 , H01L21/0217 , H01L21/022 , H01L21/02271 , H01L21/3205 , H01L21/32055
摘要： A dummy wafer structure and a method of forming the same are disclosed. The dummy wafer structure includes: a silicon substrate; a silicon nitride layer over the silicon substrate; and a silicon dioxide layer over the silicon nitride layer. The method includes: a first step of forming a silicon nitride layer over a silicon substrate so as to form a silicon-silicon nitride structure; and a second step of forming a silicon dioxide layer over the silicon-silicon nitride structure obtained in the first step so as to form a silicon-silicon nitride-silicon dioxide structure. Dummy wafers with this special structure are able to avoid deposition rate inconsistency in a polysilicon deposition process and are capable of avoiding conventional dummy wafers' adverse effect on deposit layer thicknesses of process wafers and hence providing the process wafers with deposit layers having a high inter-wafer uniformity.
摘要翻译：公开了一种虚设晶片结构及其形成方法。虚设晶片结构包括：硅衬底; 硅衬底上的氮化硅层; 以及氮化硅层上的二氧化硅层。该方法包括：在硅衬底上形成氮化硅层以形成硅 - 氮化硅结构的第一步骤; 以及在第一步骤中获得的硅 - 氮化硅结构上形成二氧化硅层以形成硅 - 氮化硅 - 二氧化硅结构的第二步骤。具有这种特殊结构的虚拟晶片能够避免多晶硅沉积工艺中的沉积速率不一致，并且能够避免常规的虚设晶片对工艺晶片的沉积层厚度的不利影响，并且因此为工艺晶片提供具有高间隔的沉积层，晶圆均匀性。

96. 发明授权

US08822294B2 Method for improving write margins of SRAM cells 有权
标题翻译：提高SRAM单元写入裕度的方法
公开(公告)号：US08822294B2
公开(公告)日：2014-09-02
申请号：US13721071
申请日：2012-12-20
申请人： Shanghai Huali Microelectronics Corporation
发明人： Liujiang Yu
IPC分类号： H01L21/00 , H01L27/11 , H01L21/28 , H01L27/02
CPC分类号： H01L21/28 , H01L27/0207 , H01L27/1104
摘要： The present invention provides a method for improving the write margins of the SRAM cells. The method comprises: before etching a polysilicon layer to form the polysilicon gates, performing a pre-implantation process to the polysilicon layer; wherein the polysilicon layer defines SRAM NMOSFETs regions and SRAM PMOSFETs regions; wherein the pre-implantation process comprises pre-implanting the fifth-group elements to the SRAM NMOSFETs regions and the NMOSFETs regions except to the SRAM NMOSFETs regions in the polysilicon layer, and pre-implanting the third-group elements to the PMOSFETs regions excluding the SRAM PMOSFETs regions in the polysilicon layer; wherein the process of pre-implanting the third-group elements comprises forming a pre-implantation photo mask capable of covering the SRAM PMOSFETs regions and using the pre-implantation photo mask to pre-implanting the third-group elements.
摘要翻译：本发明提供了一种用于提高SRAM单元的写入裕度的方法。该方法包括：在蚀刻多晶硅层以形成多晶硅栅极之前，对多晶硅层进行预注入工艺; 其中所述多晶硅层限定SRAM NMOSFET区域和SRAM PMOSFET区域; 其中所述预注入工艺包括将所述第五组元件预先植入所述SRAM NMOSFET区域和除了所述多晶硅层中的所述SRAM NMOSFET区域之外的所述NMOSFET区域，以及将所述第三组元件预先植入所述PMOSFET区域，多晶硅层中的SRAM PMOSFET区域; 其中预植入第三组元件的过程包括形成能够覆盖SRAM PMOSFET区域并使用预植入光掩模预注入第三组元件的预注入光掩模。

97. 发明申请

US20140145284A1 PHOTODIODE FOR AN IMAGE SENSOR AND METHOD OF FABRICATING THE SAME 审中-公开
标题翻译：用于图像传感器的光致抗体及其制造方法
公开(公告)号：US20140145284A1
公开(公告)日：2014-05-29
申请号：US14055394
申请日：2013-10-16
申请人： Shanghai Huali Microelectronics Corporation
发明人： Chunsheng ZHENG , Wenguang ZHANG , Yuwen CHEN
IPC分类号： H01L31/0236 , H01L31/18
CPC分类号： H01L31/02363 , H01L27/14621 , H01L27/14627 , H01L27/14685 , H01L31/103 , Y02E10/50
摘要： A photodiode for an image sensor and a method of fabricating the photodiode are disclosed. The photodiode includes a substrate having a surface defined as a light-incident surface of the photodiode, wherein a plurality of convex structures are provided on the light-incident surface of the photodiode, namely, a non-planar light-incident surface which is capable of reducing the light reflection and hence improving the ability of the photodiode to capture incident light, thereby enabling an image sensor that incorporates the photodiode to have a higher fill factor and a better performance.
摘要翻译：公开了一种用于图像传感器的光电二极管及其制造方法。光电二极管包括具有被定义为光电二极管的光入射表面的表面的基板，其中在光电二极管的光入射表面上设置多个凸起结构，即具有能量的非平面光入射表面减少光反射，从而提高光电二极管捕获入射光的能力，从而使包含光电二极管的图像传感器具有更高的填充因子和更好的性能。

98. 发明授权

US08722287B2 Phase shift focus monitor reticle, manufacturing method thereof and method for monitoring focus difference 有权
标题翻译：相移焦点监视器掩模版及其制造方法以及监控焦点差异的方法
公开(公告)号：US08722287B2
公开(公告)日：2014-05-13
申请号：US13688407
申请日：2012-11-29
申请人： Shanghai Huali Microelectronics Corporation
发明人： Wenliang Li , Peng Wu
IPC分类号： G03F1/26 , G03F1/44
CPC分类号： G03F1/26 , G03F1/44
摘要： The invention provides a phase shift focus monitor reticle, a manufacturing method thereof, and a method of monitoring focus difference using the phase shift focus monitor reticle. The phase shift focus monitor reticle comprises a shield comprising a plurality of light-transmitting portions with a certain width; and a glass layer positioned on the shield layer comprising a plurality of openings at the light-transmitting portions; wherein the width of the openings is half of the width of the light-transmitting portions; the depth of the openings is n*λ/(N−1), wherein λ is the wavelength of the lights incident on the phase shift focus monitor reticle in air, N is the refractive index of the glass layer, n is a positive integer. The invention can be applied to thicker photoresist and different process machines.
摘要翻译：本发明提供一种相移焦点监视器掩模版及其制造方法，以及使用相移焦点监视器掩模版监视对焦差异的方法。相移焦点监视器掩模版包括具有一定宽度的多个透光部分的屏蔽件; 以及位于所述屏蔽层上的玻璃层，包括在所述透光部分处的多个开口; 其中所述开口的宽度是所述透光部分的宽度的一半; 开口的深度为n *λ/（N-1），其中λ是入射到空气中的相移焦点监视器掩模版上的光的波长，N是玻璃层的折射率，n是正整数。本发明可应用于较厚的光致抗蚀剂和不同的加工机器。

99. 发明申请

US20140127835A1 METHOD OF DETECTING THE CIRCULAR UNIFORMITY OF THE SEMICONDUCTOR CIRCULAR CONTACT HOLES 有权
标题翻译：检测半导体圆形接触孔的圆形均匀性的方法
公开(公告)号：US20140127835A1
公开(公告)日：2014-05-08
申请号：US14053750
申请日：2013-10-15
申请人： Shanghai Huali Microelectronics Corporation
发明人： Kai WANG , HungLin CHEN , Yin LONG , Qiliang NI , MingShen KUO
IPC分类号： H01L21/66
CPC分类号： H01L22/12 , H01L2924/0002 , Y10S257/911 , Y10S257/912 , H01L2924/00
摘要： A method of detecting the circular uniformity of semiconductor circular contact holes. Several detection circuit structures are disposed on the semiconductor wafer: N-type active regions and P-type active regions; silicon dioxide layers separate the N-type active regions from the P-type active regions; the N-type active regions are formed in the P well and the P-type active regions are formed in the N well; polysilicon gates bridge the N-type active regions and the P-type active regions; gate oxide layers insulate the P-type regions and the N-type regions from the polysilicon gates, so that the P-type regions and the N-type regions are independent; the N-type active regions connect with circular contact holes while the P-type active regions and the polysilicon gates connect with oval contact holes; a electron beam scanner detects the circular uniformity of the contact holes. This invention advantageously reflects effectively and comprehensively the circular uniformity of the contact holes.
摘要翻译：一种检测半导体圆形接触孔的圆形均匀性的方法。多个检测电路结构设置在半导体晶片上：N型有源区和P型有源区; 二氧化硅层将N型有源区与P型有源区分开; 在P阱中形成N型有源区，在N阱中形成P型有源区; 多晶硅门桥接N型有源区和P型有源区; 栅极氧化层使P型区域和N型区域与多晶硅栅极绝缘，使得P型区域和N型区域是独立的; N型有源区域与圆形接触孔连接，而P型有源区域和多晶硅栅极与椭圆形接触孔连接; 电子束扫描器检测接触孔的圆形均匀性。本发明有利地有效地反映了接触孔的圆形均匀性。

100. 发明授权

US08658531B2 Method of forming connection holes 有权
标题翻译：形成连接孔的方法
公开(公告)号：US08658531B2
公开(公告)日：2014-02-25
申请号：US13721070
申请日：2012-12-20
申请人： Shanghai Huali Microelectronics Corporation
发明人： Yushu Yang , Cheng Li , Yuwen Chen
IPC分类号： H01L21/4763
CPC分类号： H01L21/30604 , H01L21/31116 , H01L21/76816
摘要： The present invention provides a method of forming connection holes. The method utilizes two different gases to perform two etching processes for the interlayer dielectric layer so as to form connection holes. The etching rate of the interlayer dielectric layer in the first etching process using the first etching gas is proportional to the size of the openings which defines the connection hole while the etching rate of the interlayer dielectric layer in the second etching process using the second etching gas is inversely related with size of the openings. According to the present invention, the first etching gas and the second etching gas compensate for each other to eliminate the loading effect, thus the connection holes are formed with almost the same depth. Therefore the damage of the etching stopper layer due to the high etching rate in the larger connection holes can be avoided, which prevents the excessive variation of the connecting resistance and expands the process window.
摘要翻译：本发明提供一种形成连接孔的方法。该方法利用两种不同的气体对层间电介质层进行两次蚀刻处理，形成连接孔。使用第一蚀刻气体的第一蚀刻工艺中的层间电介质层的蚀刻速率与限定连接孔的开口的尺寸成比例，而在使用第二蚀刻气体的第二蚀刻工艺中的层间电介质层的蚀刻速率与开口的尺寸成反比。根据本发明，第一蚀刻气体和第二蚀刻气体彼此补偿以消除负载效应，因此连接孔形成有几乎相同的深度。因此，可以避免由于较大的连接孔中的高蚀刻速率导致的蚀刻阻挡层的损伤，这防止了连接电阻的过度变化并扩大了工艺窗口。

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