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91. 发明申请

US20140159116A1 III-Nitride Device Having an Enhanced Field Plate 审中-公开
标题翻译：具有增强型场板的III型氮化物器件
公开(公告)号：US20140159116A1
公开(公告)日：2014-06-12
申请号：US14085037
申请日：2013-11-20
申请人： International Rectifier Corporation
发明人： Michael A. Briere , Jin Wook Chung
IPC分类号： H01L29/778
CPC分类号： H01L29/7786 , H01L29/2003 , H01L29/402
摘要： In an exemplary implementation, a semiconductor device includes a III-nitride heterojunction including a III-nitride barrier layer situated over a III-nitride channel layer to form a conduction channel including a two-dimensional electron gas. The semiconductor device further includes a gate electrode coupled to a field plate. The field plate includes a plurality of steps insulated from the conduction channel by a dielectric body and the III-nitride barrier layer. The dielectric body under each one of the plurality of steps contributes to a breakdown voltage that is at least twice a breakdown voltage of the semiconductor device at each corresponding step. The breakdown voltage can correspond to a breakdown voltage of the dielectric body and the III-nitride barrier layer.
摘要翻译：在示例性实施方案中，半导体器件包括III族氮化物异质结，其包括位于III族氮化物沟道层上方的III族氮化物势垒层，以形成包括二维电子气的导电通道。半导体器件还包括耦合到场板的栅电极。场板包括通过电介质体和III族氮化物阻挡层与导电沟道绝缘的多个台阶。在多个步骤中的每一个步骤下的电介质体有助于在每个相应步骤处的半导体器件的击穿电压的至少两倍的击穿电压。击穿电压可以对应于电介质体和III族氮化物阻挡层的击穿电压。

92. 发明申请

US20140084431A1 Semiconductor Package with Heat Spreader 有权
标题翻译：带散热器的半导体封装
公开(公告)号：US20140084431A1
公开(公告)日：2014-03-27
申请号：US14057385
申请日：2013-10-18
申请人： International Rectifier Corporation
发明人： Michael A. Briere , Chuan Cheah , Kunzhong Hu
IPC分类号： H01L23/495 , H01L23/367
CPC分类号： H01L23/495 , H01L23/3107 , H01L23/367 , H01L23/4334 , H01L23/49568 , H01L2224/16245 , H01L2224/32245 , H01L2224/73253
摘要： A semiconductor package that includes a semiconductor die and a heat spreader thermally coupled to the semiconductor and disposed at least partially within the molded housing of the package.
摘要翻译：一种半导体封装，其包括半导体管芯和散热器，所述散热器热耦合到所述半导体并且至少部分地设置在所述封装的模制外壳内。

93. 发明申请

US20140070278A1 Active Area Shaping of III-Nitride Devices Utilizing Multiple Dielectric Materials 有权
标题翻译：使用多种电介质材料的三氮化硅器件的主动区域整形
公开(公告)号：US20140070278A1
公开(公告)日：2014-03-13
申请号：US14081798
申请日：2013-11-15
申请人： International Rectifier Corporation
发明人： Michael A. Briere
IPC分类号： H01L29/778
CPC分类号： H01L29/778 , H01L21/28264 , H01L23/3192 , H01L29/2003 , H01L29/42376 , H01L29/518 , H01L29/66462 , H01L29/7786 , H01L2924/0002 , H01L2924/00
摘要： In an exemplary implementation, a III-nitride semiconductor device includes a III-nitride heterojunction including a first III-nitride body situated over a second III-nitride body to form a two-dimensional electron gas. The III-nitride semiconductor device further includes a dielectric body situated over the III-nitride heterojunction and including a first dielectric layer of a first dielectric material and a second dielectric layer of a second dielectric material different than the first dielectric material. A gate well of a first width is defined by the first dielectric layer, and is of a second width defined by the second dielectric layer, where the second width is greater than the first width. The III-nitride semiconductor device further includes a gate arrangement situated in the gate well and including a gate electrode integrated with a field plate.
摘要翻译：在示例性实施方案中，III族氮化物半导体器件包括III族氮化物异质结，其包括位于第二III族氮化物体上方的第一III族氮化物体，以形成二维电子气。 III族氮化物半导体器件还包括位于III族氮化物异质结上方的电介质体，并且包括第一电介质材料的第一电介质层和与第一电介质材料不同的第二电介质材料的第二电介质层。第一宽度的栅极阱由第一介电层限定，并且具有由第二介电层限定的第二宽度，其中第二宽度大于第一宽度。 III族氮化物半导体器件还包括位于栅极阱中并包括与场板集成的栅电极的栅极布置。

94. 发明申请

US20140008663A1 Integrated Composite Group III-V and Group IV Semiconductor Device 审中-公开
标题翻译：集成复合组III-V和IV类半导体器件
公开(公告)号：US20140008663A1
公开(公告)日：2014-01-09
申请号：US14019738
申请日：2013-09-06
申请人： International Rectifier Corporation
发明人： Michael A. Briere
IPC分类号： H01L29/205
摘要： According to one disclosed embodiment, a method for fabricating a monolithic integrated composite device comprises forming a group III-V semiconductor body over a group IV semiconductor substrate, forming a trench in the group III-V semiconductor body, and forming a group IV semiconductor body in the trench. The method also comprises fabricating at least one group IV semiconductor device in the group IV semiconductor body, and fabricating at least one group III-V semiconductor device in the group III-V semiconductor body. In one embodiment, the method further comprises planarizing an upper surface of the III-V semiconductor body and an upper surface of the group IV semiconductor body to render those respective upper surfaces substantially co-planar. In one embodiment, the method further comprises fabricating at least one passive device in a defective region of said group IV semiconductor body adjacent to a sidewall of the trench.
摘要翻译：根据一个公开的实施例，一种用于制造单片集成复合器件的方法包括在IV族半导体衬底上形成III-V族半导体体，在III-V族半导体体中形成沟槽，并形成IV族半导体体在沟里。该方法还包括在IV族半导体本体中制造至少一种IV族半导体器件，并且在III-V族半导体器件中制造至少一种III-V族III族半导体器件。在一个实施例中，该方法还包括使III-V半导体体的上表面和IV族半导体本体的上表面平坦化，以使这些相应的上表面基本上共面。在一个实施例中，该方法还包括在与沟槽的侧壁相邻的所述IV族半导体主体的缺陷区域中制造至少一个无源器件。

95. 发明申请

US20130337626A1 Monolithic Group III-V and Group IV Device 审中-公开
标题翻译：单体III-V族和IV族装置
公开(公告)号：US20130337626A1
公开(公告)日：2013-12-19
申请号：US13969392
申请日：2013-08-16
申请人： International Rectifier Corporation
发明人： Michael A. Briere
IPC分类号： H01L21/761
摘要： According to one disclosed embodiment, a method for fabricating a monolithic integrated composite device comprises forming a group III-V semiconductor body over a group IV semiconductor substrate, forming a trench in the group III-V semiconductor body, and forming a group IV semiconductor body in the trench. The method also comprises fabricating at least one group IV semiconductor device in. the group IV semiconductor body, and fabricating at least one group III-V semiconductor device in the group III-V semiconductor body. In one embodiment, the method further comprises planarizing an upper surface of the III-V semiconductor body and an upper surface of the group IV semiconductor body to render those respective upper surfaces substantially co-planar. In one embodiment, the method further comprises fabricating at least one passive device in a defective region of said group IV semiconductor body adjacent to a side-wall of the trench.
摘要翻译：根据一个公开的实施例，一种用于制造单片集成复合器件的方法包括在IV族半导体衬底上形成III-V族半导体体，在III-V族半导体体中形成沟槽，并形成IV族半导体体在沟里。该方法还包括在IV族半导体体中制造至少一种IV族半导体器件，并且在III-V族半导体体中制造至少一种III-V族III族半导体器件。在一个实施例中，该方法还包括使III-V半导体体的上表面和IV族半导体本体的上表面平坦化，以使这些相应的上表面基本上共面。在一个实施例中，该方法还包括在邻近沟槽的侧壁的所述IV族半导体主体的缺陷区域中制造至少一个无源器件。

96. 发明授权

US08536624B2 Active area shaping for III-nitride devices 有权
标题翻译： III族氮化物器件的有源区域整形
公开(公告)号：US08536624B2
公开(公告)日：2013-09-17
申请号：US13721573
申请日：2012-12-20
申请人： International Rectifier Corporation
发明人： Michael A. Briere , Paul Bridger , Jianjun Cao
IPC分类号： H01L29/66
CPC分类号： H01L29/778 , H01L21/28264 , H01L23/291 , H01L23/3171 , H01L29/2003 , H01L29/42376 , H01L29/51 , H01L29/66431 , H01L29/66462 , H01L29/66477 , H01L29/7787 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： A III-nitride heterojunction power semiconductor device that includes a passivation body with a gate well having a top mouth that is wider than the bottom mouth thereof, and a method of fabrication for the same.
摘要翻译：一种III族氮化物异质结功率半导体器件及其制造方法，其包括具有栅极阱的钝化体，其具有比其底部口宽的顶部口。

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