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    • 91. 发明授权
    • Image compression and expansion device
    • 图像压缩和扩展设备
    • US07787690B2
    • 2010-08-31
    • US10976766
    • 2004-11-01
    • Gen SasakiTakashi MatsutaniYusuke Nara
    • Gen SasakiTakashi MatsutaniYusuke Nara
    • G06K9/36
    • H04N19/40
    • RGB image data outputted from an ADC (3) is processed in an SPU (42) and an RPU (43) and then buffered into a memory (48) as YUV image data. The YUV image data is outputted from a YUV output unit (45), encoded by an image compression and expansion chip (5A) and transmitted to a main chip (4) by a DMAC (52). On the other hand, compressed moving image data stored in the memory (48) is transmitted to the image compression and expansion chip (5A) through the control by a DMAC (44), decoded therein, then converted into RGB image data in an RGB sampling unit (54) and inputted to the main chip (4) by the SPU (42) through a data line (14). With such a construction, it is possible to provide a circuit for compression and expansion, which allows connection with a main processing chip having no YUV input circuit without increasing circuit scale, maintaining general versatility of those circuits.
    • 在SPU(42)和RPU(43)中处理从ADC(3)输出的RGB图像数据,然后作为YUV图像数据缓冲到存储器(48)中。 YUV图像数据从由图像压缩和扩展芯片(5A)编码的YUV输出单元(45)输出,并通过DMAC(52)发送到主芯片(4)。 另一方面,存储在存储器(48)中的压缩运动图像数据通过其中解码的DMAC(44)的控制被传送到图像压缩和扩展芯片(5A),然后转换成RGB图像数据 采样单元(54),并通过数据线(14)由SPU(42)输入到主芯片(4)。 通过这样的结构,可以提供用于压缩和扩展的电路,其允许与不具有YUV输入电路的主处理芯片连接而不增加电路规模,从而保持这些电路的通用性。
    • 92. 发明申请
    • MEMORY SYSTEM AND COMPUTER SYSTEM
    • 存储系统和计算机系统
    • US20100162040A1
    • 2010-06-24
    • US12646349
    • 2009-12-23
    • Shinji TANAKA
    • Shinji TANAKA
    • G06F11/00G06F12/00
    • G06F12/0246G06F2212/7201G06F2212/7202
    • A memory system according to the present invention includes, in addition to an computing device, a plurality of first blocks that are provided to store information including user information, and first physical addresses not overlapping one another are assigned to, respectively, and a plurality of second blocks that are provided to store first physical addresses of initial defect blocks out of the plurality of first blocks, respectively, wherein the computing device finds the first physical address corresponding a inputted given logical address, based on a given mirror logical address corresponding to the given logical address, and information stored in the second blocks.
    • 根据本发明的存储器系统除了计算设备之外还包括多个第一块,被提供用于存储包括用户信息的信息以及彼此不重叠的第一物理地址分别被分配给多个 第二块,分别用于存储多个第一块中的初始缺陷块的第一物理地址,其中,所述计算设备基于与所述第一块对应的给定镜像逻辑地址,找到与输入的给定逻辑地址对应的第一物理地址 给定的逻辑地址和存储在第二个块中的信息。
    • 93. 发明授权
    • Semiconductor memory and data access method
    • 半导体存储器和数据存取方法
    • US07739467B2
    • 2010-06-15
    • US11668735
    • 2007-01-30
    • Takashi Oshikiri
    • Takashi Oshikiri
    • G06F12/00
    • G11C7/24
    • While a semiconductor memory operates in a first operation mode with high security, an encrypted command is inputted and then decoded to acquire the first address information. After the semiconductor memory comes into a second operation mode where the level of security is lower than that of the first operation mode, a command is inputted. Then, the second address information is acquired from the command. A control circuit in the semiconductor memory generates an address of 10 bits by using the first address information as a high-order 4 bits and the second address information as a low-order 6 bits and outputs the address to a memory array. With this operation, it becomes possible to read/write data from/to the memory array.
    • 虽然半导体存储器以高安全性的第一操作模式操作,但是输入加密命令,然后被解码以获取第一地址信息。 在半导体存储器进入安全级别低于第一操作模式的第二操作模式之后,输入命令。 然后,从命令获取第二地址信息。 半导体存储器中的控制电路通过使用第一地址信息作为高位4位并且将第二地址信息作为低位6位产生10位的地址,并将该地址输出到存储器阵列。 通过该操作,可以从/向存储器阵列读取/写入数据。
    • 94. 发明授权
    • Transcoder controlling generated codes of an output stream to a target bit rate
    • 转码器将输出流的生成代码控制为目标比特率
    • US07714751B2
    • 2010-05-11
    • US12144098
    • 2008-06-23
    • Hiromu HasegawaMiyuki Yanagida
    • Hiromu HasegawaMiyuki Yanagida
    • H03M7/00
    • H04N19/40H04N19/124H04N19/149H04N19/61
    • A transcoder calculates a reference conversion factor on the basis of a ratio between a total target bit rate of a whole second stream and an total input bit rate of a whole first stream and calculates a coefficient of variation from the total target bit rate of the whole second stream and an average output bit rate of a converted second stream in the N period. Next, a quantization step conversion factor in the next (N+1) period is calculated by adding the coefficient of variation to the reference conversion factor. Then, a quantization step value of a second stream in the (N+1) period is calculated by multiplying a quantization step value of a first stream in the (N+1) period by the quantization step conversion factor.
    • 代码转换器基于整个第二流的总目标比特率与整个第一流的总输入比特率之间的比率来计算参考转换因子,并且从整体的总目标比特率计算变异系数 第二流和在N个周期中转换的第二流的平均输出比特率。 接下来,通过将变化系数与参考转换因子相加来计算下一个(N + 1)周期中的量化步长转换因子。 然后,通过将第(N + 1)个周期中的第一流的量化步长值乘以量化步长转换因子来计算第(N + 1)周期中的第二流的量化步长值。
    • 96. 发明申请
    • IMAGE PROCESSOR
    • 图像处理器
    • US20090238477A1
    • 2009-09-24
    • US12402817
    • 2009-03-12
    • Atsushi UCHIYAMAYujiro TANIHiromu HASEGAWA
    • Atsushi UCHIYAMAYujiro TANIHiromu HASEGAWA
    • G06K9/36
    • H04N19/85H04N19/117H04N19/186
    • An image processor includes an encoder and a decoder. The encoder includes a frequency transform unit, a pre-filter, and a color conversion unit that converts a pixel signal of a first color space inputted from outside into a pixel signal of a second color space including a luminance signal and chrominance signals. The decoder includes a frequency inverse transform unit, a post-filter, and a color inverse conversion unit that inversely converts a pixel signal of the second color space into a pixel signal of the first color space. The pre-filter performs prefiltering on one or plural specific signals among the luminance and chrominance signals. The post-filter does not perform postfiltering on the above specific signals.
    • 图像处理器包括编码器和解码器。 编码器包括频率变换单元,预滤波器和颜色转换单元,其将从外部输入的第一颜色空间的像素信号转换为包括亮度信号和色度信号的第二颜色空间的像素信号。 解码器包括频率逆变换单元,后置滤波器和颜色逆变换单元,其将第二颜色空间的像素信号反向转换为第一颜色空间的像素信号。 预滤波器对亮度和色度信号中的一个或多个特定信号执行预滤波。 后置滤波器不对上述特定信号执行后置滤波。
    • 97. 发明申请
    • NOISE REDUCTION DEVICE AND DIGITAL CAMERA
    • 噪声减少装置和数字摄像机
    • US20090237532A1
    • 2009-09-24
    • US12394469
    • 2009-02-27
    • Munehiro MORI
    • Munehiro MORI
    • H04N9/64
    • H04N9/045G06T5/005G06T2207/10024H04N5/357H04N5/3675
    • The first array register stores neighboring pixels of the same color as the pixel of interest, which are sorted according to the size of the pixel value. The maximum signal comparison circuit compares the value obtained by adding the threshold ThB to the pixel value maxC, which is the (b1)th largest pixel value of the pixels in the first array register and the pixel value P22 of the pixel of interest. When the comparison shows that the pixel value of the pixel of interest P22 is larger, the pixel of interest P22 is determined to be noise, and the pixel value of the pixel of interest is replaced by maxC. The limit signal comparison circuit compares the pixel value P22 of the pixel of interest and the signal upper limit LB. When the comparison shows that P22 is larger than LB and is equal to or larger than maxC, only the pixel of interest is determined to be totally overexposed, and the pixel value of the pixel of interest is replaced by maxC.
    • 第一阵列寄存器存储与感兴趣像素相同颜色的相邻像素,其根据像素值的大小进行分类。 最大信号比较电路将通过将阈值ThB相加得到的值与作为第一阵列寄存器中的像素的第(b1)个最大像素值和感兴趣像素的像素值P22的像素值maxC进行比较。 当比较表明感兴趣像素P22的像素值较大时,感兴趣像素P22被确定为噪声,并且感兴趣像素的像素值被替换为maxC。 限制信号比较电路将感兴趣像素的像素值P22与信号上限LB进行比较。 当比较表明P22大于LB并且等于或大于maxC时,仅确定感兴趣的像素完全曝光,并且将关注像素的像素值替换为maxC。
    • 98. 发明申请
    • IMAGE PROCESSING APPARATUS AND DIGITAL CAMERA
    • 图像处理设备和数码相机
    • US20090225194A1
    • 2009-09-10
    • US12394767
    • 2009-02-27
    • Munehiro MORI
    • Munehiro MORI
    • H04N9/68
    • H04N9/77H04N9/646
    • Contour extraction circuits extract contour components YE, CbE, and CrE, respectively, from luminance signal Y, and color-difference signals Cb and Cr, respectively. The two contour components CbE and CrE of the color difference signals are inputted to the LUTs respectively, via the selectors respectively, and converted into the adjustment signals K1 and K2, respectively. The multiplier multiplies the contour component YE by the adjustment signal K1 so as to generate the modulated contour component E1. The multiplier multiplies the modulated contour component E1 by the adjustment signal K2 so as to generate the modulated contour component E2. The adder adds the modulated contour component E2 to the luminance signal Y so as to generate the luminance signal Ya, which has been contour-enhanced based on the contour component of the luminance signal and the contour components of the color-difference signals.
    • 轮廓提取电路分别从亮度信号Y和色差信号Cb和Cr分别提取轮廓分量YE,CbE和CrE。 色差信号的两个轮廓分量CbE和CrE分别经由选择器输入到LUT,并分别转换成调整信号K1和K2。 乘法器将轮廓分量YE乘以调整信号K1,以产生调制轮廓分量E1。 乘法器将经调制的轮廓分量E1乘以调整信号K2,以便生成调制轮廓分量E2。 加法器将调制的轮廓分量E2加到亮度信号Y上,以便基于亮度信号的轮廓分量和色差信号的轮廓分量产生已被轮廓增强的亮度信号Ya。