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91. 发明申请

US20100217942A1 USB host controller and controlling method for USB host controller 失效
标题翻译： USB主机控制器和USB主机控制器的控制方法
公开(公告)号：US20100217942A1
公开(公告)日：2010-08-26
申请号：US12656562
申请日：2010-02-03
申请人： Kunihiro Kondo
发明人： Kunihiro Kondo
IPC分类号： G06F13/28 , G06F12/02 , G06F3/00
CPC分类号： G06F13/385
摘要： The present invention aims to provide a USB host controller capable of reducing time for a data transfer between storage devices. A USB host controller according to the present invention includes a buffer memory for USB pipe having a first buffer memory region and a second buffer memory region, and a buffer memory controller configured to control a data transfer between the buffer memory for USB pipe and each of first and second devices. The buffer memory controller stores data from the first device in the first buffer memory region, swaps address information corresponding to the first buffer memory region and address information corresponding to the second buffer memory region, and transfers data stored in the first buffer memory region to the second device, on the basis of the address information corresponding to the first buffer memory region after the swapping.
摘要翻译：本发明旨在提供一种能够减少存储设备之间的数据传输时间的USB主机控制器。根据本发明的USB主机控制器包括：具有第一缓冲存储器区域和第二缓冲存储器区域的USB管缓冲存储器，以及缓冲存储器控制器，被配置为控制用于USB管道的缓冲存储器与每个第一和第二设备。缓冲存储器控制器将来自第一设备的数据存储在第一缓冲存储器区域中，交换与第一缓冲存储器区域对应的地址信息和对应于第二缓冲存储器区域的地址信息，并将存储在第一缓冲存储器区域中的数据传送到基于与交换后的第一缓冲存储器区域对应的地址信息。

92. 发明申请

US20100214146A1 ANALOG-TO-DIGITAL CONVERSION APPARATUS AND METHOD 失效
标题翻译：模拟数字转换设备和方法
公开(公告)号：US20100214146A1
公开(公告)日：2010-08-26
申请号：US12709056
申请日：2010-02-19
申请人： Hiroshi NAKAI
发明人： Hiroshi NAKAI
IPC分类号： H03M1/12
CPC分类号： H03M1/1014 , H03M1/12
摘要： The A/D conversion apparatus includes an A/D converter for converting a potential difference between a reference voltage input and a voltage input to be measured to a digital signal and outputting the digital signal; a first switch connected between a voltage source to be measured and the voltage input to be measured; a first sampling capacitor having a first end connected to the voltage input to be measured and to a first end of the first switch, and having a second end connected to a reference power source; a second switch connected between a reference voltage source and the reference voltage input; a second sampling capacitor having a first end connected to the reference voltage input and to a first end of the second switch, and having a second end connected to the reference power source; and an impedance adjusting circuit, which is connected between the reference voltage source and a second end of the second switch, for changing, in stepwise fashion, impedance between the reference voltage source and the second end of the second switch.
摘要翻译： A / D转换装置包括用于将参考电压输入和要测量的电压输入之间的电位差转换为数字信号并输出数字信号的A / D转换器; 连接在要测量的电压源和要测量的电压输入之间的第一开关; 第一采样电容器，其具有连接到要测量的电压输入的第一端和所述第一开关的第一端，并且具有连接到参考电源的第二端; 连接在参考电压源和参考电压输入之间的第二开关; 第二采样电容器，其具有连接到所述参考电压输入的第一端和所述第二开关的第一端，并且具有连接到所述参考电源的第二端; 以及阻抗调整电路，其连接在参考电压源和第二开关的第二端之间，以逐步的方式改变参考电压源与第二开关的第二端之间的阻抗。

93. 发明申请

US20100213973A1 Status holding circuit and status holding method 失效
标题翻译：状态保持电路和状态保持方法
公开(公告)号：US20100213973A1
公开(公告)日：2010-08-26
申请号：US12656935
申请日：2010-02-19
申请人： Toshio Takeuchi
发明人： Toshio Takeuchi
IPC分类号： H03K19/173
CPC分类号： G06F11/0766
摘要： A status holding circuit includes status holding sections of M stages (M is an integer equal to or more than 2) connected in series. Each of the status holding sections includes: N latches (N is an integer equal to or more than 2) provided for N input signals to N input terminals, respectively; and a switch circuit configured to set a data to a jth latch of the N latches in an ith status holding section of the M-stage status holding sections when a status signal is supplied to a jth input terminal of the N input terminals at an ith timing.
摘要翻译：状态保持电路包括串联连接的M级的状态保持部（M为等于或大于2的整数）。每个状态保持部分分别包括N个输入信号分配给N个输入端的N个锁存器（N是等于或大于2的整数）; 以及开关电路，其被配置为当状态信号被提供给所述N个输入端子的第j个输入端时，将所述N个锁存器的第j个锁存器设置在所述M级状态保持部分的第i个状态保持部分中定时。

94. 发明授权

US07782700B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07782700B2
公开(公告)日：2010-08-24
申请号：US12420275
申请日：2009-04-08
申请人： Kenichi Kuboyama , Hideaki Arima
发明人： Kenichi Kuboyama , Hideaki Arima
IPC分类号： G11C7/00 , G11C5/14
CPC分类号： G11C29/02 , G11C7/1078 , G11C7/1084 , G11C7/109 , G11C29/025 , G11C29/028 , G11C29/50008 , G11C2207/2254
摘要： In a semiconductor or memory device, a first ODT (On Die Termination) circuit is provided between a termination voltage port and a command input port. A first ODT controlling circuit is connected between the termination voltage port and the first ODT circuit, and detects a level of a voltage applied to the termination voltage port and controls the first ODT circuit to connect the termination voltage port and the command input port based on the detection result.
摘要翻译：在半导体或存储器件中，在终端电压端口和命令输入端口之间提供第一ODT（On Die Termination）电路。第一ODT控制电路连接在终端电压端口和第一ODT电路之间，并且检测施加到终端电压端口的电压的电平，并且控制第一ODT电路以连接端接电压端口和命令输入端口，基于检测结果。

95. 发明授权

US07781233B2 Method of manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US07781233B2
公开(公告)日：2010-08-24
申请号：US12429467
申请日：2009-04-24
申请人： Ryuji Tomita , Yosuke Sugiyama
发明人： Ryuji Tomita , Yosuke Sugiyama
IPC分类号： H01L21/00
CPC分类号： H01L22/20 , H01L21/28518 , H01L22/12
摘要： In a semiconductor manufacturing method, a metal film is formed on a substrate and heat treated. The relationship between substrate warping and the heat treatment temperature during silicide formation is acquired (S1). A silicide film is formed by forming a metal film on a substrate and heat treating, including substrate measurement during heat treatment (S2). The relationship between substrate warping at heat treatment temperature is determined from the relationship between the warping of the substrate and the temperature for heat treatment and the temperature for heat treatment carried out on the substrate when the warping of the substrate is measured. The difference between found warping and the measured warping is calculated (S4). Whether the difference exceeds a predetermined value is determined (S5). If the difference exceeds a predetermined value, heat treatment conditions are adjusted (S8), but they not adjusted if the difference is no greater than the predetermined value.
摘要翻译：在半导体制造方法中，在基板上形成金属膜并进行热处理。获得硅化物形成过程中衬底翘曲与热处理温度之间的关系（S1）。通过在基板上形成金属膜并进行热处理（包括热处理时的基板测量）（S2）而形成硅化物膜。热处理温度下的基板翘曲之间的关系由基板翘曲与热处理温度的关系以及测定基板翘曲时对基板进行热处理的温度的关系求出。计算发现翘曲与测量翘曲之间的差异（S4）。确定差是否超过预定值（S5）。如果差异超过预定值，则调整热处理条件（S8），但是如果差不大于预定值，则不进行调整。

96. 发明申请

US20100210102A1 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US20100210102A1
公开(公告)日：2010-08-19
申请号：US12758432
申请日：2010-04-12
申请人： Akira FURUYA
发明人： Akira FURUYA
IPC分类号： H01L21/768
CPC分类号： H01L21/76831 , H01L21/76843 , H01L21/76844 , H01L21/76846 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Aimed at improving adhesiveness between upper and lower interconnects in semiconductor devices, a semiconductor device of the present invention includes a second dielectric multi-layered film formed on a substrate, and containing a lower interconnect; a first dielectric multi-layered film formed on the second dielectric multi-layered film, and having a recess; an MOx film formed on the inner wall of the recess, and containing a metal M and oxygen as major components; an M film formed on the MOx film, and containing the M as a major component; and an electric conductor formed on the M film so as to fill the recess, and containing Cu as a major component, wherein the surficial portion of the interconnect fallen straight under the bottom of the recess has an oxygen concentration of 1% or smaller.
摘要翻译：为了提高半导体器件中的上下互连之间的粘合性，本发明的半导体器件包括形成在基板上并包含下互连的第二介质多层膜; 形成在所述第二电介质多层膜上并具有凹部的第一电介质多层膜; 形成在凹部的内壁上并含有金属M和氧作为主要成分的MOx膜; 形成在MOx膜上并含有M作为主要成分的M膜; 以及形成在M膜上的电导体，以填充凹部，并且包含Cu作为主要成分，其中互连的表面部分在凹部的底部下方直线的氧浓度为1％以下。

97. 发明申请

US20100210044A1 CHARGE TRANSFER DEVICE 失效
标题翻译：充电传输装置
公开(公告)号：US20100210044A1
公开(公告)日：2010-08-19
申请号：US12772666
申请日：2010-05-03
申请人： Eiji MATSUYAMA
发明人： Eiji MATSUYAMA
IPC分类号： H01L21/66
CPC分类号： H01L29/76833 , H01L27/14806
摘要： A charge transfer device 1 has an P-type region, an N-type well provided to the surficial portion of the P-type region, and transfer electrodes having P-type conductivity, provided over the N-type substrate while placing an insulating film in between.
摘要翻译：电荷转移装置1具有P型区域，设置在P型区域的表面部分的N型阱以及设置在N型衬底上的具有P型导电性的转移电极，同时放置绝缘膜之间。

98. 发明申请

US20100207093A1 Semiconductor device and method of manufacturing semiconductor device 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20100207093A1
公开(公告)日：2010-08-19
申请号：US12656728
申请日：2010-02-16
申请人： Naoya Inoue , Yoshihiro Hayashi , Kishou Kaneko
发明人： Naoya Inoue , Yoshihiro Hayashi , Kishou Kaneko
IPC分类号： H01L45/00 , H01L21/441
CPC分类号： H01L21/76807 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1633
摘要： Provided is a semiconductor device including a substrate, and a first wiring layer, a second wiring layer, and a switch via formed on the substrate. The first wiring layer has first wiring formed therein and the second wiring layer has second wiring formed therein. The switch via connects the first wiring and the second wiring. The switch via includes at least at its bottom a switch element including a resistance change layer. A resistance value of the resistance change layer changes according to a history of an electric field applied thereto.
摘要翻译：提供了一种半导体器件，其包括基板，以及形成在基板上的第一布线层，第二布线层和开关通孔。第一布线层具有形成在其中的第一布线，并且第二布线层具有形成在其中的第二布线。开关通孔连接第一布线和第二布线。开关通孔至少在其底部包括包括电阻变化层的开关元件。电阻变化层的电阻值根据施加到其上的电场的历史而变化。

99. 发明授权

US07777298B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07777298B2
公开(公告)日：2010-08-17
申请号：US12501757
申请日：2009-07-13
申请人： Hiroaki Ohkubo , Yasutaka Nakashiba
发明人： Hiroaki Ohkubo , Yasutaka Nakashiba
IPC分类号： H01L23/52
CPC分类号： H01L23/5252 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a semiconductor substrate, and an electrical fuse provided on the semiconductor substrates. The electrical fuse includes a first fuse link and a second fuse link mutually connected in series, a first current inlet/outlet terminal (first terminal) and a second current inlet/outlet terminal (second terminal) respectively provided at an end and the other end of the first fuse link, and a third current inlet/outlet terminal (second terminal) and a fourth current inlet/outlet terminal (third terminal) provided at an end and the other end of the second fuse link.
摘要翻译：半导体器件包括半导体衬底和设置在半导体衬底上的电熔丝。电熔丝包括分别相互连接的第一熔断体和第二熔断体，分别设置在端部和另一端的第一电流入口/出口端子（第一端子）和第二电流入口/出口端子（第二端子）以及设置在第二熔断体的端部和另一端的第三电流入口/出口端子（第二端子）和第四电流入口/出口端子（第三端子）。

100. 发明申请

US20100205386A1 Memory controller and memory control method 审中-公开
标题翻译：内存控制器和内存控制方式
公开(公告)号：US20100205386A1
公开(公告)日：2010-08-12
申请号：US12656482
申请日：2010-02-01
申请人： Haruki Yamashita
发明人： Haruki Yamashita
IPC分类号： G06F12/00 , G11C7/00
CPC分类号： G06F13/1689 , G11C29/02 , G11C29/023 , G11C29/028 , G11C29/38 , G11C29/50 , G11C29/50012
摘要： In order to provide a memory controller capable of calibrating a memory access timing even in a case where an application has no blanking interval, the memory controller includes: a delay circuit (3) for delaying data strobe signals; at least two FIFO buffer units (7, 8, and 9) for storing data values of data signals transmitted from a memory based on at least two of the data strobe signals delayed by the delay circuit (3), respectively; a comparator (4) for comparing the data values stored in the at least two FIFO buffer units; and a control circuit (6) for controlling delay time periods for the at least two of the data strobe signals by using the delay circuit (3) based on comparison results (10) acquired from the comparator (4). Further, one of the data values stored in the at least two FIFO buffer units is used also for normal operation.
摘要翻译：为了提供即使在应用程序没有消隐间隔的情况下能够校准存储器访问定时的存储器控制器，存储器控制器包括：延迟电路（3），用于延迟数据选通信号; 至少两个FIFO缓冲器单元（7,8和9），用于分别基于延迟电路（3）延迟的至少两个数据选通信号来存储从存储器发送的数据信号的数据值; 比较器（4），用于比较存储在所述至少两个FIFO缓冲器单元中的数据值; 以及控制电路（6），用于基于从比较器（4）获取的比较结果（10），通过使用延迟电路（3）来控制至少两个数据选通信号的延迟时间段。此外，存储在至少两个FIFO缓冲器单元中的数据值之一也用于正常操作。

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