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91. 发明授权

US08497867B2 Information processing system, information processing apparatus, display processing method therefor, and computer-readable storage medium 有权
标题翻译：信息处理系统，信息处理装置，显示处理方法和计算机可读存储介质
公开(公告)号：US08497867B2
公开(公告)日：2013-07-30
申请号：US12616438
申请日：2009-11-11
申请人： Masato Fujiwara , Toru Kikuchi , Daiki Kondo
发明人： Masato Fujiwara , Toru Kikuchi , Daiki Kondo
IPC分类号： G09G5/39 , G06F13/00
CPC分类号： H04N1/00458 , H04N1/0408 , H04N2201/0089
摘要： An information processing system stores a plurality of content data having different display qualities for each content in a storage unit, and detects a user operation to instruct switching of a content displayed on a display screen, and determines a switching speed of content display on the display screen based on the detected user operation, and decides a distribution for content data of each display quality to be read out to a temporary memory unit based on the determined switching speed, and reads out the content data from the storage unit to the temporary memory unit in accordance with the decided distribution.
摘要翻译：信息处理系统将具有不同显示质量的多个内容数据存储在存储单元中，并且检测用户操作以指示显示在显示屏幕上的内容的切换，并且确定显示器上的内容显示的切换速度基于所检测到的用户操作的屏幕，并且基于所确定的切换速度来决定将要被读出到每个显示质量的内容数据的分发给临时存储器单元，并将该内容数据从存储单元读取到临时存储器单元按照决定分配。

92. 发明授权

US08446420B2 Memory system and method for improved utilization of read and write bandwidth of a graphics processing system 失效
标题翻译：用于改善对图形处理系统的读写带宽的利用的存储器系统和方法
公开(公告)号：US08446420B2
公开(公告)日：2013-05-21
申请号：US13487802
申请日：2012-06-04
申请人： William Radke
发明人： William Radke
IPC分类号： G09G5/39 , G06T1/20 , G06F13/00
CPC分类号： G09G5/39 , G09G2360/123
摘要： A system for processing graphics data. The graphics processing system includes an embedded memory array having at least three separate banks of single-ported memory in which graphics data are stored. A memory controller coupled to the banks of memory writes post-processed data to a first bank of memory while reading data from a second bank of memory. A synchronous graphics processing pipeline processes the data read from the second bank of memory and provides the post-processed graphics data to the memory controller to be written back to a bank of memory. The processing pipeline concurrently processes an amount of graphics data at least equal to that included in a page of memory. A third bank of memory is precharged concurrently with writing data to the first bank and reading data from the second bank in preparation for access when reading data from the second bank of memory is completed.
摘要翻译：用于处理图形数据的系统。图形处理系统包括嵌入式存储器阵列，其具有存储图形数据的至少三个独立的单端口存储器组。耦合到存储体的存储器控制器将从第二存储器存储器读取数据的后处理数据写入第一存储体。同步图形处理流水线处理从第二存储体读出的数据，并将后处理的图形数据提供给存储器控制器以写回存储体。处理流水线同时处理至少等于包含在存储器页中的图形数据量。当从第二存储器存储器读取数据完成时，第三存储器组同时对第一存储体写入数据并从第二存储体读取数据以准备访问。

93. 发明授权

US08395630B2 Format conversion apparatus from band interleave format to band separate format 有权
标题翻译：格式转换装置从频带交织格式到频带分离格式
公开(公告)号：US08395630B2
公开(公告)日：2013-03-12
申请号：US11769319
申请日：2007-06-27
申请人： Jong Myon Kim , Jun Jin Kong , Jeongwook Kim , Suk Jin Kim , Soojung Ryu , Kyoung June Min , Dong-Hoon Yoo , Dong Kwan Suh , Yeon Gon Cho
发明人： Jong Myon Kim , Jun Jin Kong , Jeongwook Kim , Suk Jin Kim , Soojung Ryu , Kyoung June Min , Dong-Hoon Yoo , Dong Kwan Suh , Yeon Gon Cho
IPC分类号： G09G5/39
CPC分类号： G06T3/606
摘要： A format conversion apparatus which converts image data of a band interleave format into image data of a band separate format is provided. The apparatus includes a memory which stores image data of a band interleave format; and a converting module which reads the memory by increasing a read address of the memory for each stride, and converts the image data of the band interleave format into image data of a band separate format.
摘要翻译：提供将频带交织格式的图像数据转换成带分离格式的图像数据的格式转换装置。该装置包括：存储器，其存储频带交织格式的图像数据; 以及转换模块，其通过增加每个步幅的存储器的读取地址来读取存储器，并将频带交织格式的图像数据转换为带分离格式的图像数据。

94. 发明授权

US08373713B2 Image display apparatus and control method thereof 有权
标题翻译：图像显示装置及其控制方法
公开(公告)号：US08373713B2
公开(公告)日：2013-02-12
申请号：US13045906
申请日：2011-03-11
申请人： Masahiro Funada
发明人： Masahiro Funada
IPC分类号： G06F13/28 , G09G5/39
CPC分类号： G09G5/391 , G09G5/395 , G09G2340/02 , G09G2360/06 , G09G2360/12 , H04N5/04 , H04N9/3185
摘要： An image display apparatus includes a memory 1 having a first mode and a second mode in which image data are sequentially written and read per frame and per sub-frame area respectively, a compressor 10 capable of switching a compression output state and an uncompressed output state in which a compression image data and an uncompressed image data are outputted respectively, and a decompressor 20 capable of switching a decompression output state and a non-decompression output state. A controller 6 switches the compressor from the uncompressed output state to the compression output state during a first input vertical blanking period, switches the decompressor from the non-decompression output state to the decompression output state during a first output vertical blanking period immediately after the first input vertical blanking period, and switches the memory from the second mode to the first mode during a first output vertical blanking period.
摘要翻译：图像显示装置包括具有第一模式和第二模式的存储器1，其中每帧和每个子帧区域顺序地写入和读取图像数据;压缩器10，其能够切换压缩输出状态和未压缩输出状态分别输出压缩图像数据和未压缩图像数据，以及能够切换解压缩输出状态和非解压缩输出状态的解压缩器20。在第一输入垂直消隐期间，控制器6将压缩器从未压缩输出状态切换到压缩输出状态，在紧接在第一输入垂直消隐期之后的第一输出垂直消隐期间，将解压缩器从非解压缩输出状态切换到解压缩输出状态输入垂直消隐周期，并在第一个输出垂直消隐期间将存储器从第二模式切换到第一模式。

95. 发明授权

US08369690B2 Recording medium, reproduction apparatus, recording method, integrated circuit, program, and reproduction method 有权
标题翻译：记录介质，再现装置，记录方法，集成电路，程序和再现方法
公开(公告)号：US08369690B2
公开(公告)日：2013-02-05
申请号：US12437477
申请日：2009-05-07
申请人： Joseph McCrossan , Tomoyuki Okada , Kazuhiro Mochinaga
发明人： Joseph McCrossan , Tomoyuki Okada , Kazuhiro Mochinaga
IPC分类号： H04N5/78 , H04N5/84 , H04N5/92 , H04N5/93 , H04N5/775 , H04N5/917 , H04N5/935 , H04N7/12 , H04N7/16 , H04N9/80 , H04N9/475 , G06F3/12 , G09G5/39 , H04J3/00 , H04J3/04 , H04L12/56
CPC分类号： H04N9/8227 , G11B27/10 , G11B27/105 , G11B27/3027 , G11B27/3036 , G11B2220/2541 , H04N5/783 , H04N5/85 , H04N9/8042 , H04N9/8205
摘要： AVClip recorded in BD-ROM is obtained by multiplexing a graphics stream and a video stream. The graphics stream is a PES packet sequence that includes 1) PES packets storing graphics data (ODS) and 2) PES packets storing control information (PCS). In each ODS, values of DTS and PTS indicate a timing of decoding start for corresponding graphics data, and a timing of decoding end for corresponding graphics data, respectively. In each PCS, a value of PTS indicates a display timing of corresponding decoded graphics data combined with the video stream.
摘要翻译：通过复用图形流和视频流来获得BD-ROM中记录的AVClip。图形流是PES分组序列，其包括1）存储图形数据（ODS）的PES分组和2）存储控制信息（PCS）的PES分组。在每个ODS中，DTS和PTS的值分别指示用于相应图形数据的解码开始的定时，以及针对对应的图形数据解码结束的定时。在每个PCS中，PTS的值指示与视频流组合的对应的解码图形数据的显示定时。

96. 发明申请

US20130021354A1 METHOD AND SYSTEM FOR DISPLAYING USING BUFFER SWAPPING 有权
标题翻译：使用缓冲区切换显示的方法和系统
公开(公告)号：US20130021354A1
公开(公告)日：2013-01-24
申请号：US13544165
申请日：2012-07-09
申请人： Peter Anthony Van Eerd , Richard Jeffrey Kehres , Carl Edward Kilgour Pacey
发明人： Peter Anthony Van Eerd , Richard Jeffrey Kehres , Carl Edward Kilgour Pacey
IPC分类号： G09G5/39
CPC分类号： G09G5/399 , G09G5/346 , G09G5/393 , G09G2360/127
摘要： Methods and systems which may implement buffer swapping are provided. The methods include rendering, onto screen locations of a display screen, data from a memory having a first buffer and a second buffer, each buffer having respective buffer memory locations which correspond to the screen locations of the display screen. The methods can include: rendering first data from the first buffer onto the display screen; writing, to the second buffer, second data based on at least some of the first data from the first buffer by performing at least one of transforming at least some first data and changing corresponding screen locations of at least some first data from the first buffer, by writing at most once to each buffer memory location of the second buffer; and rendering the second data from the second buffer onto the display screen.
摘要翻译：提供了可能实现缓冲区交换的方法和系统。所述方法包括将来自具有第一缓冲器和第二缓冲器的存储器的数据呈现在显示屏幕的屏幕位置上，每个缓冲器具有与显示屏幕的屏幕位置对应的各自的缓冲存储器位置。所述方法可以包括：将第一数据从第一缓冲器呈现到显示屏上; 基于来自第一缓冲器的至少一些第一数据，通过执行至少一个变换至少一些第一数据并从第一缓冲器改变至少一些第一数据的相应屏幕位置来向第二缓冲器写入第二数据，通过最多写入一次到第二缓冲器的每个缓冲存储器位置; 以及将所述第二数据从所述第二缓冲器呈现到所述显示屏上。

97. 发明授权

US08358312B2 Multi-pass system and method supporting multiple streams of video 有权
标题翻译：支持多视频流的多通道系统和方法
公开(公告)号：US08358312B2
公开(公告)日：2013-01-22
申请号：US13193176
申请日：2011-07-28
申请人： Patrick Law , Darren Neuman , David Baer
发明人： Patrick Law , Darren Neuman , David Baer
IPC分类号： G06T1/20 , G09G5/39 , G09G5/36
CPC分类号： G06F13/28 , H04N21/426
摘要： Systems and methods are disclosed for performing multiple processing of data in a network. In one embodiment, the network comprises a first display pipeline that is formed in real time from a plurality of possible display pipelines and that performs at least a first processing step on received data. A buffer stores the processed data and a second display pipeline that is formed in real time from a plurality of possible display pipelines performs at least a second processing step on stored data.
摘要翻译：公开了用于在网络中执行数据的多个处理的系统和方法。在一个实施例中，网络包括从多个可能的显示管道实时形成并且对接收到的数据执行至少第一处理步骤的第一显示管道。缓冲器存储经处理的数据，并且从多个可能的显示管道实时形成的第二显示管道对存储的数据执行至少第二处理步骤。

98. 发明申请

US20130002693A1 VIDEO DISPLAY APPARATUS, BUFFER MANAGEMENT METHOD AND VIDEO DISPLAY SYSTEM 审中-公开
标题翻译：视频显示设备，缓冲器管理方法和视频显示系统
公开(公告)号：US20130002693A1
公开(公告)日：2013-01-03
申请号：US13397444
申请日：2012-02-15
申请人： Kazuya Nara
发明人： Kazuya Nara
IPC分类号： G09G5/39
CPC分类号： H04N21/4147 , H04N21/4334 , H04N21/4335 , H04N21/4424 , H04N21/47202 , H04N21/47217 , H04N21/4882
摘要： One embodiment provides a video display apparatus, including: a buffer configured to receive data; a buffer controller configured to control the buffer; and a reproduction part configured to reproduce the data accumulated in the buffer, wherein, when reproduction from an arbitrary position is designated for a time during which the reproduction part reproduces the data, the buffer controller controls the buffer to accumulate data of a designated destination while continuing reproduction of the data left in the buffer.
摘要翻译：一个实施例提供了一种视频显示装置，包括：被配置为接收数据的缓冲器; 配置为控制所述缓冲器的缓冲器控制器; 以及再现部，被配置为再现在所述缓冲器中累积的数据，其中当从任意位置进行的再现被指定为所述再现部分再现所述数据的时间时，所述缓冲器控制器控制所述缓冲器以累积指定目的地的数据，继续再现缓冲区中留下的数据。

99. 发明授权

US08339405B2 Programmable data processing circuit 有权
标题翻译：可编程数据处理电路
公开(公告)号：US08339405B2
公开(公告)日：2012-12-25
申请号：US12299671
申请日：2007-05-07
申请人： Carlos Antonio Alba Pinto , Ramanathan Sethuraman
发明人： Carlos Antonio Alba Pinto , Ramanathan Sethuraman
IPC分类号： G09G5/39 , G06F13/18 , G06F13/00
CPC分类号： G06T1/60
摘要： A programmable data processing circuit has a memory for storing pixel values, or more generally data values as a function of position in a signal. The programmable data processing circuit supports instructions that include an indication of a selected parameter value set that indicates how a plurality of data values must be arranged for parallel output from a memory. Instructions that indicate different parameter value sets can be executed intermixed with one another. The programmable data processing circuit responds to instructions of this type by retrieving the selected parameter value sets from a parameter storage circuit (246), and controlling a switching circuit (22) between a memory port (21) of a memory circuit (20) and a data port (26) at least partly dependent on the selected parameter value set.
摘要翻译：可编程数据处理电路具有用于存储像素值的存储器，或更一般地，作为信号中的位置的函数的数据值。可编程数据处理电路支持指令，其包括指示如何为存储器并行输出多个数据值的选定参数值集合的指示。指示不同参数值集的指令可以执行相互混合。可编程数据处理电路通过从参数存储电路（246）检索所选择的参数值集合以及控制存储器电路（20）的存储器端口（21）和存储器电路（20）的存储器端口（21）之间的切换电路（22）和至少部分地依赖于所选择的参数值集合的数据端口（26）。

100. 发明申请

US20120293545A1 GRAPHICS PROCESSING SYSTEMS 有权
标题翻译：图形处理系统
公开(公告)号：US20120293545A1
公开(公告)日：2012-11-22
申请号：US13111658
申请日：2011-05-19
申请人： Andreas Engh-Halstvedt , Jorn Nystad , Edvard Sorgard , Frode Heggelund
发明人： Andreas Engh-Halstvedt , Jorn Nystad , Edvard Sorgard , Frode Heggelund
IPC分类号： G09G5/377 , G09G5/39
CPC分类号： G06T15/40 , G06F17/30265 , G06T3/4038 , G06T11/001 , G06T11/40 , G06T11/60 , G06T2210/62 , G09G5/14 , G09G5/39 , G09G5/393
摘要： In a tile-based graphics processing system, when an overlay image is to be rendered onto an existing image, the existing tile data for the existing image from the frame buffer in the main memory is pre-loaded into the local colour buffer of the graphics processor (step 41). The overlay content is then rendered and used to modify the tile data stored in the colour buffer (step 44). When the data for a given sampling position stored in the tile buffer is modified as a result of the overlay image, a corresponding dirty bit for the tile region that the sampling position falls within is set (step 45). Then, when all the rendering for the tile has been completed, the dirty bits are examined to determine which regions of the tile have been modified (step 46). The modified tile regions are written back to the output image in the frame buffer in the main memory (step 47), but any regions whose dirty bits have not been set are not written back to the frame buffer in the main memory.
摘要翻译：在基于瓦片的图形处理系统中，当将覆盖图像呈现到现有图像上时，来自主存储器中的帧缓冲器的现有图像的现有瓦片数据被预加载到图形的本地颜色缓冲器中处理器（步骤41）。覆盖内容然后被渲染并用于修改存储在彩色缓冲器中的瓦片数据（步骤44）。当存储在瓦片缓冲器中的给定采样位置的数据作为覆盖图像的结果被修改时，设置采样位置所在的瓦片区域的对应的脏位（步骤45）。然后，当瓦片的所有渲染已经完成时，检查脏位以确定瓦片的哪些区域已被修改（步骤46）。经修改的瓦片区域被写回到主存储器中的帧缓冲器中的输出图像（步骤47），但是没有设置脏位的任何区域都不会被写回到主存储器中的帧缓冲器。

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