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91. 发明授权

US4099259A Data stores and data storage system 失效
标题翻译：数据存储和数据存储系统
公开(公告)号：US4099259A
公开(公告)日：1978-07-04
申请号：US731248
申请日：1976-10-12
申请人： Robert Parsons , Howard Cook
发明人： Robert Parsons , Howard Cook
IPC分类号： H04N7/025 , G09G5/22 , G11C8/04 , H04L29/00 , H04N7/03 , H04N7/035 , H04N7/088 , G06F13/06
CPC分类号： H04N7/0882 , G09G5/222
摘要： In a Teletext transmission system, data is transmitted in digital form during lines in the field blanking period of a composite video signal of a television transmission. On reception, the information is decoded and utilized to provide a display comprising a page having a predetermined number of rows of information in alphanumeric or graphics form. The data is received in blocks comprising information digits and each block has an associated group of address digits so that each block can be directed to an appropriate storage location in a first store, regardless of the order in which the data blocks are transmitted. The contents of the first store can then be transferred in address order into a larger capacity serial store ready for use in generating the display. Thus it is possible for a number of pages of information data to be correctly assembled in serial row order, ready for display generation, in a manner accommodating non-transmitted blank rows.
摘要翻译：在图文电视传输系统中，数据在电视传输的复合视频信号的场消隐期间的行中以数字形式发送。在接收时，信息被解码并用于提供包括具有字母数字或图形形式的具有预定数量的信息行的页面的显示。在包括信息数字的块中接收数据，并且每个块具有相关联的地址数字组，使得每个块可以被引导到第一存储中的适当的存储位置，而不管发送数据块的顺序。然后可以将第一个商店的内容以地址顺序传送到准备好用于生成显示器的更大容量的串行存储器中。因此，可以以容纳未发送的空白行的方式，以串行顺序正确地组合多页信息数据，准备好进行显示生成。

92. 发明授权

US4069970A Data access circuit for a memory array 失效
标题翻译：存储器阵列的数据访问电路
公开(公告)号：US4069970A
公开(公告)日：1978-01-24
申请号：US699423
申请日：1976-06-24
申请人： Clair Alan Buzzard , Richard Cyril Gifford , Frank William Lescinsky , Robert Michael Zachok
发明人： Clair Alan Buzzard , Richard Cyril Gifford , Frank William Lescinsky , Robert Michael Zachok
IPC分类号： G06F3/16 , G06F5/00 , G06F11/00 , G06F11/10 , G06F12/02 , G11C7/00 , G11C8/00 , G11C8/04 , G11C27/00 , G11C29/00
CPC分类号： G11C8/00 , G06F11/0754 , G06F12/0207 , G06F3/16 , G06F5/00 , G11C7/00 , G11C8/04 , G06F11/1008
摘要： A memory array, having a plurality of intersecting rows and columns, stores digitized speech. Each row and column intersection consists of a binary storage cell for storing one bit of digitized speech. Incoming digitized speech is loaded into columns of the memory array in a plurality of repetitive loading sequences, each loading sequence including: reading out the bits stored in successive rows of binary storage cells, replacing in each successive row of bits, a predetermined one of the bits in the read out row with a successive one of the bits of the digitized speech and writing each read out row of bits including the replaced bit back into the row. Multibit binary grunts (digitized speech segments) stored in the array are read out therefrom by applying the bits of the grunts to time slots in frames on a time-division highway, each frame being of n bits duration and including one bit from each of n grunts stored in the array. A selected grunt is extracted from the highway by commencing a count of the bits on the highway with a first bit of the selected grunt and by extracting the first bit and every n.sup.th bit thereafter. Memory malfunction is indicated when the number of rows in the array containing parity errors exceeds a predetermined threshold number.
摘要翻译：具有多个相交行和列的存储器阵列存储数字化语音。每行和列交叉点由用于存储一位数字化语音的二进制存储单元组成。接收的数字化语音以多个重复加载序列被加载到存储器阵列的列中，每个加载序列包括：读出存储在二进制存储单元的连续行中的位，在每个连续的位行中替换预定的一个读出行中的位与数字化语音的连续的一个比特并且将每个读出的包括被替换的位的位的行写入行。存储在阵列中的多位二进制啁啾（数字化语音段）通过将啁啾的比特应用于时分高速公路上的帧中的时隙，每个帧的n位持续时间并且包括从n 咕噜存储在阵列中。通过使用所选咕噜的第一位开始高速公路上的比特的计数，并且之后提取第一比特和每第n个比特，从高速公路中提取所选择的咕噜声。当包含奇偶校验错误的阵列中的行数超过预定阈值时，会指示内存故障。

93. 发明授权

US4032904A Means for refreshing AC stable storage cells 失效
标题翻译：用于刷新AC稳定存储单元的方法
公开(公告)号：US4032904A
公开(公告)日：1977-06-28
申请号：US594382
申请日：1975-07-09
申请人： Kevin Lee Anderson , Luis Maria Arzubi
发明人： Kevin Lee Anderson , Luis Maria Arzubi
IPC分类号： G11C11/41 , G11C8/04 , G11C8/16 , G11C11/24 , G11C11/406 , G11C7/00
CPC分类号： G11C8/16 , G11C11/406 , G11C8/04
摘要： A refresh circuit for AC stable storage cells utilizing an asymmetric a stable power source for controlling an auxiliary shift register which in turn controls the refreshing shift register. The outputs of the refreshing shift register are coupled to the gate electrodes of gating devices coupled to the memory word line.

94. 发明授权

US3935446A Apparatus for sensing radiation and providing electrical readout 失效
标题翻译：用于感测辐射和提供电气读出的装置
公开(公告)号：US3935446A
公开(公告)日：1976-01-27
申请号：US554155
申请日：1975-02-28
申请人： Gerald J. Michon
发明人： Gerald J. Michon
IPC分类号： G11C8/04 , H01L27/148 , H04N5/32 , H04N5/372 , H04N5/378 , H01J39/12
CPC分类号： G11C8/04 , H01L27/14862 , H04N3/155
摘要： An array of radiation sensing devices each including a pair of closely coupled conductor-insulator-semiconductor cells, one a row line connected cell and the other a column line connected cell, is provided on a common semiconductor substrate. The potential well associated with the row connected cell is deeper than the potential well associated with the column connected cell. Read out of a row of devices is accomplished by lowering the absolute potential of the row line to cause charge stored in the row connected cells to transfer to column connected cells of the row. The voltage on each of the column lines is sensed in sequence to provide a video signal. Subsequent to sensing the column line potentials can be lowered to inject the stored carriers into the substrate or the row line potential may be reestablished to return the stored charge to the potential wells associated with the cells connected to the row lines and thus permit repeated read out.
摘要翻译：辐射检测装置的阵列，其各自包括一对紧密耦合的导体 - 绝缘体半导体单元，一个行线连接单元，另一个是列线连接单元，设置在公共半导体基板上。与行连接的单元相关联的势阱比与柱连接的单元相关联的势阱更深。读出一排设备是通过降低行线的绝对电位来实现的，以使存储在所连接的行中的电荷的电荷传输到行的列连接的单元格。依次检测每条列线上的电压以提供视频信号。在感测之后，可以降低列线电位以将存储的载流子注入衬底中，或者可以重新建立行线电位以将存储的电荷返回到与连接到行线的单元相关联的势阱，并且因此允许重复读出。

95. 发明授权

US3631410A Event recorder 失效
公开(公告)号：US3631410A
公开(公告)日：1971-12-28
申请号：US3631410D
申请日：1969-11-03
申请人： GEN MOTORS CORP
发明人： VELASCO BRUCE M
IPC分类号： G01R13/04 , G11C8/04 , G11C17/16 , H03M1/00 , G11C11/36
CPC分类号： G11C17/16 , G01R13/04 , G11C8/04 , H03M1/361 , Y10S148/055
摘要： An apparatus is provided for recording a signal voltage as a function of magnitude and time. The apparatus includes a memory matrix comprising a plurality of diodes connected between different ones of a series of magnitude drive lines and a series of time drive lines. A magnitude input circuit is connected with the magnitude drive lines for applying a drive voltage to different ones of the drive lines as a function of the magnitude of the signal voltage. A time input circuit is connected with the time drive lines for coupling different ones of the drive lines to a reference voltage point as a function of time. The drive voltage is substantially greater than the peak voltage rating of the diodes. Therefore, as the drive voltage is applied to the selected ones of the magnitude drive lines and as selected ones of the time drive lines are coupled to the reference voltage point, the diodes connected between the selected ones of the magnitude and time drive lines are burned out or open circuited by the drive voltage. Hence, the pattern of open circuited diodes within the memory matrix provides a representation of the magnitude of the signal voltage as a function of time.

96. 发明授权

US3611437A Read-only memory with operative and inoperative data devices located at address stations and with means for controllably charging and discharging appropriate modes of the address stations 失效
标题翻译：具有位于地址站的操作和不正确的数据设备的只读存储器，以及用于控制地址站的适当的充电和放电的手段
公开(公告)号：US3611437A
公开(公告)日：1971-10-05
申请号：US3611437D
申请日：1969-01-16
申请人： GEN INSTRUMENT CORP
发明人： VARADI ANDREW G , RUBINSTEIN RICHARD B
IPC分类号： G11C17/00 , G11C7/10 , G11C8/04 , G11C17/12 , G11C17/18 , G11C11/40
CPC分类号： G11C7/1015 , G11C8/04 , G11C17/12
摘要： A permanent storage memory unit comprises a plurality of information bits stored in a predetermined manner at a plurality of address stations at either a ''''0'''' or a ''''1'''' level. The logic level at a particular address station is determined by the presence or absence of a potentially operative data-switching device. The address stations may be defined by the respective intersections of a plurality of rows and columns. The addressselecting means include column-selecting circuitry merged with the data devices at each of the columns, and row select circuitry operatively connected to the data devices.

97. 发明授权

US3585610A Solid state memory and coding system 失效
标题翻译：固态存储器和编码系统
公开(公告)号：US3585610A
公开(公告)日：1971-06-15
申请号：US3585610D
申请日：1968-07-10
申请人： GULF & WESTERN INDUSTRIES
发明人： BARTLETT PETER G , MESCHI JOSEPH E
IPC分类号： G05B19/045 , G11C8/04 , G11C11/22 , G11C13/00
CPC分类号： G11C11/22 , G05B19/045 , G11C8/04
摘要： A load sequence controller is provided which takes the form of a system of solid state memory elements, write circuits, interrogators and decoders to perform the function of a step switch which serves to allocate a plurality of loads selectively. The memory elements serve to receive and store an electrical signal representative of one of two binary states. The interrogator, which includes a logic decoder, serves to apply interrogating signals selectively to the memory elements, thereby providing a pattern of output signals representative of the binary state of the received signal for, in turn, energizing the selected loads. A circuit is provided for skipping the interrogating function of at least a selected one of the memories. The skipping circuit is interposed between the decoder output circuit and the memories for receiving the interrogation signals and has an output circuit for routing the interrogation signal on a selected one of the decoder output circuits as an input trigger signal to a counter to change the pattern of count signals quickly for skipping the interrogating function of the memory associated with the selected decoder output circuit.

98. 发明授权

US3504353A Buffer memory system 失效
标题翻译：缓冲存储器系统
公开(公告)号：US3504353A
公开(公告)日：1970-03-31
申请号：US3504353D
申请日：1967-07-31
申请人： SCM CORP
发明人： GUZAK JOHN JR
IPC分类号： G06F5/10 , G06F5/14 , G11C8/04 , G11C11/403 , G11C11/408 , G11B5/74
CPC分类号： G06F5/14 , G11C8/04 , G11C11/403 , G11C11/4085

99. 发明授权

US3480959A Range gated integrator 失效
标题翻译：范围集成器
公开(公告)号：US3480959A
公开(公告)日：1969-11-25
申请号：US3480959D
申请日：1968-05-07
申请人： UNITED AIRCRAFT CORP
发明人： RICHMOND IRVING D
IPC分类号： G01S7/292 , G01S13/18 , G11C8/04 , G01S7/28
CPC分类号： G11C8/04 , G01S7/2926 , G01S13/18 , Y10T307/799

100. 发明授权

US11823771B2 Streaming access memory device, system and method 有权
公开(公告)号：US11823771B2
公开(公告)日：2023-11-21
申请号：US17158875
申请日：2021-01-26
申请人： STMicroelectronics International N.V. , STMICROELECTRONICS S.r.l.
发明人： Nitin Chawla , Thomas Boesch , Anuj Grover , Surinder Pal Singh , Giuseppe Desoli
IPC分类号： G11C8/04 , G06N3/02
CPC分类号： G11C8/04 , G06N3/02
摘要： A system includes a random access memory organized into individually addressable words. Streaming access control circuitry is coupled to word lines of the random access memory. The streaming access control circuitry responds to a request to access a plurality of individually addressable words of a determined region of the random access memory by generating control signals to drive the word lines to streamingly access the plurality of individually addressable words of the determined region. The request indicates an offset associated with the determined region and a pattern associated with the streaming access.

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