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91. 发明申请

US20120205720A1 TANTALUM SILICON OXYNITRIDE HIGH-K DIELECTRICS AND METAL GATES 有权
标题翻译： TANTALUM硅氧化物高K电介质和金属栅
公开(公告)号：US20120205720A1
公开(公告)日：2012-08-16
申请号：US13458196
申请日：2012-04-27
申请人： Leonard Forbes , Kie Y. Ahn , Arup Bhattacharyya
发明人： Leonard Forbes , Kie Y. Ahn , Arup Bhattacharyya
IPC分类号： H01L27/04 , H01L29/788 , H01L29/02
CPC分类号： H01L21/0215 , C23C16/308 , H01L21/0223 , H01L21/02255 , H01L21/02332 , H01L21/0234 , H01L21/28079 , H01L21/28273 , H01L21/3141 , H01L21/3145 , H01L21/31637 , H01L28/40 , H01L29/513 , H01L29/517 , H01L29/6653 , H01L29/66545
摘要： Electronic apparatus and methods of forming the electronic apparatus include a tantalum silicon oxynitride film on a substrate for use in a variety of electronic systems. The tantalum silicon oxynitride film may be structured as one or more monolayers. The tantalum silicon oxynitride film may be formed using a monolayer or partial monolayer sequencing process. Metal electrodes may be disposed on a dielectric containing a tantalum silicon oxynitride film.
摘要翻译：形成电子设备的电子设备和方法包括用于各种电子系统的基板上的钽氮氧化硅膜。钽氮氧化硅膜可以被构造为一个或多个单层。可以使用单层或部分单层测序方法形成钽氮氧化硅膜。金属电极可以设置在包含钽氮氧化硅膜的电介质上。

92. 发明授权

US08115325B2 Semiconductor integrated circuit including plurality of bonding pads 有权
标题翻译：半导体集成电路包括多个接合焊盘
公开(公告)号：US08115325B2
公开(公告)日：2012-02-14
申请号：US12385501
申请日：2009-04-09
申请人： Kenichi Ishikawa
发明人： Kenichi Ishikawa
IPC分类号： H01L23/522 , H01L21/822 , H01L27/04 , H01L21/82 , H01L23/52
CPC分类号： H01L24/06 , H01L23/5283 , H01L23/5286 , H01L2224/05553 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01082 , H01L2924/14
摘要： A semiconductor integrated circuit includes a plurality of bonding pads formed along an edge of a semiconductor substrate; a plurality of I/O cells arranged along the edge under the plurality of bonding pads; an upper layer wire mesh including a plurality of upper layer wirings; and a core region formed on the semiconductor substrate. In the semiconductor integrated circuit, the core region has an area larger than an area occupied by the upper layer wire mesh in a plane parallel to a surface of the semiconductor substrate.
摘要翻译：半导体集成电路包括沿着半导体衬底的边缘形成的多个接合焊盘; 多个I / O单元，沿着所述多个接合焊盘的边缘排列; 上层丝网，其包括多个上层布线; 以及形成在半导体衬底上的芯区域。在半导体集成电路中，芯区域的面积大于在与半导体衬底的表面平行的平面中由上层金属丝网占据的面积。

93. 发明申请

US20120032294A1 METHOD FOR FABRICATION OF A SEMICONDUCTOR DEVICE AND STRUCTURE 有权
标题翻译：用于制造半导体器件和结构的方法
公开(公告)号：US20120032294A1
公开(公告)日：2012-02-09
申请号：US13162154
申请日：2011-06-16
申请人： Zvi Or-Bach , Brian Cronquist , Israel Beinglass , Jan Lodewijk de Jong , Deepak C. Sekar
发明人： Zvi Or-Bach , Brian Cronquist , Israel Beinglass , Jan Lodewijk de Jong , Deepak C. Sekar
IPC分类号： H01L27/04
CPC分类号： H01L27/08 , H01L21/26506 , H01L21/26513 , H01L21/76254 , H01L21/8221 , H01L21/84 , H01L23/481 , H01L23/544 , H01L27/0207 , H01L27/0688 , H01L27/105 , H01L27/10876 , H01L27/10894 , H01L27/10897 , H01L27/11 , H01L27/1108 , H01L27/112 , H01L27/11807 , H01L27/11898 , H01L27/1203 , H01L2223/5442 , H01L2223/54426 , H01L2223/54453 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2924/00011 , H01L2924/01322 , H01L2924/10253 , H01L2924/12032 , H01L2924/1301 , H01L2924/1305 , H01L2924/13062 , H01L2924/13091 , H01L2924/15311 , H01L2924/3011 , H01L2924/3025 , H01L2924/00 , H01L2224/80001
摘要： A semiconductor device comprising: a first single crystal silicon layer comprising first transistors, first alignment mark, and at least one metal layer overlying said first single crystal silicon layer, wherein said at least one metal layer comprises copper or aluminum more than other materials; a second layer overlying said at least one metal layer, said second layer comprising second transistors, second alignment mark, and a through via through said second layer, wherein said through via is a part of a connection path between said first transistors and said second transistors, wherein alignment of said through via is based on said first alignment mark and said second alignment mark and effected by a distance between said first alignment mark and said second alignment mark.
摘要翻译：一种半导体器件，包括：第一单晶硅层，包括第一晶体管，第一对准标记和覆盖所述第一单晶硅层的至少一个金属层，其中所述至少一个金属层比其它材料包含铜或铝; 覆盖所述至少一个金属层的第二层，所述第二层包括第二晶体管，第二对准标记和穿过所述第二层的通孔，其中所述通孔是所述第一晶体管和所述第二晶体管之间的连接路径的一部分，其中所述通孔的对准基于所述第一对准标记和所述第二对准标记，并且受到所述第一对准标记和所述第二对准标记之间的距离的影响。

94. 发明授权

US08004014B2 Semiconductor integrated circuit device having metal interconnect regions placed symmetrically with respect to a cell boundary 有权
标题翻译：具有相对于单元边界对称放置的金属互连区域的半导体集成电路器件
公开(公告)号：US08004014B2
公开(公告)日：2011-08-23
申请号：US12542263
申请日：2009-08-17
申请人： Tomoaki Ikegami , Hidetoshi Nishimura , Kazuyuki Nakanishi
发明人： Tomoaki Ikegami , Hidetoshi Nishimura , Kazuyuki Nakanishi
IPC分类号： H01L23/52 , H01L27/04
CPC分类号： H01L27/04 , H01L27/0207 , H01L27/11807
摘要： A layout structure of a semiconductor integrated circuit is provided with which narrowing and breaking of metal interconnects near a cell boundary can be prevented without increasing the data amount and processing time for OPC. A cell A and a cell B are adjacent to each other along a cell boundary. The interconnect regions of metal interconnects from which to the cell boundary no other interconnect region exists are placed to be substantially axisymmetric with respect to the cell boundary, while sides of diffusion regions facing the cell boundary are asymmetric with respect to the cell boundary.
摘要翻译：提供半导体集成电路的布局结构，可以防止在单元边界附近的金属互连的变窄和断开，而不增加OPC的数据量和处理时间。单元格A和单元格B沿着单元边界彼此相邻。相对于单元边界，金属互连的连接区域到单元边界没有其他互连区域被放置为基本上是轴对称的，而面向单元边界的扩散区域的边相对于单元边界是不对称的。

95. 发明申请

US20110175197A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
标题翻译：半导体集成电路设备
公开(公告)号：US20110175197A1
公开(公告)日：2011-07-21
申请号：US13010191
申请日：2011-01-20
申请人： Hiroshi FURUTA
发明人： Hiroshi FURUTA
IPC分类号： H01L27/04
CPC分类号： H01L27/0928 , H03K19/00338
摘要： A semiconductor integrated circuit device includes: a plurality of data holding circuits; and a plurality of wells. The plurality of data holding circuits is provided in a substrate of a first conductive type. Each of the plurality of data holding circuits includes a first well of the first conductive type and a second well of a second conductive type different from the first conductive type. The plurality of wells is arranged in two directions for the each of the plurality of data holding circuits.
摘要翻译：一种半导体集成电路装置，包括：多个数据保持电路; 和多个井。多个数据保持电路设置在第一导电类型的衬底中。多个数据保持电路中的每一个包括第一导电类型的第一阱和不同于第一导电类型的第二导电类型的第二阱。对于多个数据保持电路中的每一个，多个阱被布置在两个方向上。

96. 发明申请

US20110073827A1 NANODEVICE ARRAYS FOR ELECTRICAL ENERGY STORAGE, CAPTURE AND MANAGEMENT AND METHOD FOR THEIR FORMATION 有权
标题翻译：用于电力储存，捕获和管理的纳米设备阵列及其形成方法
公开(公告)号：US20110073827A1
公开(公告)日：2011-03-31
申请号：US12869215
申请日：2010-08-26
申请人： Gary W. RUBLOFF , Sang Bok LEE , Israel PEREZ , Laurent LECORDIER , Parag BANERJEE
发明人： Gary W. RUBLOFF , Sang Bok LEE , Israel PEREZ , Laurent LECORDIER , Parag BANERJEE
IPC分类号： H01L27/04 , H01L21/62
CPC分类号： H01G11/86 , B82Y10/00 , B82Y30/00 , H01G11/26 , H01G11/36 , H01L28/60 , H01L29/0665 , H01L29/0676 , H01L29/872 , H01L31/03529 , H01L51/0048 , Y02E10/50 , Y02E60/13
摘要： An apparatus, system, and method are provided for a vertical two-terminal nanotube device configured to capture and generate energy, to store electrical energy, and to integrate these functions with power management circuitry. The vertical nanotube device can include a column disposed in an anodic oxide material extending from a first distal end of the anodic oxide material to a second distal end of the anodic oxide material. Further, the vertical nanotube device can include a first material disposed within the column, a second material disposed within the column, and a third material disposed between the first material and the second material. The first material fills the first distal end of the column and extends to the second distal end of the column along inner walls of the column. The second material fills the first distal end of the column and extends to the second distal end of the column within the first material. Both the first material and the second material are exposed at the first distal end of the column.
摘要翻译：提供了一种用于垂直两端纳米管装置的装置，系统和方法，其被配置为捕获和产生能量，存储电能，并将这些功能与功率管理电路集成。垂直纳米管装置可以包括设置在从阳极氧化物材料的第一远端延伸到阳极氧化物材料的第二远端的阳极氧化物材料中的柱。此外，垂直纳米管装置可以包括设置在柱内的第一材料，设置在柱内的第二材料和设置在第一材料和第二材料之间的第三材料。第一种材料填充柱的第一远端，并沿柱的内壁延伸到柱的第二远端。第二材料填充柱的第一远端并延伸到第一材料内的柱的第二远端。第一材料和第二材料都在柱的第一远端露出。

97. 发明授权

US07863615B2 Display unit and method of manufacturing the same 有权
标题翻译：显示单元及其制造方法
公开(公告)号：US07863615B2
公开(公告)日：2011-01-04
申请号：US12253477
申请日：2008-10-17
申请人： Naoki Hayashi , Atsuya Makita , Yasunobu Hiromasu
发明人： Naoki Hayashi , Atsuya Makita , Yasunobu Hiromasu
IPC分类号： H01L27/04 , H01L21/70
CPC分类号： H01L27/124
摘要： A display unit includes, on an insulating substrate, a plurality of wirings formed to extend in different directions, a thin-film transistor, and a display element. At least one of the plurality of wirings is a divided wiring having a crossing portion formed at an intersection with the other of the plurality of wirings, and a main portion which is formed in a layer same as the other of the plurality of wirings with an insulating film in between and which is electrically connected to the crossing portion via an conductive connection provided in the insulating film. At least one of the main portion and the crossing portion includes a first layer and a second layer stacked in order from the insulating substrate side, the second layer being in direct contact with the first layer and made of a material of a higher melting point than the first layer.
摘要翻译：显示单元在绝缘基板上包括形成为沿不同方向延伸的多个布线，薄膜晶体管和显示元件。所述多个布线中的至少一个是具有与所述多个布线中的另一布线交叉的交叉部分的交叉部分的分割布线，以及与所述多个布线中的另一布线形成为相同的层的主体部，绝缘膜，并且经由设置在绝缘膜中的导电连接电连接到交叉部分。主要部分和交叉部分中的至少一个包括从绝缘基板侧依次层叠的第一层和第二层，第二层与第一层直接接触，并且由比熔点高的材料制成第一层。

98. 发明申请

US20100164058A1 CHIP PACKAGE WITH STACKED INDUCTORS 审中-公开
标题翻译：带堆叠电感的芯片封装
公开(公告)号：US20100164058A1
公开(公告)日：2010-07-01
申请号：US12429870
申请日：2009-04-24
申请人： Jeff BIAR , Jacky Lee
发明人： Jeff BIAR , Jacky Lee
IPC分类号： H01L27/04
CPC分类号： H01L23/3121 , H01L23/645 , H01L24/48 , H01L24/73 , H01L25/16 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2924/00014 , H01L2924/181 , H01L2924/19103 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor chip package with inductors includes a substrate, a semiconductor chip, an inductor and an insulator cover. The substrate has an active surface with a patterned circuit thereon. The inductor disposes on the active surface of the substrate. The semiconductor chip stacks over the inductor and electrically interconnects with the patterned circuit of the substrate and the inductor. The insulator cover encapsulates the inductor and the chip.
摘要翻译：具有电感器的半导体芯片封装包括基板，半导体芯片，电感器和绝缘体盖。衬底具有其上具有图案化电路的有源表面。电感器设置在基板的有源表面上。半导体芯片堆叠在电感器上并与衬底和电感器的图案化电路电互连。绝缘体盖封装电感和芯片。

99. 发明申请

US20100140724A1 EMBEDDED MICROELECTROMECHANICAL SYSTEMS (MEMS) SEMICONDUCTOR SUBSTRATE AND RELATED METHOD OF FORMING 有权
标题翻译：嵌入式微电子系统（MEMS）半导体基板及其相关方法
公开(公告)号：US20100140724A1
公开(公告)日：2010-06-10
申请号：US12331521
申请日：2008-12-10
申请人： Olivier LE NEEL , Peyman Sana , Loi Nguyen , Venkatesh Mohanakrishnaswamy
发明人： Olivier LE NEEL , Peyman Sana , Loi Nguyen , Venkatesh Mohanakrishnaswamy
IPC分类号： H01L27/04 , H01L21/76 , H01L21/36
CPC分类号： B81C1/00246 , B81B2201/0271 , H01L27/0617
摘要： An embedded MEMS semiconductor substrate is set forth and can be a starting material for subsequent semiconductor device processing. A MEMS device is formed in a semiconductor substrate, including at least one MEMS electrode and a buried silicon dioxide sacrificial layer has been applied for releasing the MEMS. A planarizing layer is applied over the substrate, MEMS device and MEMS electrode. A polysilicon protection layer is applied over the planarizing layer. A polysilicon nitride capping layer is applied over the polysilicon protection layer. A polysilicon seed layer is applied over the polysilicon nitride capping layer. The MEMS device is released by removing at least a portion of the buried silicon dioxide sacrificial layer and an epitaxial layer is grown over the polysilicon seed layer to be used for subsequent semiconductor wafer processing.
摘要翻译：介绍了一种嵌入式MEMS半导体衬底，可以作为后续半导体器件处理的起始材料。 MEMS器件形成在包括至少一个MEMS电极的半导体衬底中，并且埋置的二氧化硅牺牲层已被应用于释放MEMS。在衬底，MEMS器件和MEMS电极上施加平坦化层。在平坦化层上施加多晶硅保护层。多晶硅氮化物覆盖层被施加在多晶硅保护层上。多晶硅种子层施加在多晶硅氮化物覆盖层上。通过去除掩埋的二氧化硅牺牲层的至少一部分来释放MEMS器件，并且在多晶硅种子层上生长外延层以用于随后的半导体晶片处理。

100. 发明申请

US20100123170A1 SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME 有权
标题翻译：半导体器件及其形成方法
公开(公告)号：US20100123170A1
公开(公告)日：2010-05-20
申请号：US12621104
申请日：2009-11-18
申请人： Hiroyuki FUJIMOTO
发明人： Hiroyuki FUJIMOTO
IPC分类号： H01L27/04 , H01L21/768 , H01L27/06
CPC分类号： H01L21/823487 , H01L27/10876 , H01L29/41741 , H01L29/456 , H01L29/66666 , H01L29/7827
摘要： A semiconductor device includes a transistor, a conductive pad, and a contact. The conductive pad is electrically connected to the transistor. The conductive pad may include, but is not limited to, a first region and a second region. The contact is electrically connected to the conductive pad. At least a main part of the first region overlaps the transistor in plan view. At least a main part of the second region does not overlap the transistor in plan view. At least a main part of the contact overlaps the second region in plan view. The at least main part of the contact does not overlap the first region in plan view. The at least main part of the contact does not overlap the transistor in plan view.
摘要翻译：半导体器件包括晶体管，导电焊盘和触点。导电焊盘电连接到晶体管。导电焊盘可以包括但不限于第一区域和第二区域。触点电连接到导电焊盘。第一区域的至少主要部分在平面图中与晶体管重叠。第二区域的至少主要部分在平面图中不与晶体管重叠。在平面图中，至少接触的主要部分与第二区域重叠。在平面图中，接触件的至少主要部分不与第一区域重叠。接触的至少主要部分在平面图中不与晶体管重叠。

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