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91. 发明授权

US5488248A Memory integrated circuit 失效
标题翻译：内存集成电路
公开(公告)号：US5488248A
公开(公告)日：1996-01-30
申请号：US446091
申请日：1995-05-19
申请人： Kuo-Hua Lee , Janmye Sung
发明人： Kuo-Hua Lee , Janmye Sung
IPC分类号： H01L21/8244 , H01L27/11 , H01L27/085
CPC分类号： H01L27/1108 , Y10S257/904
摘要： An integrated circuit, illustratively an SRAM, having a low resistance path between an access transistor and a pull down transistor is disclosed. Connection for the cell load to the node between the access transistor and pull down transistor is made outside the defined current path.
摘要翻译：公开了一种在存取晶体管和下拉晶体管之间具有低电阻路径的集成电路，例如SRAM。在存在晶体管和下拉晶体管之间的节点的电池负载的连接在限定的电流路径之外。

92. 发明授权

US5382821A High power field effect transistor 失效
标题翻译：大功率场效应晶体管
公开(公告)号：US5382821A
公开(公告)日：1995-01-17
申请号：US988258
申请日：1992-12-14
申请人： Shigeru Nakajima
发明人： Shigeru Nakajima
IPC分类号： H01L29/423 , H01L27/085 , H01L27/088 , H01L27/105
CPC分类号： H01L29/42316
摘要： There is disclosed an FET having a high drain breakdown voltage and a short gate length comprising an active layer 2 formed on a surface layer of a semiconductor substrate 1; a highly doped impurity source region 4 and highly doped impurity drain region 4 formed in the surface layer of the semiconductor substrate 1 to sandwich the active layer 2; an insulation film 5 formed on the highly doped impurity source region 4; a gate electrode 8 formed on the active layer 2 and the insulation film 5 while maintaining a constant distance 1.sub.GD from the highly doped impurity drain region 4; and a source electrode 6 and a drain electrode 7 formed on the highly doped impurity source region 4 and the highly doped impurity drain region 4, respectively.
摘要翻译：公开了一种具有高漏极击穿电压和短栅极长度的FET，其包括形成在半导体衬底1的表面层上的有源层2; 形成在半导体衬底1的表面层中以夹持有源层2的高掺杂杂质源区4和高掺杂杂质漏极区4; 形成在高掺杂杂质源区4上的绝缘膜5; 形成在有源层2和绝缘膜5上的栅电极8，同时保持与高掺杂杂质漏区4的距离1GD不变; 以及分别形成在高掺杂杂质源极区4和高掺杂杂质漏极区4上的源电极6和漏电极7。

93. 发明授权

US5313082A High voltage MOS transistor with a low on-resistance 失效
标题翻译：具有低导通电阻的高压MOS晶体管
公开(公告)号：US5313082A
公开(公告)日：1994-05-17
申请号：US18080
申请日：1993-02-16
申请人： Klas H. Eklund
发明人： Klas H. Eklund
IPC分类号： H01L27/02 , H01L21/337 , H01L21/8232 , H01L21/8234 , H01L27/06 , H01L27/085 , H01L27/088 , H01L27/095 , H01L29/06 , H01L29/08 , H01L29/78 , H01L29/808 , H01L29/784
CPC分类号： H01L27/085 , H01L29/0634 , H01L29/0847 , H01L29/7835 , H01L29/7832
摘要： An embodiment of the present invention is an improved insulated-gate, field-effect transistor and a three-sided, junction-gate field-effect transistor connected in series on the same chip to form a high-voltage MOS transistor. An extended drain region is formed on top of a substrate of opposite conductivity material. A layer of material with a conductivity opposite to that of the material of the extended drain region is buried within the extended drain region such that field-effect pinch-off depletion zones extend both above and below the buried layer. A top layer of material similar to the substrate is formed by ion implantation through the same mask window as the extended drain region. The top layer covers the buried layer and extended drain region and itself is covered by a silicon dioxide layer above. Current flow through the extended drain is controlled by the substrate and buried layer when a voltage is applied to pinch-off the extended drain between them in a familiar field-effect fashion.
摘要翻译：本发明的一个实施例是一种改进的绝缘栅，场效应晶体管和串联在同一芯片上的三边形结栅场效应晶体管，以形成高压MOS晶体管。延伸的漏极区域形成在相对导电材料的衬底的顶部上。具有导电性与延伸漏极区的材料导电性相反的材料层被掩埋在延伸的漏极区内，使得场效应夹断耗尽区在掩埋层的上方和下方延伸。通过与延伸的漏极区域相同的掩模窗口的离子注入形成与衬底类似的顶层材料。顶层覆盖掩埋层和延伸的漏极区，并且其上面被二氧化硅层覆盖。通过延伸漏极的电流通过衬底和掩埋层进行控制，当施加电压以熟悉的场效应方式将它们之间的扩展漏极夹紧时。

94. 发明授权

US5005059A Digital-to-analog converting field effect device and circuitry 失效
标题翻译：数字到模拟转换场效应器件和电路
公开(公告)号：US5005059A
公开(公告)日：1991-04-02
申请号：US345746
申请日：1989-05-01
申请人： John M. Golio , Joseph Staudinger
发明人： John M. Golio , Joseph Staudinger
IPC分类号： H03M1/36 , H01L21/8234 , H01L27/085 , H01L27/088 , H01L29/78 , H01L29/812 , H03M1/74
CPC分类号： H01L27/085 , H01L29/7831 , H01L29/8124
摘要： A field effect device and circuit suitable for providing an analog output signal having a magnitude which is representative of a digital input code having a sequence of bits. The device includes a plurality of gate electrodes located between an input electrode and an output electrode. The gate electrodes have unequal lengths to provide different gate widths each representative of the magnitude of a portion of an analog signal provided at the output electrode in response to a digital signal of a particular logic state, such as a logical "one", when applied to any one of the gate electrodes. Thus, the magnitude of the current conducted between the input electrode and the output electrode is responsive to the sum of the widths of the gates receiving the digital signal of a particular logic state.
摘要翻译：一种场效应器件和电路，适于提供具有表示具有位序列的数字输入代码的幅度的模拟输出信号。该器件包括位于输入电极和输出电极之间的多个栅电极。栅极电极具有不同的长度以提供不同的栅极宽度，每个栅极宽度表示当施加时响应于特定逻辑状态的数字信号（例如逻辑“1”）在输出电极处提供的模拟信号的一部分的幅度的大小到任意一个栅电极。因此，在输入电极和输出电极之间传导的电流的大小响应于接收特定逻辑状态的数字信号的门的宽度的总和。

95. 发明授权

US4654548A Complementary logic circuit 失效
标题翻译：互补逻辑电路
公开(公告)号：US4654548A
公开(公告)日：1987-03-31
申请号：US627576
申请日：1984-07-03
申请人： Tetsu Tanizawa , Osam Ohba
发明人： Tetsu Tanizawa , Osam Ohba
IPC分类号： H03K17/04 , H01L27/085 , H03K19/094 , H03K19/017
CPC分类号： H03K19/094 , H01L27/085
摘要： A complementary logic circuit which has large power handling capacity, high switching speed and still has low power consumption is disclosed. The circuit of the present invention is composed from a first stage comprising a complementary MIS-FET, and an output stage comprising a complementary vertical FET. The gate of the V-FET is arranged so as to serve as the drain or source of the MIS-FET. In such an arrangement, the steps of fabricating the IC are reduced and the packing density is increased. By varying the connection of positive and negative voltage sources, the circuit can be operated as an inverting or non-inverting logic circuit.
摘要翻译：公开了具有大功率处理能力，高开关速度并且仍然具有低功耗的互补逻辑电路。本发明的电路由包括互补MIS-FET的第一级和包括互补垂直FET的输出级构成。 V-FET的栅极被配置为用作MIS-FET的漏极或源极。在这种布置中，制造IC的步骤减少，堆积密度增加。通过改变正负电压源的连接，该电路可以作为反相或非反相逻辑电路运行。

96. 发明授权

US4435785A Unipolar voltage non-volatile JRAM cell 失效
标题翻译：单极性电压非易失性JRAM单元
公开(公告)号：US4435785A
公开(公告)日：1984-03-06
申请号：US269201
申请日：1981-06-02
申请人： Richard A. Chapman
发明人： Richard A. Chapman
IPC分类号： G11C11/39 , G11C16/04 , H01L27/07 , H01L27/085 , H01L29/808 , G11C11/24 , H01L29/80
CPC分类号： G11C16/0466 , G11C11/39 , H01L27/0733 , H01L27/085 , H01L29/808
摘要： A non-volatile JRAM cell is constructed to require only positive voltage for programming and erasing of data in the cell. The "well" region of the cell JFET device may be implanted with an impurity concentration that will permit lower breakdown voltage or the non-volatile gate may overlap the JFET gate sufficiently to be able to have the same effect, or some combination of both may be used. This allows the cell to be erased using voltages of one polarity.
摘要翻译：构造非易失性JRAM单元仅需要正电压来编程和擦除单元中的数据。可以注入电池JFET器件的“阱”区域，其杂质浓度将允许更低的击穿电压，或者非易失性栅极可以充分地与JFET栅极重叠以能够具有相同的效果，或两者的某种组合使用。这允许使用一个极性的电压擦除电池。

97. 发明授权

US4409725A Method of making semiconductor integrated circuit 失效
标题翻译：制造半导体集成电路的方法
公开(公告)号：US4409725A
公开(公告)日：1983-10-18
申请号：US309428
申请日：1981-10-07
申请人： Tadahiko Hotta , Terumoto Nonaka
发明人： Tadahiko Hotta , Terumoto Nonaka
IPC分类号： H01L21/8238 , H01L21/8249 , H01L27/085 , H01L21/22 , H01L21/306 , H01L29/76
CPC分类号： H01L21/8249 , H01L21/8238 , H01L27/085
摘要： A method of making a semiconductor integrated circuit on a semiconductor substrate containing thereon an SIT and an IG(MOS) FET or an SIT and C-MOS FETs, comprises a series of steps of making these functional semiconductor devices many of which steps are rendered to be common to the SIT and the FET. The gate region of said IG(MOS) FET is formed as a semiconductor gate layer which typically is made of polycrystalline silicon, and an active semiconductor area of said IG(MOS) FET is formed by using this semiconductor gate layer as the mask therefor.
摘要翻译：在其上包含SIT和IG（MOS）FET或SIT和C-MOS FET的半导体衬底上制造半导体集成电路的方法包括使这些功能半导体器件成为许多步骤的一系列步骤对于SIT和FET是常见的。所述IG（MOS）FET的栅极区域形成为通常由多晶硅制成的半导体栅极层，并且通过使用该半导体栅极层作为掩模来形成所述IG（MOS）FET的有源半导体区域。

98. 发明授权

US4403395A Monolithic integration of logic, control and high voltage interface circuitry 失效
公开(公告)号：US4403395A
公开(公告)日：1983-09-13
申请号：US319866
申请日：1981-11-09
申请人： Patrick A. Curran
发明人： Patrick A. Curran
IPC分类号： G05F3/20 , H01L21/761 , H01L21/8248 , H01L21/8249 , H01L27/06 , H01L27/085 , H01L27/088 , H01L27/092 , H03K19/0944 , H01L21/265
CPC分类号： H03K19/09448 , G05F3/20 , H01L21/761 , H01L21/8248 , H01L21/8249 , H01L27/0623 , H01L27/085 , H01L27/088 , H01L27/0922
摘要： Monolithic integration of digital logic circuitry, precision control circuitry, and high voltage interface circuits on the same semiconductor chip is achieved, using various combinations selected from D-MOS, vertical NPN, lateral NPN, PNP, P-MOS, N-MOS, and J-FET components. Cathode driver circuits for a plasma display panel are integrated with this technology. Other applications include automotive and television circuits.

99. 发明授权

US4373253A Integrated CMOS process with JFET 失效
标题翻译：集成CMOS工艺与JFET
公开(公告)号：US4373253A
公开(公告)日：1983-02-15
申请号：US253470
申请日：1981-04-13
申请人： Wadie N. Khadder , Jia-Tarng Wang , James E. Solomon
发明人： Wadie N. Khadder , Jia-Tarng Wang , James E. Solomon
IPC分类号： H01L21/8238 , H01L27/085 , H01L27/092 , H01L29/808 , H01L27/04 , H01L21/22 , H01L21/263
CPC分类号： H01L27/085 , H01L21/8238 , H01L27/0927 , H01L29/808
摘要： A process for fabricating JFET devices into a conventional CMOS monolithic IC. The combination of devices provides linear circuit operation with low noise characteristics.
摘要翻译：将JFET器件制造成传统CMOS单片IC的工艺。器件的组合提供具有低噪声特性的线性电路操作。

100. 发明授权

US4228444A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US4228444A
公开(公告)日：1980-10-14
申请号：US947050
申请日：1978-09-29
申请人： Ryoiku Togei
发明人： Ryoiku Togei
IPC分类号： H01L29/812 , H01L21/338 , H01L27/085 , H01L29/423 , H01L29/45 , H01L29/76 , H01L29/80
CPC分类号： H01L27/085 , H01L29/42312 , H01L29/456 , H01L29/7606
摘要： On a semiconductor substrate (or layer) of one conductivity type, a semiconductor layer of the opposite conductivity type is formed and a source and a drain region of the same conductivity type as the semiconductor substrate are formed in the semiconductor layer. Junctions are respectively formed between the source and drain regions and the semiconductor layer at such positions where punch-through may easily occur between the source and drain regions and the semiconductor substrate when operating voltages are applied to these regions. A local potential distribution generation electrode, which makes an ohmic contact with the semiconductor layer, is formed between the source and drain regions. By applying voltages to both the local potential distribution generation electrode and a drain electrode at substantially the same time, a potential barrier normally formed in the semiconductor layer is removed, thereby to inject carriers from the source region to the drain region through the semiconductor substrate (or layer).
摘要翻译：在一种导电型的半导体衬底（或层）上，形成相反导电型的半导体层，并且在半导体层中形成与半导体衬底相同导电类型的源区和漏区。在源极和漏极区域之间并且在工作电压被施加到这些区域时在这样的位置处可能容易地在源极和漏极区域和半导体衬底之间产生穿通的位置处形成接合区域和半导体层。在源极和漏极区域之间形成与半导体层形成欧姆接触的局部电位分布产生电极。通过同时向局部电位分配产生电极和漏电极施加电压，去除在半导体层中通常形成的势垒，从而通过半导体衬底将载流子从源极区域注入到漏极区域或层）。

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