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11. 发明申请

US20140290983A1 STACKED MULTILAYER STRUCTURE 有权
标题翻译：堆叠多层结构
公开(公告)号：US20140290983A1
公开(公告)日：2014-10-02
申请号：US13853303
申请日：2013-03-29
申请人： KINSUS INTERCONNECT TECHNOLOGY CORP.
发明人： Ting-Hao Lin , Yu-Te Lu , De-Hao Lu
IPC分类号： H05K1/02 , H05K1/09
CPC分类号： H05K3/4647 , H05K1/0366 , H05K3/38
摘要： Disclosed is a stacked multilayer structure, including a first circuit layer having bumps, a plastic film stacked on the first circuit layer to fill up the space among the bumps so as to form a co-plane, and a second circuit layer formed on the co-plane and connected to the first circuit layer. The plastic film includes a glass fiber layer which is embedded and not exposed. The adhesion between plastic film and the second circuit layer is greatly improved because the glass fiber layer of the plastic film filling up the space among the bumps is not deformed and exposed outwards. Therefore, the yield and reliability of the stacked multilayer structure is increased.
摘要翻译：公开了一种堆叠的多层结构，包括具有凸起的第一电路层，堆叠在第一电路层上以填充凸块之间的空间以形成共面的塑料膜，以及形成在共面上的第二电路层平面并连接到第一电路层。该塑料膜包括嵌入并不暴露的玻璃纤维层。由于填充凸块之间的空间的塑料膜的玻璃纤维层不会变形并向外露出，所以塑料膜与第二电路层之间的粘合性大大提高。因此，层叠多层结构的成品率和可靠性提高。

12. 发明申请

US20130224513A1 LAMINATE CIRCUIT BOARD WITH A MULTI-LAYER CIRCUIT STRUCTURE 有权
标题翻译：具有多层电路结构的层压电路板
公开(公告)号：US20130224513A1
公开(公告)日：2013-08-29
申请号：US13663141
申请日：2012-10-29
申请人： KINSUS INTERCONNECT TECHNOLOGY CORP.
发明人： Jun-Chung Hsu , Chi-Ming Lin , Tso-Hung Yeh , Ya-Hsiang Chen
IPC分类号： H05K1/03
CPC分类号： H05K3/28 , H05K3/243 , H05K3/4644 , H05K2201/0347
摘要： A laminate circuit board with a multi-layer circuit structure which includes a substrate, a first circuit metal layer, a second circuit metal layer, a first nanometer plating layer, a second nanometer plating layer and a cover layer is disclosed. The first circuit metal layer is embedded in the substrate or formed on at least one surface of the substrate which is smooth. The first nanometer plating layer with a smooth surface overlaps the first circuit metal layer. The second nanometer plating layer is formed on the other surface of the substrate and fills up the opening in the cover layer to electrically connect the first circuit metal layer. The junction adhesion is improved by the chemical bonding between the nanometer plating layer and the cover layer/the substrate. Therefore, the circuit metal layer does not need to be roughened and the density of the circuit increases.
摘要翻译：公开了一种具有多层电路结构的叠层电路板，其包括基板，第一电路金属层，第二电路金属层，第一纳米镀层，第二纳米镀层和覆盖层。第一电路金属层嵌入衬底中或形成在衬底的平滑的至少一个表面上。具有平滑表面的第一纳米镀层与第一电路金属层重叠。第二纳米镀层形成在基板的另一个表面上，并填满覆盖层中的开口以电连接第一电路金属层。通过纳米电镀层和覆盖层/基板之间的化学键合来改善连接粘附。因此，电路金属层不需要粗糙化，电路密度增加。

13. 发明授权

US08083954B2 Method for fabricating component-embedded printed circuit board 有权
标题翻译：组件嵌入式印刷电路板的制造方法
公开(公告)号：US08083954B2
公开(公告)日：2011-12-27
申请号：US12131932
申请日：2008-06-03
申请人： Chien-Wei Chang , Ting-Hao Lin , Yu-Te Lu
发明人： Chien-Wei Chang , Ting-Hao Lin , Yu-Te Lu
IPC分类号： H01B13/00
CPC分类号： B32B37/226 , B32B38/06 , B32B2305/342 , B32B2457/08 , H01L24/24 , H01L24/82 , H01L2224/04105 , H01L2224/32245 , H01L2224/73267 , H01L2224/8203 , H01L2224/83005 , H01L2224/83132 , H05K1/023 , H05K1/185 , H05K1/188 , H05K3/025 , H05K2201/0355 , H05K2201/10636 , H05K2203/063 , Y02P70/611
摘要： A method for fabricating a component-embedded PCB includes: providing a carrier plate having a plating metal layer plated thereon; disposing an electronic component on the plating metal layer of the carrier plate; laminating a metal layer onto the plating metal layer having the electronic component disposed thereon and the carrier plate by a dielectric film; removing the carrier plate and exposing the plating metal layer; and patterning at least one of the metal layer and the plating metal layer to be a circuit layer.
摘要翻译：一种用于制造部件嵌入式PCB的方法包括：提供其上镀有电镀金属层的载体板; 将电子部件设置在载体板的电镀金属层上; 通过电介质膜将金属层层叠在其上设置有电子部件的电镀金属层和载体板上; 移除载体板并暴露电镀金属层; 并且将金属层和电镀金属层中的至少一个图案化为电路层。

14. 发明授权

US07875809B2 Method of fabricating board having high density core layer and structure thereof 有权
标题翻译：具有高密度芯层的板的制造方法及其结构
公开(公告)号：US07875809B2
公开(公告)日：2011-01-25
申请号：US11766194
申请日：2007-06-21
申请人： Chien-Wei Chang , Ting-Hao Lin , Jen-Fang Chang , Yu-Te Lu , Chia-Chi Lo
发明人： Chien-Wei Chang , Ting-Hao Lin , Jen-Fang Chang , Yu-Te Lu , Chia-Chi Lo
IPC分类号： H05K1/00
CPC分类号： H05K3/4602 , H05K3/108 , H05K3/427 , H05K2201/0347 , H05K2201/09536 , H05K2201/0959 , Y10T29/49124 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , Y10T29/49165
摘要： A circuit board includes a core layer substrate having a plated through hole filled with a dielectric material. The plated through hole has a sidewall coated with an inner electroless copper layer, and an electroplated metal layer plated on the inner electroless copper layer before the plated through hole is filled with the dielectric material. The outer portion of the filled plated through hole is thicker than the center portion and tapered toward the center portion to form a depressed surface on the filled plated through hole. The core layer substrate is covered with a patterned electroless copper layer and a patterned electroplated copper layer that connect with the inner electroless copper layer and electroplated metal layer of the plated through hole. The patterned electroplated copper layer forms a flat copper pad above the plated through hole.
摘要翻译：电路板包括具有填充有介电材料的电镀通孔的芯层基板。电镀通孔具有涂覆有内部化学镀铜层的侧壁和在电镀通孔填充有电介质材料之前镀在内部化学镀铜层上的电镀金属层。填充电镀通孔的外部比中心部分厚，并且朝向中心部分逐渐变细，以在填充的电镀通孔上形成凹陷表面。芯层衬底被覆有图案化的无电铜层和与电镀通孔的内部化学镀铜层和电镀金属层连接的图案化电镀铜层。图案化的电镀铜层在电镀通孔上方形成平坦的铜焊盘。

15. 发明授权

US07353591B2 Method of manufacturing coreless substrate 有权
标题翻译：无芯基板的制造方法
公开(公告)号：US07353591B2
公开(公告)日：2008-04-08
申请号：US11379059
申请日：2006-04-18
申请人： Tso-Hung Yeh
发明人： Tso-Hung Yeh
IPC分类号： H05K3/36
CPC分类号： H05K3/0097 , H01L21/4857 , H01L23/49822 , H01L2924/0002 , H05K3/0052 , H05K3/025 , H05K3/4644 , H05K2203/0169 , H05K2203/0228 , H05K2203/1536 , Y10T29/49124 , Y10T29/49126 , Y10T29/49128 , Y10T29/49155 , H01L2924/00
摘要： A method for manufacturing coreless substrates is provided herein. The method first provides a base whose top and bottom sides are covered with metal layers respectively that are detachable from the base. From the two metal layers, the method then develops the bump-pad side or ball side wiring layers required by the coreless substrate simultaneously. The two metal layers along with their respective wiring layers are then separated from the base into two independent semi-products of the coreless substrate. The method then develops from the other sides of the two semi-products the laminate side wiring layers required by the coreless substrate.
摘要翻译：本发明提供一种无芯基板的制造方法。该方法首先提供了一个基部，其底面和底面分别由与基座分离的金属层覆盖。从两个金属层开始，该方法同时开发无芯基板所需的凸块焊盘侧或球侧布线层。然后将两个金属层及其各自的布线层从基底分离成无芯基板的两个独立的半成品。然后，该方法从两个半成品的另一侧发展成无芯基板所需的层压板侧布线层。

16. 发明授权

US11495390B2 Buildup board structure 有权
公开(公告)号：US11495390B2
公开(公告)日：2022-11-08
申请号：US16285138
申请日：2019-02-25
申请人： KINSUS INTERCONNECT TECHNOLOGY CORP.
发明人： Ting-Hao Lin , Chiao-Cheng Chang , Yi-Nong Lin
IPC分类号： H01F27/28 , H05K1/03 , H05K1/11 , H05K1/16 , H05K3/46
摘要： A buildup board structure incorporating magnetic induction coils and flexible boards is disclosed. The buildup board structure includes at least one first buildup unit or at least one second buildup unit. The first buildup unit includes at least one first buildup body, the second buildup unit includes at least one second buildup body. Any two adjacent buildup bodies are separated by a covering layer provided with a central hole for electrical insulation. All central holes are aligned. Each buildup body includes a plurality of flexible boards, and each flexible board is embedded with a plurality of magnetic induction coils surrounding the corresponding central hole and connected through connection pads. The first and/or second buildup bodies are easily laminated in any order by any number as desired such that the effect of magnetic induction provided by the magnetic induction coils embedded in the buildup board structure are addable to greatly enhance the overall effect of magnetic induction.

17. 发明授权

US10882296B2 Film-peeling apparatus 有权
公开(公告)号：US10882296B2
公开(公告)日：2021-01-05
申请号：US16199565
申请日：2018-11-26
申请人： KINSUS INTERCONNECT TECHNOLOGY CORP.
发明人： Shang-Chi Wang , Yun-Han Yeh , Cyuan-Bang Wu
IPC分类号： B32B43/00 , B32B38/10 , B65H41/00 , H05K3/00
摘要： A film-peeling apparatus is adapted to peel a protective film on a surface of a substrate. The surface of the substrate has a bare area which is not covered by the protective film. The film-peeling apparatus includes a punching member, a connector connected to the punching member, and a controller. The controller is configured for driving, through the connector, the punching member to punch at predetermined positions nearby or on a first edge of the protective film adjacent to the bare area.

18. 发明授权

US10405423B2 Multi-layer circuit board 有权
公开(公告)号：US10405423B2
公开(公告)日：2019-09-03
申请号：US15863605
申请日：2018-01-05
申请人： KINSUS INTERCONNECT TECHNOLOGY CORP.
发明人： Ting-Hao Lin , Chiao-Cheng Chang , Yi-Nong Lin
IPC分类号： H05K1/02 , H05K1/09 , H05K1/14 , H05K3/46
摘要： A multi-layer circuit board includes a first circuit board, conducting blocks, a second circuit board, and conducting recesses. The first circuit board has a first conductor layer mounted on the first circuit board. The conducting blocks are mounted on the first circuit board and electrically connected to the first conductor layer. The second circuit board has a second conductor layer mounted thereon and facing the first circuit board. The conducting recesses are formed in the second circuit board, electrically connected to the second conductor layer, and corresponding to the respective conducting blocks. The insulating layer is mounted between the first conductor layer and the second conductor layer. The second circuit board is on the first circuit board, the conducting blocks are respectively mounted in the conducting recesses to electrically connect the first conductor layer and the second conductor layer.

19. 发明授权

US10371719B2 Printed circuit board circuit test fixture with adjustable density of test probes mounted thereon 有权
公开(公告)号：US10371719B2
公开(公告)日：2019-08-06
申请号：US15130982
申请日：2016-04-17
申请人： KINSUS INTERCONNECT TECHNOLOGY CORP.
发明人： Ting-Hao Lin , Chiao-Cheng Chang , Yi-Nong Lin
IPC分类号： G01R1/073 , G01R31/28
摘要： A printed circuit board (PCB) test fixture includes a substrate, a first insulation layer formed on the substrate, a conductor layer formed on the first insulation layer and electrically connected to the upper electrodes through at least one first connection member, a second insulation layer formed on the first insulation layer, and multiple conductive cones arranged on the second insulation layer in a matrix form. A part of the conductive cones is electrically connected to the conductor layer through at least one second connection member. The circuit layout of the conductor layer, the at least one first connection member and the at least one second connection member is employed to supply testing power to a part of the conductive cones and an adjustable arrangement of the conductive cones to enhance density of test probes upon electrical testing.

20. 发明申请

US20180160533A1 MULTILAYER PRINTED CIRCUIT BOARD 审中-公开
公开(公告)号：US20180160533A1
公开(公告)日：2018-06-07
申请号：US15369822
申请日：2016-12-05
申请人： KINSUS INTERCONNECT TECHNOLOGY CORP.
发明人： Ting-Hao LIN , Chiao-Cheng CHANG , Yi-Nong LIN
IPC分类号： H05K1/14 , H05K1/02 , H05K3/36 , H05K3/46
CPC分类号： H05K3/4641 , H05K3/4647 , H05K3/4682 , H05K2201/10242 , H05K2203/041 , H05K2203/0568
摘要： A multilayer printed circuit board includes a first circuit board, a second circuit board and bonding films. The first circuit board includes a first dielectric layer, a first wiring pattern layer, a plurality of conductive blocks and a plurality of solder balls. The first wiring pattern layer is formed on a first surface of the first dielectric layer and the conductive blocks are formed on a second surface of the first dielectric layer. The solder balls are formed on a surface of the first wiring pattern layer. The second circuit board includes a second dielectric layer, a second wiring pattern layer, second conductive blocks and conductive pillars. The second wiring pattern layer is formed on a third surface of the second dielectric layer and the second conductive blocks are formed on a fourth surface thereof. The conductive pillars are formed on the second wiring pattern layer.

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