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11. 发明授权

US10826840B1 Multiple copies of stateful tables 有权
公开(公告)号：US10826840B1
公开(公告)日：2020-11-03
申请号：US15835242
申请日：2017-12-07
申请人： Barefoot Networks, Inc.
发明人： Jay Evan Scott Peterson , Michael Gregory Ferrara , Anurag Agrawal , Patrick Bosshart , Jeongkeun Lee
IPC分类号： H04L12/863 , H04L12/741 , H04L12/935
摘要： Some embodiments provide a method for a packet processing pipeline of a network forwarding integrated circuit. The method stores two copies of a stateful table used by the packet processing pipeline. The stateful table is modified according to data processed by the packet processing pipeline. Upon receiving data to write to the stateful table, the method generates (i) a first copy of the received data along with an indicator for a first one of the copies of the stateful table and (ii) a second copy of the received data along with an indicator for a second one of the copies of the stateful table. The method sends the first copy of the received data into the packet processing pipeline before sending the second copy of the received data into the packet processing pipeline.

12. 发明申请

US20200344138A1 FORWARDING ELEMENT DATA PLANE WITH FLOW SIZE DETECTOR 审中-公开
公开(公告)号：US20200344138A1
公开(公告)日：2020-10-29
申请号：US16870785
申请日：2020-05-08
申请人： Barefoot Networks, Inc.
发明人： Georgios NIKOLAIDIS , Jeongkeun LEE , Masoud Moshref JAVADI
IPC分类号： H04L12/26 , H04L12/823 , H04L12/24 , H04L12/761 , H04L12/721 , H04L12/715 , H04L12/743 , H04L12/801 , H04L12/851 , H04L12/935 , H04L12/861
摘要： Some embodiments of the invention provide a data-plane forwarding circuit (data plane) that has a flow-size detection circuit that generates flow-size density distribution for all or some of the data message flows that it processes for forwarding in a network. The flow-size (FS) detection circuit in some embodiments generates statistical values regarding the processed data message flows, and based on these statistical values, it generates a FS density distribution that expresses a number of flows in different flow-size sub-ranges in a range of flow sizes. In some embodiments, the density distribution is a probabilistic density distribution that is based on probabilistic statistical values that the flow-size detection circuit generates for the data message flows that are processed for forwarding within the network. The FS detection circuit in some embodiments generates probabilistic statistical values for the data message flows by generating hash values from header values of the data message flows and accumulating flow-size values at memory locations identified by the generated hash values. In some embodiments, the generated hashes for different data message flows can collide, which results in the accumulated flow-size values being probabilistic values that might have a certain level of inaccuracy.

13. 发明申请

US20200344122A1 DYNAMICALLY RECONFIGURING DATA PLANE OF FORWARDING ELEMENT TO ACCOUNT FOR OPERATING TEMPERATURE 审中-公开
公开(公告)号：US20200344122A1
公开(公告)日：2020-10-29
申请号：US16870680
申请日：2020-05-08
申请人： Barefoot Networks, Inc.
发明人： Remy CHANG
IPC分类号： H04L12/24 , G06F1/3234 , G06F1/04 , H04L12/741 , H04L12/947 , H04L12/935 , H04L12/721 , G06F1/20 , G06F1/32
摘要： Some embodiments of the invention provide a network forwarding element that can be dynamically reconfigured to adjust its data message processing to stay within a desired operating temperature or power consumption range. In some embodiments, the network forwarding element includes (1) a data-plane forwarding circuit (“data plane”) to process data tuples associated with data messages received by the IC, and (2) a control-plane circuit (“control plane”) for configuring the data plane forwarding circuit. The data plane includes several data processing stages to process the data tuples. The data plane also includes an idle-signal injecting circuit that receives from the control plane configuration data that the control plane generates based on the IC's temperature. Based on the received configuration data, the idle-signal injecting circuit generates idle control signals for the data processing stages. Each stage that receives an idle control signal enters an idle state during which the majority of the components of that stage do not perform any operations, which reduces the power consumed and temperature generated by that stage during its idle state.

14. 发明申请

US20200313999A1 NETWORK TESTING USING A PROGRAMMABLE PACKET ENGINE 审中-公开
公开(公告)号：US20200313999A1
公开(公告)日：2020-10-01
申请号：US16833227
申请日：2020-03-27
申请人： Barefoot Networks, Inc.
发明人： Jeongkeun LEE , Georgios NIKOLAIDIS , Andre LAM , Remy CHANG , Joon-Myung KANG , Ashkan NIKRAVESH , Ramkumar KRISHNAMOORTHY , Alain LOGE
IPC分类号： H04L12/26 , H04L29/06
摘要： Embodiments described herein describe a network tester that is configured to perform packet modification at an egress pipeline of a programmable packet engine. A packet stream is received at an egress pipeline of an output port of the programmable packet engine, wherein the output port includes a packet modifier. Packets of the packet stream are modified at the packet modifier. The packet stream including modified packets is transmitted through an egress pipeline of the output port.

15. 发明授权

US10785342B1 Storing packet data in mirror buffer 有权
公开(公告)号：US10785342B1
公开(公告)日：2020-09-22
申请号：US16289001
申请日：2019-02-28
申请人： Barefoot Networks, Inc.
发明人： Parag D. Bhide , Alain Loge , Chaitanya Kodeboyina , Anurag Agrawal
IPC分类号： H04L29/08 , H04L29/06
摘要： Some embodiments provide a method for a hardware forwarding element. Based on a set of characteristics of a packet, the method determines to copy a packet to a particular temporary storage of a set of temporary storages of the hardware forwarding element. Based on a property of the particular temporary storage, the method stores only a particular portion of the packet in the particular temporary storage. A same size portion of each packet copied to the particular temporary storage is stored in the particular temporary storage.

16. 发明授权

US10778583B2 Chained longest prefix matching in programmable switch 有权
公开(公告)号：US10778583B2
公开(公告)日：2020-09-15
申请号：US15927663
申请日：2018-03-21
申请人： Barefoot Networks, Inc.
发明人： Milad Sharif
IPC分类号： H04L12/745 , H04L12/743 , H04L12/753 , H04L29/06 , H04L12/851 , H04L12/741 , H04L12/755
摘要： Some embodiments provide a method for configuring unit memories (e.g., unit static random access memories (SRAMs) and ternary content addressable memories (TCAMs) of a network forwarding IC to implement a set of longest prefix matching (LPM) tables. Two different methods of providing a longest prefix match (LPM) operation that minimize the use of ternary content addressable memory (TCAM) are presented. Each method takes advantage of the use of match-action stages and the programmability of the unit memories. An algorithmic LPM embodiment is presented which uses a TCAM index with pointers to SRAM partitions that store subtrees of a routing tree (routing trie structure) and performs subtree rearrangements in the partitions upon the addition of certain routing entries. A chained LPM embodiment, allocates separate exact-match tables for a set of address prefix lengths in, for example, SRAMS, as well as a set of non-exact match tables in, for example, TCAMs.

17. 发明授权

US10757005B2 Execution of packet-specified actions at forwarding element 有权
公开(公告)号：US10757005B2
公开(公告)日：2020-08-25
申请号：US15948992
申请日：2018-04-09
申请人： Barefoot Networks, Inc.
发明人： Changhoon Kim , Jeongkeun Lee , Milad Sharif , Robert Soule
IPC分类号： H04L12/751 , H04L12/721 , H04L12/24 , H04L12/741 , H04L12/26 , H04L29/06 , H04L12/773 , H04L9/06
摘要： Some embodiments provide a method for a particular forwarding element (FE) in a network of FEs. The method receives a packet at the particular FE. The packet includes a packet header that includes, for each of multiple FEs along a path from a source of the packet to a destination of the packet, (i) an identifier for the FE and (ii) a set of one or more actions for the FE to perform on the packet. The method parses the packet header to identify the set of actions for the particular FE. The method performs the identified set of actions.

18. 发明申请

US20200265002A1 FORWARDING ELEMENT INTEGRATED CIRCUIT CHIP WITH SEPARATE I/O AND SWITCHING TILES 审中-公开
公开(公告)号：US20200265002A1
公开(公告)日：2020-08-20
申请号：US16796828
申请日：2020-02-20
申请人： Barefoot Networks, Inc.
发明人： Anurag AGRAWAL , Alain LOGE
IPC分类号： G06F13/40 , H03K17/81
摘要： Some embodiments of the invention provide a novel method and chip design for a forwarding chip, that decouples input-output (IO) technology requirements from the technology used in a high bandwidth switching ASIC. In some embodiments, a main die including a latest generation switching chip is coupled to a set of IO dies (e.g., SerDes dies). The main die, in some embodiments, uses a latest technology (e.g., 7 nm nodes) while the IO dies, in some embodiments, use a more mature technology (e.g., 16 nm nodes). Some embodiments provide multiple IO dies that each provide connectivity to external components to the high bandwidth switching ASIC (e.g., a core ASIC die). The multiple dies are mounted on a silicon interposer, in some embodiments, using microbumps to make the connections between the dies and the silicon interposer. Additional connections to the pad are made from each die including to general purpose input-output (GPIO) connections. In some embodiments, the main die and the IO dies make all connections through microbumps on the silicon interposer and some microbumps connect to external components using through-silicon vias (TSVs). The microbumps of the main die, in some embodiments, are arranged so that they are mirrored on either side of the main die and rotationally invariant under a 180 degree rotation. IO dies, in some embodiments, are mounted in a first orientation to connect to a first side of the main die and a second rotated (by 180 degrees) orientation to connect to a second opposite side of the main die.

19. 发明授权

US10721188B2 Forwarding element data plane with computing parameter distributor 有权
公开(公告)号：US10721188B2
公开(公告)日：2020-07-21
申请号：US16147750
申请日：2018-09-30
申请人： Barefoot Networks, Inc.
发明人： Masoud Moshref Javadi , Changhoon Kim , Patrick W. Bosshart , Anurag Agrawal
IPC分类号： H04L12/935 , G06F9/455 , G06N3/08
摘要： Some embodiments provide a network forwarding element with a data-plane forwarding circuit that has a parameter collecting circuit to store and distribute parameter values computed by several machines in a network. In some embodiments, the machines perform distributed computing operations, and the parameter values that compute are parameter values associated with the distributed computing operations. The parameter collecting circuit of the data-plane forwarding circuit (data plane) in some embodiments (1) stores a set of parameter values computed and sent by a first set of machines, and (2) distributes the collected parameter values to a second set of machines once it has collected the set of parameter values from all the machines in the first set. The first and second sets of machines are the same set of machines in some embodiments, while they are different sets of machines (e.g., one set has at least one machine that is not in the other set) in other embodiments. In some embodiments, the parameter collecting circuit performs computations on the parameter values that it collects and distributes the result of the computations once it has processed all the parameter values distributed by the first set of machines. The computations are aggregating operations (e.g., adding, averaging, etc.) that combine corresponding subset of parameter values distributed by the first set of machines.

20. 发明授权

US10686658B1 Incremental update of the data plane of a hardware forwarding element 有权
公开(公告)号：US10686658B1
公开(公告)日：2020-06-16
申请号：US16219921
申请日：2018-12-13
申请人： Barefoot Networks, Inc.
发明人： Gregory C. Watson , Julianne Zhu , Ravindra Sunkad , Steven Licking , Sachin Bahadur
IPC分类号： H04L12/28 , H04L12/24 , G06F13/42 , H04L12/861 , G06F13/28 , G06F13/16 , H04L12/741
摘要： A method of incremental updating of a network forwarding element that includes (i) a set of data plane circuits with a set of ingress buffers and a group of configurable packet processing stages and (ii) a set of control plane circuits comprising a set of direct memory access (DMA) buffers. Configuration data for reconfiguring the data plane packet processing stages is loaded into the DMA buffers while the packet processing stages are processing the packets. The ingress buffers are configured to (i) pause sending the packets to the processing stages and (ii) continue storing the incoming packets while sending the data plane packets to the processing stages is paused. The configuration data is loaded from the DMA buffers into the packet processing stages. The ingress buffers are configured to resume sending the data packet plane packets to the packet processing stages.

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