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11. 发明申请

US20080073056A1 Air conditioner for vehicle 有权
标题翻译：汽车空调
公开(公告)号：US20080073056A1
公开(公告)日：2008-03-27
申请号：US11903751
申请日：2007-09-24
申请人： Hiroshi Takeda , Yasufumi Kojima , Hiroyuki Tomita
发明人： Hiroshi Takeda , Yasufumi Kojima , Hiroyuki Tomita
IPC分类号： B60H3/00
CPC分类号： B60H1/00735 , B60H1/00828
摘要： In an air amount control for controlling an air amount to be blown into a vehicle compartment, a water temperature control map in which the air amount is set based on a water temperature of cooling water for the vehicle is stored, and the air amount is determined based on control characteristics of the water temperature control map. The water temperature control map is learned and changed based on a set air amount, and the air amount to be blown into the vehicle compartment is determined based on the learned water temperature control map in a case where the set air amount is changed by a passenger and the water temperature is in a predetermined range.
摘要翻译：在用于控制吹入车厢的空气量的空气量控制中，存储基于车辆的冷却水的水温设定空气量的水温控制图，并且确定空气量基于水温控制图的控制特性。基于设定的空气量来学习和改变水温控制图，并且在乘客改变设定空气量的情况下，基于学习水温控制图来确定要吹入车厢的空气量水温处于预定范围内。

12. 发明申请

US20060125747A1 Display device and automatic synchronization judging circuit 审中-公开
标题翻译：显示设备和自动同步判断电路
公开(公告)号：US20060125747A1
公开(公告)日：2006-06-15
申请号：US11297449
申请日：2005-12-09
申请人： Hiroshi Takeda , Youji Hirano
发明人： Hiroshi Takeda , Youji Hirano
IPC分类号： G09G3/36 , G09G5/00
CPC分类号： G09G5/008 , G09G5/006 , G09G2310/06 , G09G2340/0407
摘要： An automatic synchronization judging circuit to be used in a liquid crystal display device is provided which is capable of realizing, by a small-scale circuit, a function of correctly judging a synchronizing signal to serve as a reference signal for displaying operations in any case of combinations of synchronizing signals to be input. The automatic synchronization judging circuit includes a counter and a judging device. The counter, when having counted a DE (Data Enable) signal up to a predetermined number being 1 or more, makes a signal output from the counter go high and stops the counting. The judging device generates a judging signal. If the judging signal is high, the driving mode is judged as a “fixed mode” which uses a vertical synchronizing signal and a horizontal synchronizing signal as the reference signal. If the judging signal is low, the driving mode is judged as a “DE mode” which uses the DE (Data Enable) signal as the reference signal.
摘要翻译：提供了一种在液晶显示装置中使用的自动同步判断电路，其能够通过小规模电路实现正确判断同步信号作为参考信号的功能，用于在任何情况下要输入的同步信号的组合。自动同步判断电路包括计数器和判断装置。当计数达到预定数量为1或更大的DE（数据使能）信号时，计数器使得从计数器输出的信号变高并停止计数。判断装置产生判断信号。如果判断信号为高，则将驱动模式判断为使用垂直同步信号和水平同步信号作为参考信号的“固定模式”。如果判断信号为低，则将驱动模式判定为使用DE（数据使能）信号作为参考信号的“DE模式”。

13. 发明申请

US20060077202A1 Mode-selecting apparatus, display apparatus including the same, and method of selecting a mode in display unit 有权
标题翻译：模式选择装置，包括该模式选择装置的显示装置以及在显示单元中选择模式的方法
公开(公告)号：US20060077202A1
公开(公告)日：2006-04-13
申请号：US11247238
申请日：2005-10-12
申请人： Hiroshi Takeda
发明人： Hiroshi Takeda
IPC分类号： G09G5/00
CPC分类号： G09G3/2096 , G09G3/2092 , G09G5/18
摘要： A mode-selecting apparatus for selecting one of a first mode in which images are displayed on a display unit in accordance with a vertical synchronization control signal and a horizontal synchronization control signal, and a second mode in which images are displayed on the display unit in accordance with a data-enable signal, includes a first unit which counts a number of input horizontal synchronization control signals in each of frame periods, a second unit which counts a number of input data-enable signals in each of frame periods, and a third unit which selects one of the first and second modes in accordance with both the number of input horizontal synchronization control signals and the number of input data-enable signals.
摘要翻译：一种模式选择装置，用于根据垂直同步控制信号和水平同步控制信号选择图像在显示单元上显示的第一模式中的一种模式，以及第二模式，其中在显示单元上显示图像根据数据使能信号，包括对每个帧周期中的输入水平同步控制信号的数量进行计数的第一单元，对每个帧周期内的输入数据使能信号数进行计数的第二单元，以及第三单元单元，其根据输入的水平同步控制信号的数量和输入数据使能信号的数量来选择第一和第二模式之一。

14. 发明授权

US06643720B2 Data transfer control method, and peripheral circuit, data processor and data processing system for the method 失效
公开(公告)号：US06643720B2
公开(公告)日：2003-11-04
申请号：US10211297
申请日：2002-08-05
申请人： Hiroshi Takeda
发明人： Hiroshi Takeda
IPC分类号： G06F1300
CPC分类号： G11C7/1027 , G06F13/1689 , G11C7/22
摘要： A memory 1 performs its internal operation in response to access requests (200, 201 and 202) of a CPU 2 in synchronism with the oscillated output of a self-excited oscillator 102 incorporated therein and according to said access requests, and outputs a response request 103 for said access requests to said CPU in synchronism with its internal operation. The CPU performs the access requests for the memory, and fetches data from the outside or outputs the data to the outside in response to and in synchronism with the response request 103 from the accessed memory and according to the kinds of said access requests.

15. 发明授权

US06598099B2 Data transfer control method, and peripheral circuit, data processor and data processing system for the method 失效
公开(公告)号：US06598099B2
公开(公告)日：2003-07-22
申请号：US10211263
申请日：2002-08-05
申请人： Hiroshi Takeda
发明人： Hiroshi Takeda
IPC分类号： G06F1300
CPC分类号： G11C7/1027 , G06F13/1689 , G11C7/22
摘要： A memory 1 performs its internal operation in response to access requests (200, 201 and 202) of a CPU 2 in synchronism with the oscillated output of a self-excited oscillator 102 incorporated therein and according to said access requests, and outputs a response request 103 for said access requests to said CPU in synchronism with its internal operation. The CPU performs the access requests for the memory, and fetches data from the outside or outputs the data to the outside in response to and in synchronism with the response request 103 from the accessed memory and according to the kinds of said access requests.

16. 发明授权

US06538653B1 Graphic processing system for displaying characters and pictures at high speed 失效
公开(公告)号：US06538653B1
公开(公告)日：2003-03-25
申请号：US08625241
申请日：1996-04-01
申请人： Koyo Katsura , Shigeru Matsuo , Shigeaki Yoshida , Hiroshi Takeda , Hisashi Kaziwara
发明人： Koyo Katsura , Shigeru Matsuo , Shigeaki Yoshida , Hiroshi Takeda , Hisashi Kaziwara
IPC分类号： G06T340
CPC分类号： G09G5/393 , G09G5/22 , G09G5/26 , G09G5/363
摘要： A graphic processing system has a processor for managing a display area and a character font area both included within an address space. From coded information indicative of a character transferred through a data bus of the system, the processor generates an address at which a character font pattern of the corresponding character has been stored and transfers that character font pattern to a predetermined position on the display area. The graphic processing system realizes high speed development of fonts.

17. 发明授权

US06518235B1 Methods for improving brain function using leptin or analogs thereof 失效
标题翻译：使用瘦素或其类似物改善脑功能的方法
公开(公告)号：US06518235B1
公开(公告)日：2003-02-11
申请号：US09200919
申请日：1998-11-30
申请人： Yutaka Oomura , Nobuaki Hori , Takemasa Shiraishi , Kazuo Sasaki , Hiroshi Takeda , Minoru Tsuji , Teruhiko Matsumiya
发明人： Yutaka Oomura , Nobuaki Hori , Takemasa Shiraishi , Kazuo Sasaki , Hiroshi Takeda , Minoru Tsuji , Teruhiko Matsumiya
IPC分类号： A01N3718
CPC分类号： C07K14/5759 , A61K38/2264
摘要： The present invention is to provide a drug for improvement of brain function which is effective to prevent from or to cure dementia such as Alzheimer's disease. The drug for improvement of brain function of this invention comprises leptin of mammals as an effective component wherefore has a superior effect in improvement of learning and memory.
摘要翻译：本发明提供一种改善脑功能的药物，其有效地防止或治愈诸如阿尔茨海默病的痴呆症。用于改善本发明的脑功能的药物包括哺乳动物的瘦素作为有效成分，因此在改善学习和记忆方面具有优异的效果。

18. 发明授权

US06247073B1 Memory outputting both data and timing signal with output data and timing signal being aligned with each other 有权
标题翻译：存储器输出数据和定时信号，输出数据和定时信号彼此对准
公开(公告)号：US06247073B1
公开(公告)日：2001-06-12
申请号：US09400999
申请日：1999-09-21
申请人： Hiroshi Takeda
发明人： Hiroshi Takeda
IPC分类号： G06F1200
CPC分类号： G11C7/1027 , G06F13/1689 , G11C7/22
摘要： A memory 1 performs its internal operation in response to access requests (200, 201 and 202) of a CPU 2 in synchronism with the oscillated output of a self-excited oscillator 102 incorporated therein and according to said access requests, and outputs a response request 103 for said access requests to said CPU in synchronism with its internal operation. The CPU performs the access requests for the memory, and fetches data from the outside or outputs the data to the outside in response to and in synchronism with the response request 103 from the accessed memory and according to the kinds of said access requests.
摘要翻译：存储器1响应于CPU 2的接收请求（200,201和202）与其中并入的自激振荡器102的振荡输出同步并且根据所述访问请求执行其内部操作，并且输出响应请求 103，用于与其内部操作同步地对所述CPU的所述访问请求。 CPU执行对存储器的访问请求，并且从外部获取数据或者响应于来自所访问的存储器的响应请求103并根据所述访问请求的种类而将数据输出到外部。

19. 发明授权

US5610622A Display control device 失效
标题翻译：显示控制装置
公开(公告)号：US5610622A
公开(公告)日：1997-03-11
申请号：US309413
申请日：1994-09-20
申请人： Hiroshi Takeda , Shigeaki Yoshida , Koyo Katsura
发明人： Hiroshi Takeda , Shigeaki Yoshida , Koyo Katsura
IPC分类号： G09G5/18 , G09G5/12 , G09G1/08
CPC分类号： G09G5/12
摘要： A CRT (cathode ray tube) controller for controlling one CRT device in an interlace mode has a synchronizing circuit of bi-directional construction, in order to make possible synchronous operation of the CRT controller with other circuits (other CRT controllers or a TV system). When the CRTC is used as a master circuit of a CRT display system, a synchronizing signal is derived from the synchronizing circuit in synchronization on with a count signal of a vertical scanning counter and an output of an interlace controller of the CRTC, and is supplied to a synchronizing terminal of the other CRTCs. Scanning counters and a flip-flop for controlling an interlace operation of the other CRTCs are reset to their initial state in synchronization with the synchronizing signal. When the CRTC is used as a slave circuit, scanning counters and a flip-flop of the CRTC are reset to their initial state in synchronization with the external synchronizing signal.
摘要翻译：用于以隔行模式控制一个CRT器件的CRT（阴极射线管）控制器具有双向结构的同步电路，以便使CRT控制器与其他电路（其它CRT控制器或TV系统）可以同步操作，。当CRTC用作CRT显示系统的主电路时，根据垂直扫描计数器的计数信号和CRTC的隔行控制器的输出，同步信号从同步电路得到，并被提供到其他CRTC的同步终端。用于控制其他CRTC的隔行扫描的扫描计数器和触发器与同步信号同步地被复位到其初始状态。当CRTC用作从电路时，与外部同步信号同步，将扫描计数器和CRTC的触发器复位到初始状态。

20. 发明授权

US5511178A Cache control system equipped with a loop lock indicator for indicating the presence and/or absence of an instruction in a feedback loop section 失效
标题翻译：缓存控制系统配备有用于指示反馈回路部分中存在和/或不存在指令的循环锁定指示器
公开(公告)号：US5511178A
公开(公告)日：1996-04-23
申请号：US156301
申请日：1993-11-23
申请人： Hiroshi Takeda , Shigezumi Matsui
发明人： Hiroshi Takeda , Shigezumi Matsui
IPC分类号： G06F9/38 , G06F9/45 , G06F12/08 , G06F12/12 , G06F12/02
CPC分类号： G06F9/381 , G06F12/0862 , G06F2212/6028
摘要： In a cache memory 20, there exist a plurality of cache lines 201, each of which is equipped with a loop lock L for indicating that an instruction is present in a feedback loop section. The states of the loop locks L are dynamically changed according to the executed state of a program. At the time of excluding the cache lines for a prefetch, the instruction string in the loop is held in the cache memory 20 till the program control transfers to the outside of the loop.
摘要翻译：在高速缓冲存储器20中，存在多个高速缓存线201，每条高速缓存线201配备有用于指示反馈回路部分中存在指令的回路锁L。循环锁L的状态根据程序的执行状态而动态变化。在排除用于预取的高速缓存行时，循环中的指令串被保存在高速缓冲存储器20中，直到程序控制转移到循环的外部。

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