专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US09087784B2 Structure and method of Tinv scaling for high k metal gate technology 有权
标题翻译：用于高k金属栅极技术的Tinv缩放的结构和方法
公开(公告)号：US09087784B2
公开(公告)日：2015-07-21
申请号：US14167532
申请日：2014-01-29
申请人： International Business Machines Corporation
发明人： Michael P. Chudzik , Dechao Guo , Siddarth A. Krishnan , Unoh Kwon , Carl J. Radens , Shahab Siddiqui
IPC分类号： H01L21/28 , H01L21/8238 , H01L27/092
CPC分类号： H01L21/28008 , H01L21/823842 , H01L21/823857 , H01L27/092
摘要： A complementary metal oxide semiconductor (CMOS) structure including a scaled n-channel field effect transistor (nFET) and a scaled p-channel field transistor (pFET) is provided. Such a structure is provided by forming a plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion within an nFET gate stack, and forming at least a pFET threshold voltage adjusted high k gate dielectric layer portion within a pFET gate stack. The pFET threshold voltage adjusted high k gate dielectric layer portion in the pFET gate stack may also plasma nitrided. The plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion includes up to 15 atomic % N2 and an nFET threshold voltage adjusted species located therein.
摘要翻译：提供包括缩放的n沟道场效应晶体管（nFET）和缩放的p沟道场效应晶体管（pFET）的互补金属氧化物半导体（CMOS）结构。通过在nFET栅极堆叠内形成等离子体氮化的nFET阈值电压调整的高k栅极电介质层部分，以及在pFET栅极堆叠内形成至少pFET阈值电压调整的高k栅介质层部分来提供这种结构。 pFET栅极堆叠中的pFET阈值电压调节的高k栅介质层部分也可以等离子体氮化。等离子体氮化nFET阈值电压调节的高k栅极电介质层部分包括高达15原子％的N 2和位于其中的nFET阈值电压调节的物质。

12. 发明授权

US09059313B2 Replacement gate having work function at valence band edge 有权
标题翻译：在价带边缘具有功函数的替换门
公开(公告)号：US09059313B2
公开(公告)日：2015-06-16
申请号：US13770552
申请日：2013-02-19
申请人： International Business Machines Corporation
发明人： Keith Kwong Hon Wong , Michael P. Chudzik , Unoh Kwon
IPC分类号： H01L21/8238 , H01L29/51 , H01L29/165 , H01L29/49 , H01L29/78 , H01L29/66
CPC分类号： H01L21/823842 , H01L29/165 , H01L29/4966 , H01L29/51 , H01L29/517 , H01L29/518 , H01L29/665 , H01L29/66545 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7843 , H01L29/7848
摘要： Replacement gate stacks are provided, which increase the work function of the gate electrode of a p-type field effect transistor (PFET). In one embodiment, the work function metal stack includes a titanium-oxide-nitride layer located between a lower titanium nitride layer and an upper titanium nitride layer. The stack of the lower titanium nitride layer, the titanium-oxide-nitride layer, and the upper titanium nitride layer produces the unexpected result of increasing the work function of the work function metal stack significantly. In another embodiment, the work function metal stack includes an aluminum layer deposited at a temperature not greater than 420° C. The aluminum layer deposited at a temperature not greater than 420° C. produces the unexpected result of increasing the work function of the work function metal stack significantly.
摘要翻译：提供了替代栅极堆叠，这增加了p型场效应晶体管（PFET）的栅电极的功函数。在一个实施例中，功函数金属堆叠包括位于下部氮化钛层和上部氮化钛层之间的氧化钛 - 氮化物层。下部氮化钛层，钛氧化物 - 氮化物层和上部氮化钛层的堆叠产生显着增加功函数金属叠层功函数的意想不到的结果。在另一个实施例中，功函数金属堆叠包括在不高于420℃的温度下沉积的铝层。在不高于420℃的温度下沉积的铝层产生增加工件功函数的意想不到的结果功能金属堆叠显着。

13. 发明授权

US08940599B2 Scaled equivalent oxide thickness for field effect transistor devices 有权
标题翻译：场效应晶体管器件的等效氧化物厚度变化
公开(公告)号：US08940599B2
公开(公告)日：2015-01-27
申请号：US14217574
申请日：2014-03-18
申请人： International Business Machines Corporation
发明人： Takashi Ando , Changhwan Choi , Unoh Kwon , Vijay Narayanan
IPC分类号： H01L21/8238 , H01L21/02 , H01L21/28 , H01L29/51
CPC分类号： H01L21/823842 , H01L21/02164 , H01L21/02697 , H01L21/28229 , H01L21/823857 , H01L29/517 , H01L29/518
摘要： A field effect transistor device includes a first gate stack portion including a dielectric layer disposed on a substrate, a first TiN layer disposed on the dielectric layer, a metallic layer disposed on the dielectric layer, and a second TiN layer disposed on the metallic layer, a first source region disposed adjacent to the first gate stack portion, and a first drain region disposed adjacent to the first gate stack portion.
摘要翻译：场效应晶体管器件包括：第一栅堆叠部分，包括设置在衬底上的电介质层，设置在电介质层上的第一TiN层，设置在电介质层上的金属层和设置在金属层上的第二TiN层，与第一栅叠层部相邻设置的第一源极区域和与第一栅极堆叠部分相邻设置的第一漏极区域。

14. 发明授权

US08912607B2 Replacement metal gate structures providing independent control on work function and gate leakage current 有权
标题翻译：替代金属栅极结构提供对功函数和栅极漏电流的独立控制
公开(公告)号：US08912607B2
公开(公告)日：2014-12-16
申请号：US13789018
申请日：2013-03-07
申请人： International Business Machines Corporation
发明人： Unoh Kwon , Ramachandra Divakaruni , Siddarth A. Krishnan , Ravikumar Ramachandran
IPC分类号： H01L21/70 , H01L27/092 , H01L27/088 , H01L21/28 , H01L21/8234 , H01L21/8238 , H01L29/49 , H01L29/66 , H01L29/78 , H01L29/51
CPC分类号： H01L27/092 , H01L21/28088 , H01L21/82345 , H01L21/823462 , H01L21/823842 , H01L21/823857 , H01L27/088 , H01L27/0922 , H01L29/49 , H01L29/513 , H01L29/66545 , H01L29/7833 , H01L29/7843
摘要： The thickness and composition of a gate dielectric can be selected for different types of field effect transistors through a planar high dielectric constant material portion, which can be provided only for selected types of field effect transistors. Further, the work function of field effect transistors can be tuned independent of selection of the material stack for the gate dielectric. A stack of a barrier metal layer and a first-type work function metal layer is deposited on a gate dielectric layer within recessed gate cavities after removal of disposable gate material portions. After patterning the first-type work function metal layer, a second-type work function metal layer is deposited directly on the barrier metal layer in the regions of the second type field effect transistor. A conductive material fills the gate cavities, and a subsequent planarization process forms dual work function metal gate structures.
摘要翻译：可以通过平面高介电常数材料部分为不同类型的场效应晶体管选择栅极电介质的厚度和组成，其可以仅针对选定类型的场效应晶体管提供。此外，场效应晶体管的工作功能可以独立于栅极电介质的材料堆叠的选择而被调整。在去除一次性栅极材料部分之后，在凹入的栅极腔内的栅极电介质层上沉积阻挡金属层和第一类型功函数金属层的堆叠。图案化第一型功函数金属层之后，第二类功函数金属层直接沉积在第二类型场效应晶体管的区域中的势垒金属层上。导电材料填充栅极腔，随后的平坦化工艺形成双功能金属栅极结构。

15. 发明授权

US08809176B2 Replacement gate with reduced gate leakage current 有权
标题翻译：栅极泄漏电流降低的替代栅极
公开(公告)号：US08809176B2
公开(公告)日：2014-08-19
申请号：US13842217
申请日：2013-03-15
申请人： International Business Machines Corporation
发明人： Takashi Ando , Michael P. Chudzik , Rishikesh Krishnan , Siddarth A. Krishnan , Unoh Kwon , Keith Kwong Hon Wong
IPC分类号： H01L21/3205
CPC分类号： H01L21/28008 , H01L21/28088 , H01L21/823842 , H01L29/4966 , H01L29/66545 , H01L29/66606 , H01L29/7833 , H01L29/7843
摘要： Replacement gate work function material stacks are provided, which provides a work function about the energy level of the conduction band of silicon. After removal of a disposable gate stack, a gate dielectric layer is formed in a gate cavity. A metallic compound layer including a metal and a non-metal element is deposited directly on the gate dielectric layer. At least one barrier layer and a conductive material layer is deposited and planarized to fill the gate cavity. The metallic compound layer includes a material having a work function about 4.4 eV or less, and can include a material selected from tantalum carbide and a hafnium-silicon alloy. Thus, the metallic compound layer can provide a work function that enhances the performance of an n-type field effect transistor employing a silicon channel.
摘要翻译：提供了替代栅极工作功能材料堆叠，其提供关于硅导带的能级的功函数。在去除一次性栅极堆叠之后，在栅极腔中形成栅极电介质层。包括金属和非金属元素的金属化合物层直接沉积在栅极介电层上。沉积至少一个势垒层和导电材料层并平坦化以填充栅极腔。金属化合物层包括功函数约4.4eV或更低的材料，并且可以包括选自碳化钽和铪硅合金的材料。因此，金属化合物层可以提供增强采用硅通道的n型场效应晶体管的性能的功函数。

16. 发明申请

US20140057426A1 NON-VOLATILE MEMORY STRUCTURE EMPLOYING HIGH-K GATE DIELECTRIC AND METAL GATE 有权
标题翻译：使用高K门电介质和金属门的非易失性存储器结构
公开(公告)号：US20140057426A1
公开(公告)日：2014-02-27
申请号：US14066119
申请日：2013-10-29
申请人： International Business Machines Corporation
发明人： Nicolas Breil , Michael P. Chudzik , Rishikesh Krishnan , Siddarth A. Krishnan , Unoh Kwon
IPC分类号： H01L21/28 , H01L21/02
CPC分类号： H01L21/28273 , H01L21/0228 , H01L21/823842 , H01L21/823857 , H01L21/823892 , H01L27/11546 , H01L29/42376 , H01L29/4958 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/66545 , H01L29/7881
摘要： A high dielectric constant (high-k) gate dielectric for a field effect transistor (FET) and a high-k tunnel dielectric for a non-volatile random access memory (NVRAM) device are simultaneously formed on a semiconductor substrate. A stack of at least one conductive material layer, a control gate dielectric layer, and a disposable material layer is subsequently deposited and lithographically patterned. A planarization dielectric layer is deposited and patterned, and disposable material portions are removed. A remaining portion of the control gate dielectric layer is preserved in the NVRAM device region, but is removed in the FET region. A conductive material is deposited in gate cavities to provide a control gate for the NVRAM device and a gate portion for the FET. Alternately, the control gate dielectric layer may replaced with a high-k control gate dielectric in the NVRAM device region.
摘要翻译：在半导体衬底上同时形成用于场效应晶体管（FET）的高介电常数（高k）栅极电介质和非易失性随机存取存储器（NVRAM）器件的高k隧道电介质。随后沉积至少一个导电材料层，控制栅极电介质层和一次性材料层的堆叠并且被光刻图案化。沉积并图案化平坦化介电层，并且去除一次性材料部分。控制栅极电介质层的剩余部分保留在NVRAM器件区域中，但在FET区域中被去除。导电材料沉积在栅极腔中以为NVRAM器件提供控制栅极和用于FET的栅极部分。或者，控制栅介质层可以用NVRAM器件区域中的高k控制栅极电介质代替。

17. 发明申请

US20130175635A1 REPLACEMENT METAL GATE STRUCTURES FOR EFFECTIVE WORK FUNCTION CONTROL 有权
标题翻译：更换用于有效工作功能控制的金属门结构
公开(公告)号：US20130175635A1
公开(公告)日：2013-07-11
申请号：US13780003
申请日：2013-02-28
申请人： International Business Machines Corporation
发明人： Unoh Kwon , Michael P. Chudzik , Ravikumar Ramachandran
IPC分类号： H01L27/092
CPC分类号： H01L27/0922 , H01L21/823842
摘要： A stack of a barrier metal layer and a first-type work function metal layer is deposited in replacement metal gate schemes. The barrier metal layer can be deposited directly on the gate dielectric layer. The first-type work function metal layer is patterned to be present only in regions of a first type field effect transistor. A second-type work function metal layer is deposited directly on the barrier metal layer in the regions of a second type field effect transistor. Alternately, the first-type work function layer can be deposited directly on the gate dielectric layer. The barrier metal layer is patterned to be present only in regions of a first type field effect transistor. A second-type work function metal layer is deposited directly on the gate dielectric layer in the regions of the second type field effect transistor. A conductive material fill and planarization form dual work function replacement gate structures.
摘要翻译：在替换金属栅极方案中沉积阻挡金属层和第一型功函数金属层的堆叠。阻挡金属层可以直接沉积在栅极介电层上。图案化第一型功函数金属层仅存在于第一类场效应晶体管的区域中。第二类功函数金属层直接沉积在第二类场效应晶体管的区域中的势垒金属层上。或者，第一类功函数层可以直接沉积在栅介电层上。图案化阻挡金属层仅存在于第一类场效应晶体管的区域中。第二类型功函数金属层直接沉积在第二类场效应晶体管的区域中的栅介质层上。导电材料填充和平坦化形成双功能功能替代栅极结构。

18. 发明授权

US11031301B2 Gate formation scheme for n-type and p-type transistors having separately tuned threshold voltages 有权
公开(公告)号：US11031301B2
公开(公告)日：2021-06-08
申请号：US16691803
申请日：2019-11-22
申请人： International Business Machines Corporation
发明人： Ruqiang Bao , Unoh Kwon , Vijay Narayanan
IPC分类号： H01L21/8238 , H01L29/49 , H01L27/092 , H01L21/28
摘要： Embodiments of the invention include a wafer having gate stacks over channel fins. The wafer includes a first channel fin in an n-type region of a substrate, a second channel fin in a p-type region of the substrate, and a gate dielectric over the substrate and the first and second channel fins. A work function metal stack is over the gate dielectric, the first channel fin in the n-type region, and the second channel fin in the p-type region. The work function metal stack over the gate dielectric and the first channel fin in the n-type region forms a first work function metal stack. The work function metal stack over the gate dielectric and the second fin in the p-type region forms a second work function metal stack. The first work function metal stack includes a shared layer of work function metal shared with the second work function metal stack.

19. 发明申请

US20180330996A1 FIELD EFFECT TRANSISTOR GATE STACK 审中-公开
公开(公告)号：US20180330996A1
公开(公告)日：2018-11-15
申请号：US16026209
申请日：2018-07-03
申请人： International Business Machines Corporation
发明人： Ruqiang Bao , Siddarth A. Krishnan , Unoh Kwon , Vijay Narayanan
IPC分类号： H01L21/8238 , H01L27/092 , H01L29/49 , H01L21/28 , H01L29/66
CPC分类号： H01L21/823842 , H01L21/28088 , H01L21/823821 , H01L27/092 , H01L27/0924 , H01L29/4966 , H01L29/66545
摘要： A method for fabricating a gate stack of a semiconductor device comprises forming a first dielectric layer over a channel region of the device, depositing a first nitride layer on exposed portions of the first dielectric layer, depositing a scavenging layer on the first nitride layer, forming a capping layer over the scavenging layer, removing portions of the capping layer, the scavenging layer, and the first nitride layer to expose a portion of the first dielectric layer in an n-type field effect transistor (nFET) region of the gate stack, forming a barrier layer over the first dielectric layer and the capping layer, forming a first gate metal layer over the barrier layer, depositing a second nitride layer on the first gate metal layer, and depositing a gate electrode material on the second nitride layer.

20. 发明授权

US09997610B2 Gate stack formed with interrupted deposition processes and laser annealing 有权
公开(公告)号：US09997610B2
公开(公告)日：2018-06-12
申请号：US15417464
申请日：2017-01-27
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Takashi Ando , Aritra Dasgupta , Oleg Gluschenkov , Balaji Kannan , Unoh Kwon
IPC分类号： H01L29/51 , H01L27/088 , H01L21/8238
CPC分类号： H01L29/513 , H01L21/022 , H01L21/02255 , H01L21/0228 , H01L21/02356 , H01L21/2636 , H01L21/268 , H01L21/28185 , H01L21/28194 , H01L21/28229 , H01L21/823412 , H01L21/823462 , H01L21/823857 , H01L27/088 , H01L29/42364 , H01L29/511 , H01L29/517 , H01L29/518
摘要： Semiconductor structures and methods of fabricating the same using interrupted deposition processes and multiple laser anneals are provided. The structure includes a high-k gate stack with a high-k bilayer or nanolaminate where a bottom portion of the bilayer is crystallized while a top portion of the bilayer is amorphous.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式