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11. 发明授权

US5732011A Digital system having high speed buffering 失效
标题翻译：具有高速缓冲的数字系统
公开(公告)号：US5732011A
公开(公告)日：1998-03-24
申请号：US801908
申请日：1997-02-14
申请人： Steven G. Schmidt
发明人： Steven G. Schmidt
IPC分类号： G06F5/06 , G11C13/00
CPC分类号： G06F5/06
摘要： A FIFO memory eliminates the delay associated with selecting memory locations during a read and write operation and prevents data intended to be saved from changing during the write operation. The FIFO memory includes a shift register having a plurality of memory locations, data input and data output terminals coupled to the memory, a first memory location coupled to the data output terminal that is immediately output enabled in response to a read operation, and a single pointer arrangement coupled to the memory locations for selectively saving data contents in successive memory locations coincidentally with the occurrence of successive write operations.
摘要翻译： FIFO存储器消除了在读取和写入操作期间与选择存储器位置相关联的延迟，并且防止在写入操作期间保存的数据不被改变。 FIFO存储器包括具有多个存储器位置的移位寄存器，耦合到存储器的数据输入端和数据输出端，耦合到数据输出端的第一存储器位置，其响应于读取操作立即被输出使能，以及单个指针布置耦合到存储器位置，用于在连续写入操作的发生中与选择性地在连续存储器位置中保存数据内容。

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