专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明申请

US20160104535A1 NONVOLATILE MEMORY HAVING MEMORY ARRAY WITH DIFFERENTIAL CELLS 有权
标题翻译：具有不同细胞的记忆阵列的非易失性存储器
公开(公告)号：US20160104535A1
公开(公告)日：2016-04-14
申请号：US14743315
申请日：2015-06-18
申请人： eMemory Technology Inc.
发明人： Yu-Hsiung Tsai
IPC分类号： G11C16/14 , G11C16/26
CPC分类号： G11C16/14 , G11C5/063 , G11C16/0433 , G11C16/08 , G11C16/10 , G11C16/26 , G11C16/30 , H01L27/092 , H01L27/11521 , H01L27/11526 , H01L29/0642 , H01L29/1095 , H02M1/14 , H02M3/07
摘要： A nonvolatile memory includes a memory array. The memory array is connected to m word lines and (2+n) bit line pairs. These bit line pairs include an erase bit line pair, a program bit line pair and n data bit line pairs. Each word line is connected with (2+n) differential cells of a corresponding row. The (2+n) differential cells include an erase flag differential cell, a program flag differential cell and n data differential cells. The erase flag differential cell is connected with the erase bit line pair. The program flag differential cell is connected with the program line pair. The n data differential cells are connected with the data line pairs. The n data differential cells are determined as erased cells or programmed cells according to setting conditions of the erase flag differential cell and the program flag differential cell.
摘要翻译：非易失性存储器包括存储器阵列。存储器阵列连接到m个字线和（2 + n）个位线对。这些位线对包括擦除位线对，程序位线对和n个数据位线对。每个字线与相应行的（2 + n）个差分单元连接。（2 + n）个差分单元包括擦除标志差分单元，程序标志差分单元和n个数据差分单元。擦除标志差分单元与擦除位线对连接。程序标志差分单元与程序行对相连。 n个数据差分单元与数据线对相连。根据擦除标志差分单元和程序标志差分单元的设置条件，将n个数据差分单元确定为擦除单元或编程单元。

12. 发明申请

US20160042795A1 NON-VOLATILE MEMORY APPARATUS AND ERASING METHOD THEREOF 审中-公开
标题翻译：非易失性存储器及其擦除方法
公开(公告)号：US20160042795A1
公开(公告)日：2016-02-11
申请号：US14920895
申请日：2015-10-23
申请人： eMemory Technology Inc.
发明人： Yu-Hsiung Tsai , Chun-Yuan Lo
IPC分类号： G11C16/14
CPC分类号： G11C16/14 , G11C16/16 , H02M1/14 , H02M3/07 , H03K19/018514
摘要： The invention provides a non-volatile memory apparatus and an erasing method thereof. The non-volatile memory apparatus includes a plurality of memory sectors and a control voltage provider. The memory sectors disposed in a same well, wherein, each of the memory sectors includes a plurality of memory cells for respectively receiving a plurality of control line signals. The control voltage provider provides the control line signals to the memory cells of each of the first memory sectors. When an erasing operation is operated, one of the memory sectors is selected for erasing and the control voltage provider provides the control line signals of the selected memory sector with an erase control voltage and provides the control line signals of the un-selected memory sectors with a un-erase control voltage, voltage levels of the erase control voltage and the un-erase control voltage are different.
摘要翻译：本发明提供一种非易失性存储装置及其擦除方法。非易失性存储装置包括多个存储器扇区和控制电压提供器。设置在同一个井中的存储器扇区，其中每个存储器扇区包括用于分别接收多个控制线信号的多个存储单元。控制电压提供器将控制线信号提供给每个第一存储器扇区的存储单元。当擦除操作被操作时，选择一个存储器扇区用于擦除，并且控制电压提供器提供所选择的存储器扇区的控制线信号的擦除控制电压，并且向未选择的存储器扇区提供控制线信号擦除控制电压，擦除控制电压和解除擦除控制电压的电压电平不同。

13. 发明申请

US20150092497A1 BIAS GENERATOR FOR FLASH MEMORY AND CONTROL METHOD THEREOF 有权
标题翻译：用于闪速存储器的偏置发生器及其控制方法
公开(公告)号：US20150092497A1
公开(公告)日：2015-04-02
申请号：US14242022
申请日：2014-04-01
申请人： eMemory Technology Inc.
发明人： Yu-Hsiung Tsai
IPC分类号： G11C16/30 , G11C16/28 , G11C16/04 , G11C5/14
CPC分类号： H01L27/11558 , G11C5/147 , G11C7/12 , G11C16/0408 , G11C16/0433 , G11C16/28 , G11C16/30 , H01L21/28273 , H01L27/11519 , H01L27/11521 , H01L29/42328 , H01L29/4916
摘要： A bias voltage generator for providing a control voltage and a source line voltage to a memory array includes a reference voltage generating circuit and a voltage converting circuit. The reference voltage generating circuit receives a program signal or an erase signal, and generates a reference voltage. If the program signal is received by the reference voltage generating circuit, the reference voltage has a positive temperature coefficient. If the erase signal is received by the reference voltage generating circuit, the reference voltage has a negative temperature coefficient. The voltage converting circuit converts the reference voltage into the control voltage and the source line voltage. The voltage converting circuit enlarges the reference voltage by a first magnification so as to produce the source line voltage, and enlarges the reference voltage by a second magnification so as to produce the control voltage.
摘要翻译：用于向存储器阵列提供控制电压和源极线电压的偏置电压发生器包括参考电压产生电路和电压转换电路。参考电压产生电路接收编程信号或擦除信号，并产生参考电压。如果编程信号由参考电压产生电路接收，则参考电压具有正温度系数。如果由参考电压产生电路接收到擦除信号，则参考电压具有负温度系数。电压转换电路将参考电压转换成控制电压和源极线电压。电压转换电路通过第一倍率放大参考电压，以产生源极线电压，并且将基准电压放大第二放大率以产生控制电压。

14. 发明授权

US08982634B2 Flash memory 有权
标题翻译：闪存
公开(公告)号：US08982634B2
公开(公告)日：2015-03-17
申请号：US14152467
申请日：2014-01-10
申请人： eMemory Technology Inc.
发明人： Yu-Hsiung Tsai , Yuan-Tai Lin , Ching-Yuan Lin , Chao-Wei Kuo , Shang-Wei Fang , Wein-Town Sun
IPC分类号： G11C11/34 , G11C13/00 , G11C16/04 , G11C16/12
CPC分类号： G11C13/0069 , G11C13/0064 , G11C16/04 , G11C16/12
摘要： The present invention provides a flash memory including a memory cell, a current limiter and a program voltage generator. The memory cell is programmed in response to a program current and a program voltage. The current limiter reflects amount of the program current by a data-line signal, e.g., a data-line voltage. The program voltage generator generates and controls the program voltage in response to the data-line voltage, such that the program current can track to a constant reference current.
摘要翻译：本发明提供一种包括存储单元，限流器和编程电压发生器的闪速存储器。响应于编程电流和编程电压对存储单元进行编程。电流限制器通过数据线信号（例如数据线电压）反映节目电流的量。程序电压发生器响应于数据线电压产生并控制编程电压，使得编程电流可以跟踪恒定的参考电流。

15. 发明申请

US20140211562A1 FLASH MEMORY AND ASSOCIATED PROGRAMMING METHOD 有权
标题翻译：闪存和相关编程方法
公开(公告)号：US20140211562A1
公开(公告)日：2014-07-31
申请号：US13755045
申请日：2013-01-31
申请人： EMEMORY TECHNOLOGY INC.
发明人： Che-Wei Chang , Chia-Fu Chang , Yu-Hsiung Tsai , Chia-Jung Hsu
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/30
摘要： A flash memory includes a program voltage generator, plural memory units, a current limiter, and a multi-bit program control unit. The program voltage generator is used for providing a constant program voltage during a detecting cycle and providing a dynamically-adjustable program voltage during a program cycle. The plural memory units output plural drain currents and plural data line voltages to plural data lines. The current limiter is used for receiving a reference current and a reference voltage, thereby controlling the plural drain currents. During the detecting cycle, a specified data line voltage of the plural data line voltages with the minimum voltage level is detected by the multi-bit program control unit. During the program cycle, the specified data line voltage is used as a feedback voltage, and the dynamically-adjustable program voltage is generated by the program voltage generator according to the feedback voltage.
摘要翻译：闪速存储器包括编程电压发生器，多个存储器单元，限流器和多位程序控制单元。程序电压发生器用于在检测周期期间提供恒定的编程电压，并在编程周期期间提供动态可调节的编程电压。多个存储单元将多个漏极电流和多个数据线电压输出到多条数据线。电流限制器用于接收参考电流和参考电压，从而控制多个漏极电流。在检测周期期间，由多位程序控制单元检测具有最小电压电平的多条数据线电压的指定数据线电压。在编程周期中，指定的数据线电压用作反馈电压，动态可调程序电压由编程电压发生器根据反馈电压产生。

16. 发明申请

US20140119125A1 FLASH MEMORY 有权
公开(公告)号：US20140119125A1
公开(公告)日：2014-05-01
申请号：US14152467
申请日：2014-01-10
申请人： eMemory Technology Inc.
发明人： Yu-Hsiung Tsai , Yuan-Tai Lin , Ching-Yuan Lin , Chao-Wei Kuo , Shang-Wei Fang , Wein-Town Sun
IPC分类号： G11C16/12
CPC分类号： G11C13/0069 , G11C13/0064 , G11C16/04 , G11C16/12
摘要： The present invention provides a flash memory including a memory cell, a current limiter and a program voltage generator. The memory cell is programmed in response to a program current and a program voltage. The current limiter reflects amount of the program current by a data-line signal, e.g., a data-line voltage. The program voltage generator generates and controls the program voltage in response to the data-line voltage, such that the program current can track to a constant reference current.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式