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11. 发明申请

US20230086600A1 STABLE SWITCHING FOR A POWER FACTOR CORRECTION BOOST CONVERTER USING AN INPUT VOLTAGE AND AN OUTPUT VOLTAGE 有权
公开(公告)号：US20230086600A1
公开(公告)日：2023-03-23
申请号：US17478500
申请日：2021-09-17
申请人： NXP USA, Inc.
发明人： Remco Twelkemeijer , Wilhelmus Hinderikus Maria Langeslag
IPC分类号： H02M1/42 , H02M1/08 , H02M1/00
摘要： Stable switching is disclosed for a power factor correction boost converter using an input voltage and an output voltage. In one example, a boost converter control system includes a gate driver coupled to a switch of a boost converter to generate a drive signal to control switching of the switch, wherein a period of the drive signal is adjusted using a current adjustment signal. A current control loop is coupled to the gate driver to receive a sensed input current from the boost converter and a desired input current and to generate the current adjustment signal to the gate driver. A current limiter is coupled to the gate driver and the current control loop to determine a duty cycle of the switch, to determine a maximum input current in response to the duty cycle, and to restrict the desired input current to below the maximum input current.

12. 发明授权

US11609833B2 Fault injection in a clock monitor unit 有权
公开(公告)号：US11609833B2
公开(公告)日：2023-03-21
申请号：US17024798
申请日：2020-09-18
申请人： NXP USA, Inc.
发明人： Praveen Durga , Parul Bansal
IPC分类号： G06F11/27 , G01R31/317 , G06F11/263 , H03K5/22 , G06F1/04 , G01R23/15 , G01R31/3193 , G06F11/07 , G01R31/319 , G01R31/3187
摘要： A self-test mechanism within an integrated circuit to test for faulty operation of a clock monitor unit implemented within the integrated circuit for monitoring a clock signal. The mechanism intentionally injects faults into the clock monitor unit to evaluate if the clock monitor unit is operating in accordance with its specified operating parameters. The injected faults are intended to cause the clock monitor unit to determine that the clock signal is operating outside of an artificially generated, imaginary specified frequency range. If the injected faults do not cause the clock monitor unit to determine that the clock signal is operating both above and below the artificially generated, imaginary specified frequency range, then the clock monitor unit is not functioning according to specified operating parameters.

13. 发明授权

US11609821B2 Method and system for managing fault recovery in system-on-chips 有权
公开(公告)号：US11609821B2
公开(公告)日：2023-03-21
申请号：US17039576
申请日：2020-09-30
申请人： NXP USA, Inc.
发明人： Ankur Behl , Neha Srivastava
IPC分类号： G06F11/14 , G06F11/30 , G06F11/07 , G06F13/40
摘要： A fault recovery system including a fault controller is disclosed. The fault controller is coupled between a processor and an interconnect, and configured to receive a time-out signal that is indicative of a failure of the processor to execute a transaction after a fault is detected in the processor. The failure in the execution of the transaction results in queuing of the interconnect. Based on the time-out signal, the fault controller is further configured to generate and transmit a control signal to the processor to disconnect the processor from the interconnect. Further, the fault controller is configured to execute the transaction, and in turn, dequeue the interconnect. When the transaction is successfully executed, the fault controller is further configured to generate a status signal to reset the processor, thereby managing a fault recovery of the processor.

14. 发明申请

US20230079916A1 T-MATCH TOPOLOGY WITH BASEBAND TERMINATION 有权
公开(公告)号：US20230079916A1
公开(公告)日：2023-03-16
申请号：US17471228
申请日：2021-09-10
申请人： NXP USA, Inc.
发明人： Jeffrey Spencer Roberts , Ning Zhu , Damon G. Holmes
IPC分类号： H03F1/56 , H03F3/195 , H03F1/02
摘要： Embodiments of RF amplifiers and packaged RF amplifier devices each include an amplification path with a transistor die, and an output-side impedance matching circuit having a T-match circuit topology. The output-side impedance matching circuit includes a first inductive element connected between the transistor output terminal and a quasi RF cold point node, a second inductive element connected between the quasi RF cold point node and an output of the amplification path, and a first capacitance connected between the quasi RF cold point node and a ground reference node. The RF amplifiers and devices also include a baseband termination circuit connected to the quasi RF cold point node, which includes a third inductive element, a resistor, and a second capacitance in series between the quasi RF cold point node and the ground reference node and a third capacitance between a baseband termination circuit node and the ground reference node.

15. 发明申请

US20230079000A1 BUILT IN SELF TEST (BIST) FOR CLOCK GENERATION CIRCUITRY 有权
公开(公告)号：US20230079000A1
公开(公告)日：2023-03-16
申请号：US17447743
申请日：2021-09-15
申请人： NXP USA, Inc.
发明人： Jorge Arturo Corso Sarmiento , Anurag Jindal
IPC分类号： G01R31/317 , G01R31/3177 , G01R31/3187 , G01R31/3185
摘要： Testing clock division circuitry includes generating pseudo random test pattern bits for scan chain logic in programmable clock division logic circuitry and divided clock counter circuitry. A shift clock is used to shift the test pattern bits into the scan chain logic. A capture clock signal is used in the programmable clock division logic during a non-test mode of operation. The shift clock is used to provide output shift bits from the scan chain logic to a multi-input shift register (MISR). Once all the output shift bits for the test pattern bits are provided to the MISR, a final test signature from the MISR is compared to an expected test signature to determine whether the programmable clock division logic circuitry and divided clock counter circuitry are free of faults.

16. 发明授权

US11605962B2 Multi-level encoding for battery management system 有权
公开(公告)号：US11605962B2
公开(公告)日：2023-03-14
申请号：US16934458
申请日：2020-07-21
申请人： NXP USA, Inc.
发明人： Laurent Bordes , Simon Bertrand , Alexis Nathanael Huot-Marchand
IPC分类号： H02J7/00 , H01M10/42 , H04L67/12
摘要： A battery management system comprises a first and second battery cell controllers and a transmission line providing a point-to-point signal transmission path between the first and second battery cell controllers. At least one of the first and second battery cell controllers includes a logic circuit constructed and arranged for encoding data for transmission as a serial data stream along the signal transmission path in compliance with a multi-level encoding technique. The logic circuit comprises an encoding/decoding circuit that generates a modulated signal of the serial data stream over at least three discrete signal levels at a predetermined and fixed data pulse frequency for transmission through the transmission line and encodes a plurality of data units of the serial data stream into a data packet. The data packet includes at least three symbols constructed and arranged with at least four consecutive transmissions per symbol. Each transmission of each symbol assumes one of the three discrete signal levels. At least one transceiver is configured in a transmit mode or a receive mode and that discards any combinations of the maximum number of possible combinations to reduce a source of electromagnetic interference (EMI) on the transmission line.

17. 发明授权

US11604223B1 Clock control system for scan chains 有权
公开(公告)号：US11604223B1
公开(公告)日：2023-03-14
申请号：US17644605
申请日：2021-12-16
申请人： NXP USA, INC.
发明人： Himanshu Mangal , Amol Agarwal , Abhishek Mahajan , Love Gupta , Pratyush Pranav Joshi
IPC分类号： G01R31/3185 , G01R31/317
摘要： A clock control system for a scan chain generates two clock signals. During a shift phase of a testing mode of the scan chain, one clock signal is an inverted version of the other clock signal. The clock control system provides the clock signal and the inverted clock signal to two different scan flip-flops of the scan chain, respectively. Each of the two scan flip-flops performs a flip-flop operation when the received clock signal transitions from a de-asserted state to an asserted state. Thus, the two flip-flop operations are mutually exclusive during the shift phase. As a result, a dynamic voltage drop across the scan chain during the shift phase is reduced.

18. 发明申请

US20230066652A1 SEMICONDUCTOR DEVICE PACKAGING WARPAGE CONTROL 有权
公开(公告)号：US20230066652A1
公开(公告)日：2023-03-02
申请号：US17412327
申请日：2021-08-26
申请人： NXP USA, INC.
发明人： Vivek Gupta , Michael B. Vincent , Scott M. Hayes , Richard Te Gan , Zhiwei Gong
IPC分类号： H01L23/00 , H01L21/48 , H01L21/56 , H01L23/13
摘要： A method of manufacturing a carrier for semiconductor device packaging is provided. The method includes forming a carrier having a plurality of plateau regions separated by a plurality of channels. The carrier is configured and arranged to support a plurality of semiconductor die during a packaging operation. The plurality of channels is filled with a material configured to control warpage of the carrier.

19. 发明申请

US20230060492A1 DEVICE, SYSTEM, AND METHOD FOR WIRELESS LOCAL AREA NETWORK (WLAN) SENSING 有权
公开(公告)号：US20230060492A1
公开(公告)日：2023-03-02
申请号：US17894998
申请日：2022-08-24
申请人： NXP USA, Inc.
发明人： Dong Wei , Rui Cao , Hongyuan Zhang , Christian Raimund Berger , Liwen Chu
IPC分类号： H04W24/08 , H04W52/14 , H04W52/54
摘要： Embodiments of a device, a method, and a system for wireless local area network (WLAN) sensing are disclosed. In an embodiment, the device for WLAN sensing includes a wireless network interface device implemented on one or more integrated circuits (ICs), where the wireless network interface device is configured to receive a sounding Physical Layer (PHY) Protocol Data Unit (PPDU) that includes preamble training fields, and detect environmental changes using managed sensing measurements obtained from the preamble training fields included in the sounding PPDU.

20. 发明授权

US11588481B2 Radio frequency switches with voltage equalization 有权
公开(公告)号：US11588481B2
公开(公告)日：2023-02-21
申请号：US17190702
申请日：2021-03-03
申请人： NXP USA, Inc.
发明人： Venkata Naga Koushik Malladi
IPC分类号： H03K17/16 , H04B1/48 , H01L27/12 , H01L21/84
摘要： Embodiments described herein include radio frequency (RF) switches that may provide increased power handling capability. In general, the embodiments described herein can provide this increased power handling by equalizing the voltages across transistors when the RF switch is open. Specifically, the embodiments described herein can be implemented to equalize the source-drain voltages across each field effect transistor (FET) in a FET stack that occurs when the RF switch is open and not conducting current. This equalization can be provided by using one or more compensation circuits to couple one or more gates and transistor bodies in the FET stack in a way that at least partially compensates for the effects of parasitic leakage currents in the FET stack.

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