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11. 发明授权

US11545565B2 Semiconductor device and method of forming low voltage power MOSFETs using graphene for metal layers and graphene nanoribbons for channel and drain enhancement regions of power vertical and lateral MOSFETs 有权
公开(公告)号：US11545565B2
公开(公告)日：2023-01-03
申请号：US17075753
申请日：2020-10-21
申请人： IceMos Technology Limited
发明人： Samuel J. Anderson
IPC分类号： H01L21/00 , H01L29/76 , H01L29/16 , H01L21/02 , H01L29/66
摘要： A semiconductor device has a substrate and graphene with semiconducting properties or diamond region formed on the substrate. The graphene with semiconducting properties or diamond region is formed on or within the substrate using liquid-phase-epitaxy growth of graphene enabled by a catalytic alloy of Ni and Cu. The substrate can be silicon, silicon carbide, gallium arsenide, gallium nitride, germanium, or indium phosphide. A semiconductor component is formed over the graphene with semiconducting properties or diamond region and substrate. The semiconductor component can be a power MOSFET, IGBT, or CTIGBT with a gate structure formed over the substrate, source region adjacent to the gate structure, and drain region adjacent to the gate structure opposite the source region. The graphene with semiconducting properties or diamond region is formed under a gate of the MOSFET to reduce drain to source resistance, as well as providing radiation hardening for the device.

12. 发明授权

US11545430B2 Integrated circuitry and method used in forming a memory array comprising strings of memory cells 有权
公开(公告)号：US11545430B2
公开(公告)日：2023-01-03
申请号：US17070269
申请日：2020-10-14
申请人： Micron Technology, Inc.
发明人： Collin Howder , John D. Hopkins , Alyssa N. Scarbrough
IPC分类号： H01L29/76 , H01L23/522 , H01L27/11519 , H01L27/11524 , H01L27/11582 , H01L27/11565 , H01L27/1157 , H01L27/11556
摘要： A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. A lower portion of a stack is formed, with the stack ultimately comprising vertically-alternating first tiers and second tiers above the conductor tier. The stack comprises laterally-spaced memory-block regions. Material of the first tiers is of different composition from material of the second tiers. A lowest of the first tiers comprises conductive first sacrificial material. Conductive second material is directly electrically coupled to the conductive first sacrificial material. The conductive first sacrificial material and the conductive second material have different reduction potentials that are at least 0.5V away from one another. A lowest of the second tiers is insulative and below the lowest first tier. The vertically-alternating first tiers and second tiers of an upper portion of the stack are formed above the lower portion. Channel-material strings are formed that extend through the first tiers and the second tiers in the upper portion to the lowest first tier in the lower portion. Horizontally-elongated trenches are formed into the stack that are individually between immediately-laterally-adjacent of the memory-block regions and extend to the conductive first sacrificial material and the conductive second material in the lowest first tier. The conductive first sacrificial material is galvanically etched through the trenches. The lowest second tier is removed after the galvanically etching. After removing the lowest second tier, conducting material is formed in the lowest first tier that directly electrically couples together the channel material of the individual channel-material strings and the conductor material of the conductor tier. Other embodiments, including structure independent of method, are disclosed.

13. 发明授权

US11532733B1 Dielectric isolation structure for multi-gate transistors 有权
公开(公告)号：US11532733B1
公开(公告)日：2022-12-20
申请号：US17359105
申请日：2021-06-25
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Jen-Hong Chang , Yi-Hsiu Liu , You-Ting Lin , Chih-Chung Chang , Kuo-Yi Chao , Jiun-Ming Kuo , Yuan-Ching Peng , Sung-En Lin , Chia-Cheng Chao , Chung-Ting Ko
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L29/66 , H01L21/8234 , H01L29/06 , H01L29/78
摘要： Semiconductor structures and methods of forming the same are provided. A method according to the present disclosure includes forming a stack of epitaxial layers over a substrate, forming a first fin-like structure and a second fin-like structure from the stack, forming an isolation feature between the first fin-like structure and the second fin-like structure, forming a cladding layer over the first fin-like structure and the second fin-like structure, conformally depositing a first dielectric layer over the cladding layer, depositing a second dielectric layer over the first dielectric layer, planarizing the first dielectric layer and the second dielectric layer until the cladding layer are exposed, performing an etch process to etch the second dielectric layer to form a helmet recess, performing a trimming process to trim the first dielectric layer to widen the helmet recess, and depositing a helmet feature in the widened helmet recess.

14. 发明授权

US11522076B2 Field effect transistor, method of fabricating field effect transistor, and electronic device 有权
公开(公告)号：US11522076B2
公开(公告)日：2022-12-06
申请号：US16772742
申请日：2018-10-17
申请人： BEIJING HUA TAN YUAN XIN ELECTRONICS TECHNOLOGY CO., LTD , BEIJING HUATAN TECHNOLOGY CO., LTD
发明人： Shibo Liang
IPC分类号： H01L29/66 , H01L29/16 , H01L29/76 , H01L21/02
摘要： A field effect transistor (FET), a method of fabricating a field effect transistor, and an electronic device, the field effect transistor comprises: a source and a drain, the source being made of a first graphene film; a channel disposed between the source and the drain, and comprising a laminate of a second graphene film and a material layer having semiconductor properties, the second graphene film being formed of bilayer graphene; and a gate disposed on the laminate and electrically insulated from the laminate.

15. 发明申请

US20220336647A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
公开(公告)号：US20220336647A1
公开(公告)日：2022-10-20
申请号：US17852079
申请日：2022-06-28
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
发明人： Sheng-Kai SU
IPC分类号： H01L29/76 , H01L29/66 , H01L29/78 , H01L29/24
摘要： A method includes forming a semiconductor fin protruding above a substrate; forming a first 2D material layer across the semiconductor fin; depositing a gate material layer over the first 2D material layer; etching the gate material layer and the first 2D material layer to form a gate structure and a patterned first 2D material layer under the gate structure; laterally growing a second 2D material layer from the patterned first 2D material layer to beyond the gate structure; after laterally growing the second 2D material layer, forming gate spacers respectively on opposite sidewalls of the gate structure; and after forming the gate spacers, forming a third 2D material layer on the second 2D material layer until a combination of the third 2D material layer and the second 2D material layer comprises at least three or more monolayers of PtSe2.

16. 发明申请

US20220336455A1 TRANSISTORS WITH VARYING WIDTH NANOSHEET 有权
公开(公告)号：US20220336455A1
公开(公告)日：2022-10-20
申请号：US17810341
申请日：2022-06-30
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Yi-Hsiung LIN , Yi-Hsun CHIU , Shang-Wen CHANG , Ching-Wei TSAI , Yu-Xuan HUANG , Kuan-Lun CHENG , Chih-Hao WANG
IPC分类号： H01L27/092 , H01L29/78 , H01L29/66 , H01L29/76
摘要： The present disclosure relates to an integrated circuit. In one implementation, the integrated circuit may include a semiconductor substrate; at least one source region comprising a first doped semiconductor material; at least one drain region comprising a second doped semiconductor material; at least one gate formed between the at least one source region and the at least one drain region; and a nanosheet formed between the semiconductor substrate and the at least one gate. The nanosheet may be configured as a routing channel for the at least one gate and may have a first region having a first width and a second region having a second width. The first width may be smaller than the second width.

17. 发明授权

US11469247B2 Semiconductor device and manufacturing method of a semiconductor device 有权
公开(公告)号：US11469247B2
公开(公告)日：2022-10-11
申请号：US17091180
申请日：2020-11-06
申请人： SK hynix Inc.
发明人： In Su Park
IPC分类号： H01L29/94 , H01L29/76 , H01L27/11582 , H01L29/10 , H01L29/417 , H01L29/45 , H01L27/11556 , H01L27/24 , H01L21/02 , H01L21/311 , H01L21/3213 , H01L21/28
摘要： A semiconductor device includes a stack structure, a channel layer passing through the stack structure, a memory layer enclosing the channel layer and including first and second openings which expose the channel layer, a well plate coupled to the channel layer through the first opening, and a source plate coupled to the channel layer through the second opening.

18. 发明授权

US11462628B2 Semiconductor device, and manufacturing method thereof 有权
公开(公告)号：US11462628B2
公开(公告)日：2022-10-04
申请号：US16771168
申请日：2018-11-13
申请人： CSMC TECHNOLOGIES FAB2 CO., LTD.
发明人： Huajun Jin , Guipeng Sun
IPC分类号： H01L31/062 , H01L29/76 , H01L29/66 , H01L29/40 , H01L29/78
摘要： A semiconductor device, and a manufacturing method thereof. The method includes: providing a semiconductor substrate provided with a body region, a gate dielectric layer, and a field oxide layer, formed on the semiconductor substrate; forming a gate polycrystalline, the gate polycrystalline covering the gate dielectric layer and the field oxide layer and exposing at least one portion of the field oxide layer; forming a drift region in the semiconductor substrate by ion implantation using a drift region masking layer as a mask, removing the exposed portion of the field oxide layer by further using the drift region masking layer as the mask to form a first field oxide self-aligned with the gate polycrystalline; forming a source region in the body region, and forming a drain region in the drift region; forming a second field oxide on the semiconductor substrate; and forming a second field plate on the second field oxide.

19. 发明授权

US11462536B2 Integrated circuit structures having asymmetric source and drain structures 有权
公开(公告)号：US11462536B2
公开(公告)日：2022-10-04
申请号：US16147538
申请日：2018-09-28
申请人： Intel Corporation
发明人： Anupama Bowonder , Rishabh Mehandru , Mark Bohr , Tahir Ghani
IPC分类号： H01L29/76 , H01L29/94 , H01L27/092 , H01L21/8238 , H01L29/06 , H01L29/08 , H01L29/423 , H01L29/66 , H01L29/78
摘要： Integrated circuit structures having asymmetric source and drain structures, and methods of fabricating integrated circuit structures having asymmetric source and drain structures, are described. For example, an integrated circuit structure includes a fin, and a gate stack over the fin. A first epitaxial source or drain structure is in a first trench in the fin at a first side of the gate stack. A second epitaxial source or drain structure is in a second trench in the fin at a second side of the gate stack, the second epitaxial source or drain structure deeper into the fin than the first epitaxial source or drain structure.

20. 发明授权

US11444095B2 Semiconductor device with integrated memory devices and MOS devices and process of making the same 有权
公开(公告)号：US11444095B2
公开(公告)日：2022-09-13
申请号：US17229848
申请日：2021-04-13
申请人： UNITED MICROELECTRONICS CORP.
发明人： Wang Xiang , Chia-Ching Hsu , Shen-De Wang , Weichang Liu
IPC分类号： H01L29/76 , H01L29/66 , H01L27/092 , H01L27/11568 , H01L27/11573 , H01L21/02 , H01L21/28 , H01L29/49 , H01L21/3213 , H01L21/027 , H01L29/78 , H01L29/51 , H01L21/8238 , H01L21/311
摘要： A semiconductor device with integrated memory devices and metal-oxide-semiconductor (MOS) devices, including a substrate with a first area and a second area, multiple double-diffused metal-oxide-semiconductor (DMOS) devices on the first area, wherein the double-diffused metal-oxide-semiconductor (DMOS) device includes a field oxide on the substrate, a first gate dielectric layer adjacent to the field oxide, and a first polysilicon gate on the field oxide and the first gate dielectric layer, and multiple memory units on the second area, wherein the memory unit includes an oxide-nitride-oxide (ONO) tri-layer and a second polysilicon gate on the oxide-nitride-oxide (ONO) tri-layer, wherein a top surface of the second polysilicon gate of the memory unit in the second area and a top surface of the first polysilicon gate of the double-diffused metal-oxide-semiconductor (DMOS) in the first area are on the same level.

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