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11. 发明授权

US11545983B2 Systems and methods for phase locked loop realignment with skew cancellation 有权
公开(公告)号：US11545983B2
公开(公告)日：2023-01-03
申请号：US17159335
申请日：2021-01-27
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Tsung-Hsien Tsai , Ruey-Bin Sheen , Chih-Hsien Chang , Cheng-Hsiang Hsieh
IPC分类号： H03L7/089 , H03D13/00 , H03L7/099 , H03L7/093
摘要： Systems and methods are provided for a phase locked loop. A phase/frequency detector is configured to receive a reference signal and a feedback signal. A charge pump is configured to receive outputs from the phase/frequency detector and to generate pulses. An oscillator is configured to generate an output waveform based on the charge pump pulses. A realignment path is configured to generate a clock realignment signal that is provided to the oscillator based on the outputs from the phase/frequency detector.

12. 发明申请

US20220407526A1 PHASE NOISE PERFORMANCE USING MULTIPLE RESONATORS WITH VARYING QUALITY FACTORS AND FREQUENCIES 有权
公开(公告)号：US20220407526A1
公开(公告)日：2022-12-22
申请号：US17354089
申请日：2021-06-22
申请人： Skyworks Solutions, Inc.
发明人： Aslamali A. Rafi , Srisai R. Seethamraju
IPC分类号： H03L7/099 , H03B5/32 , H03L7/093
摘要： Nested phase-locked loops (PLLs) utilize resonators of different quality factors, oscillation frequencies, and tunability. A reference clock signal for a first PLL is based on a free running bulk acoustic wave (BAW) resonator. The first PLL utilizes an LC oscillator as a voltage controlled oscillator. A crystal oscillator supplies a reference clock signal to a second PLL. Feedback dividers of the first and second PLLs are coupled to the LC oscillator. A delta sigma modulator coupled to the loop filter of the second PLL controls the feedback divider of the first PLL. The first PLL utilizes a high update rate to ensure that the jitter power spectral density is spread over a wide frequency range. The nested PLL architecture allows the overall phase noise plot to follow that of the crystal resonator at low frequencies, the BAW resonator at mid-frequencies, and the LC resonator at high frequencies.

13. 发明申请

US20220385294A1 DIGITALLY CONTROLLED OSCILLATOR INSENSITIVE TO CHANGES IN PROCESS, VOLTAGE, TEMPERATURE AND DIGITAL PHASE LOCKED LOOP INCLUDING SAME 有权
公开(公告)号：US20220385294A1
公开(公告)日：2022-12-01
申请号：US17675351
申请日：2022-02-18
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： KANGYEOP CHOO , WOOSEOK KIM , WONSIK YU , CHANYOUNG JEONG
IPC分类号： H03L7/099 , H03L7/093 , H03B5/04
摘要： A digitally controlled oscillator (DCO) includes; a current mirror configured to generate a supply current in response to a bias voltage matching a reference current, a variable resistor connected to the current mirror through a first node outputting the reference current and configured to provide a variable resistance in response to a first control signal, an oscillation circuit connected to the current mirror through a second node outputting the supply current and configured to generate an oscillation signal in response to the supply current, and a feedback circuit configured to control the bias voltage in relation to at least one of a voltage at the first node and a voltage at the second node.

14. 发明申请

US20220368334A1 PHASE SYNCHRONIZATION CIRCUIT, TRANSMISSION AND RECEPTION CIRCUIT, AND SEMICONDUCTOR INTEGRATED CIRCUIT 有权
公开(公告)号：US20220368334A1
公开(公告)日：2022-11-17
申请号：US17877481
申请日：2022-07-29
申请人： Socionext Inc.
发明人： Hiromitsu OSAWA
IPC分类号： H03L7/099 , H03L7/093 , H03L7/18 , H03K3/023
摘要： A phase synchronization circuit includes: an oscillation circuit that includes a variable current generation unit that generates a variable current of a current amount corresponding to a control voltage and a fixed current generation unit that generates a fixed. current of a current amount corresponding to a correction code and generates an output clock signal having a frequency corresponding to the total current amount of the variable current and the fixed current; a feedback circuit that generates a feedback clock signal based on the output clock signal; a control voltage generation circuit that generates the control voltage to make a frequency of the output clock signal become a desired frequency in a normal operation mode; and a correction code generation circuit that generates the correction code in a calibration mode, in which in the calibration mode, the control voltage generation circuit outputs a fixed one of the control voltage.

15. 发明申请

US20220365173A1 RADAR SYSTEM 有权
公开(公告)号：US20220365173A1
公开(公告)日：2022-11-17
申请号：US17661944
申请日：2022-05-04
申请人： NXP B.V.
发明人： Ulrich Moehlmann , Cristian Pavao Moreira , Andreas Johannes Köllmann
IPC分类号： G01S7/40 , H03L7/093 , H03L7/099
摘要： Radar System The disclosure relates to a radar system having multiple radar transceiver modules, in which each module has a clock signal that is synchronised with a clock signal generated by a leader transceiver module. Example embodiments include a radar system (400) comprising a plurality of radar transceiver modules (401, 402) mounted to a common PCB (404), the plurality of radar transceiver modules comprising a leader module (401) and one or more follower modules (402), the leader module (401) comprising a first oscillator (403) configured to provide a first clock signal at a first frequency to each follower module (402), each of the leader and follower modules comprising a phase locked loop, PLL, clock signal generator (300), the PLL clock signal generator (300) comprising a divide by n clock divider (304) arranged to output 2n phase shifted clock signals (314) at a third frequency and a multiplexer (306) connected to receive the 2n phase shifted clock signals from the divide by n clock divider (304) and output a third clock signal (308) selected by an input phase select signal (307).

16. 发明授权

US11496139B2 Frequency measurement circuit with adaptive accuracy 有权
公开(公告)号：US11496139B2
公开(公告)日：2022-11-08
申请号：US17246232
申请日：2021-04-30
申请人： Movellus Circuits Incorporated
发明人： Xiao Wu , Jeffrey Fredenburg
IPC分类号： H03L7/099 , H03L7/183 , H03L7/093
摘要： A frequency measurement circuit includes a counter circuit to receive a first digitally-controlled oscillator (DCO) clock signal corresponding to a first DCO input codeword and a measurement signal. The counter circuit is responsive to the measurement signal to generate a count representing a measured frequency of the first DCO clock signal. A control circuit is configured to selectively adjust a parameter of the measurement signal for generating a second count of a second DCO clock signal corresponding to a second DCO codeword. The control circuit selectively adjusts the parameter based on a received control signal.

17. 发明授权

US11495382B2 High Q-factor inductor 有权
公开(公告)号：US11495382B2
公开(公告)日：2022-11-08
申请号：US16252618
申请日：2019-01-19
申请人： Intel Corporation
发明人： Mark Elzinga
IPC分类号： H01F17/00 , H03L7/093 , H03L7/099 , H01F41/04 , H03B5/08
摘要： Described is a high Q-factor inductor. The inductor is formed as a unit cell coil, which is copied twice for a dual-coil inductor and copied four times for a quad-coil inductor. For each copy of the unit cell coil, the coil is rotated a subsequent substantially 90 degrees or substantially −90 degrees. The rotation enables the terminals of the inductor to be routed equal-distant to a circuit that is placed in the line of symmetry between the two coils.

18. 发明授权

US11489532B2 Analog phase locked loop 有权
公开(公告)号：US11489532B2
公开(公告)日：2022-11-01
申请号：US17241578
申请日：2021-04-27
申请人： NXP B.V.
发明人： Mathieu Périn , Stefano Dal Toso
IPC分类号： H03L7/099 , H03L7/097 , H03L7/093
摘要： An analog PLL comprising: a VCO configured to provide a PLL output signal; a phase detector (PD) configured to receive a feedback signal from the VCO and a reference signal and wherein the PD provides a PD signal to a low pass filter (LPF), the LPF configured to filter of the PD signal and provide the filtered signal as a tuning voltage for the VCO; and a tracking loop configured to receive the tuning voltage and comprising at least a tracking loop comparator configured to provide a comparator output voltage based on a difference between the tuning voltage and a target voltage, wherein an output of the tracking loop provides a tracking voltage based on the comparator output voltage and wherein the frequency of the PLL output voltage is based on the tuning voltage and the tracking voltage.

19. 发明授权

US11489443B2 Charge pump circuit 有权
公开(公告)号：US11489443B2
公开(公告)日：2022-11-01
申请号：US17445598
申请日：2021-08-21
申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.
发明人： Haining Xu
IPC分类号： H02M3/07 , H03L7/093
摘要： A charge pump circuit includes: a charge pump core circuit configured to generate an output voltage, an oscillator configured to provide a clock signal for the charge pump core circuit, and a feedback circuit configured to control the oscillator based on the output voltage, wherein the feedback circuit includes an inner loop.

20. 发明申请

US20220321134A1 FREQUENCY DIVIDING CIRCUIT, FREQUENCY DIVIDING METHOD AND PHASE LOCKED LOOP 有权
公开(公告)号：US20220321134A1
公开(公告)日：2022-10-06
申请号：US17708944
申请日：2022-03-30
申请人： MAXIO Technology (Hangzhou) Co., Ltd.
发明人： Tengxiao Jiang , Zhiyu Zhuang , Yiren Huang
IPC分类号： H03L7/197 , H03L7/081 , H03L7/089 , H03L7/093
摘要： Disclosed is a frequency dividing circuit, a frequency dividing method and a phase locked loop. The frequency dividing circuit comprises: a clock selection unit outputting a first clock signal, select a second clock signal lagging behind the first clock signal by (½-1/M) of one phase; an integer frequency dividing unit performing frequency division on the first clock signal to provide a frequency-divided clock signal; a trigger unit triggering the frequency-divided clock signal according to the second clock signal to obtain a modulation clock signal; a switching signal unit providing a switching signal according to the modulation clock signal and a preset target output frequency. The clock selection unit selects and further outputs a third clock signal as the first clock signal according to the target phase selection information, to adjust the frequency of the frequency-divided clock signal, reduce noise and improve loop bandwidth of the phase locked loop.

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