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21. 发明授权

US10261426B2 Optimization method and system for overlay error compensation 有权
公开(公告)号：US10261426B2
公开(公告)日：2019-04-16
申请号：US15800071
申请日：2017-11-01
申请人： Shanghai Huali Microelectronics Corporation
发明人： Yunqing Dai , Jian Wang
IPC分类号： G03F7/20 , H01L21/68 , H01L21/66
摘要： An optimization method for overlay error compensation is disclosed. The method comprises setting process parameters for each semiconductor layer of a semiconductor device corresponding to a run path formed by different lithographic apparatus which sequentially process target semiconductor layers from a first target layer to a latest target layer; measuring overlay errors between an actual and a theoretical exposed patterns of the first semiconductor layer; selecting a group of process parameters corresponding to the run path from the first target layer to the latest target layer aligned by the current semiconductor layer; after exposing the current semiconductor layer using the selected process parameters, measuring overlay errors between the current semiconductor layer and its target layer; and correcting the selected process parameters according to the overlay errors between the current semiconductor layer and its target layer, and the overlay errors between the actual and theoretical exposed patterns of the first semiconductor layer.

22. 发明授权

US10134900B2 SiGe source/drain structure and preparation method thereof 有权
公开(公告)号：US10134900B2
公开(公告)日：2018-11-20
申请号：US15390528
申请日：2016-12-25
申请人： SHANGHAI HUALI MICROELECTRONICS CORPORATION
发明人： Qiuming Huang , Jun Tan , Qiang Yan
IPC分类号： H01L29/78 , H01L21/8234 , H01L29/66 , H01L29/165 , H01L29/49 , H01L29/04 , H01L29/06 , H01L29/40 , H01L21/02 , H01L21/306
摘要： A structure of SiGe source/drain and a preparation method thereof are disclosed in the present invention. Firstly, providing a semiconductor single crystal silicon substrate. Secondly, etching the semiconductor single crystal silicon substrate to form recesses on both sides of the gate. Thirdly, epitaxially growing a SiGe seed layer and a SiGe bulk layer in the recesses in turn. Fourthly, subjecting the SiGe bulk layer to a crystal plane treatment with a mixed-gases. Fifthly, epitaxially growing a lattice change layer on the SiGe bulk layer. Finally, epitaxially growing a cap layer on the lattice change layer. The preparation method of the present invention can greatly improve the morphology of the SiGe epitaxy in the incomplete Un-tuck structure, and promote the formation of the subsequent metal silicide (NiSi), so that problems such as abnormal resistance and leakage of active area (AA leakage) can be effectively prevented.

23. 发明授权

US10083266B2 Simulation method of CMP process 有权
公开(公告)号：US10083266B2
公开(公告)日：2018-09-25
申请号：US15283286
申请日：2016-09-30
申请人： SHANGHAI HUALI MICROELECTRONICS CORPORATION
发明人： Yun Cao , Huan Kan , Fang Wei , Jun Zhu , Yukun Lv , Xusheng Zhang
IPC分类号： G06F17/50 , H01L21/768
CPC分类号： G06F17/504 , G06F2217/16 , H01L21/3212 , H01L21/76819
摘要： A simulation method of CMP process comprises: building a CMP model, and forming a matrix table of line width logarithm-density according to the CMP model, and making each intersection of the matrix table correspond to each CMP result under the corresponding line width and density; dividing a layout into a plurality of grids, and converting the equivalent line width and density of each grid into the coordinate of line width logarithm-density in the matrix table; fitting and calculating preliminary CMP simulation results of each grid according to the coordinate of each grid in the matrix table and the CMP simulation results of its adjacent intersections of the matrix table; fitting and computing final CMP simulation results of each grid according to a related weighting factor which considers the impact of adjacent grids for the current grid on the layout; outputting the final CMP simulation results of the whole layout.

24. 发明申请

US20180175195A1 HIGH PRESSURE LOW THERMAL BUDGE HIGH-K POST ANNEALING PROCESS 审中-公开
公开(公告)号：US20180175195A1
公开(公告)日：2018-06-21
申请号：US15429194
申请日：2017-02-10
申请人： Shanghai Huali Microelectronics Corporation
发明人： Qiuming Huang
IPC分类号： H01L29/78 , H01L21/306 , H01L21/02 , H01L29/08 , H01L29/165 , H01L29/66 , H01L21/3065 , H01L21/308 , H01L29/167 , H01L27/11
CPC分类号： H01L29/7848 , H01L21/02181 , H01L21/02381 , H01L21/02532 , H01L21/0262 , H01L21/28185 , H01L21/30604 , H01L21/3065 , H01L21/3081 , H01L27/1104 , H01L29/0847 , H01L29/165 , H01L29/167 , H01L29/517 , H01L29/66545 , H01L29/66636
摘要： A method of embedding SiGe when fabricating a PMOS device is provided. Multiple layers of SiGe layers with different Ge contents may be formed such that the Ge content increases to from bottom layer(s) to middle layer(s), and decreases from the middle layer(s) to top layer(s). In some embodiments, the embedded SiGe can have a SiGe seed layer over a substrate, a first SiGe transition layer over the SiGe seed layer, a SiGe milled layer over the first SiGe transition layer, and a second SiGe transition layer over the SiGe middle layer. The first SiGe transition layer can have a Ge content increasing from a bottom of the first SiGe transition layer to a top of the first SiGe transition layer. The second SiGe transition layer can have a Ge content decreasing from a bottom of the second SiGe transition layer to a top of the second SiGe transition layer.

25. 发明申请

US20180175157A1 METHOD FOR AVOIDING IL REGROWN IN A HKMG PROCESS 审中-公开
公开(公告)号：US20180175157A1
公开(公告)日：2018-06-21
申请号：US15429192
申请日：2017-02-10
申请人： Shanghai Huali Microelectronics Corporation
发明人： Yingming Liu , Yu Bao , Haifeng Zhou , Jingxun Fang
IPC分类号： H01L29/51 , H01L29/423 , H01L21/28 , H01L21/02 , H01L29/66 , H01L29/78
CPC分类号： H01L29/517 , H01L21/28185 , H01L21/28229 , H01L29/49 , H01L29/513 , H01L29/66545 , H01L29/78
摘要： The present disclosure addresses and solves the current problem of oxygen accumulation in IL after an HKMG stack is formed. A fabrication method is provided for fabricating high-k/metal gate semiconductor device by forming at least one Titanium (Ti) layer between multiple HK layers. A high-k/metal gate semiconductor device including at least one TiO2 layer between multiple HK layers is also provided.

26. 发明申请

US20180174924A1 FABRICATION TECHNOLOGY FOR METAL GATE 审中-公开
公开(公告)号：US20180174924A1
公开(公告)日：2018-06-21
申请号：US15429195
申请日：2017-02-10
申请人： Shanghai Huali Microelectronics Corporation
发明人： Tong Lei , Yongyue Chen , Haifeng Zhou
IPC分类号： H01L21/8238 , H01L27/092 , H01L29/66 , H01L21/02 , H01L21/321 , H01L21/033
CPC分类号： H01L21/823828 , H01L21/02115 , H01L21/02167 , H01L21/0332 , H01L21/3212 , H01L21/823842 , H01L27/0922 , H01L29/66545
摘要： One aspect of the present disclosure is a method of fabricating metal gate by forming special layers in place of traditional TiN hard mask over the ILD0 layer to avoid ILD0 losses due to conventional ILD0 CMP. The method can comprise: after the ILD0 CMP, forming a first thin ashable film layer over the ILD0 layer; then forming a second thin dielectric layer over the first layer; during the aluminum CMP process for a first region (PMOS or NMOS), removing the second layer through polishing until the top surface of the first ashable film layer; and then removing first ashable film layer through an ashing method such as burning. In this way, ILD0 loss can be reduced during the first aluminum CMP step and thus can reduce initial height of ILD0, which in turn can reduce the height of initial dummy gate filled in the cavity.

27. 发明授权

US09680023B1 Method of manufacturing a dual-gate FinFET 有权
公开(公告)号：US09680023B1
公开(公告)日：2017-06-13
申请号：US15235124
申请日：2016-08-12
申请人： Yu Bao
发明人： Yu Bao
IPC分类号： H01L27/108 , H01L29/78 , H01L29/40 , H01L29/66
CPC分类号： H01L29/7855 , H01L29/401 , H01L29/66545 , H01L29/66795
摘要： A method of manufacturing a dual-gate FinFET is provided. The method includes: forming a fin structure on the semiconductor substrate, depositing an oxide layer and planarizing until the top of the fin structure is exposed, depositing a hard mask layer and patterning, preforming a first etch back process to one side of the oxide layer, and then removing the rest of the hard mask layer, preforming a second etch back process to the oxide layers at both sides of the fin structure simultaneously, forming a gate dielectric layer on surface of the fin structure, then depositing gate material on the gate dielectric layer and patterning, removing gate material on top of the fin structure, forming a drive gate and a control gate at two sides of the fin structure respectively; wherein height of the control gate is higher than height of the drive gate.

28. 发明授权

US09390915B1 Methods and systems for improved uniformity of SiGe thickness 有权
标题翻译：提高SiGe厚度均匀性的方法和系统
公开(公告)号：US09390915B1
公开(公告)日：2016-07-12
申请号：US14691520
申请日：2015-04-20
申请人： Shanghai Huali Microelectronics Corporation
发明人： Quanbo Li , Jun Huang , Xiangguo Meng
IPC分类号： H01L21/762 , H01L21/02 , H01L21/311 , H01L21/66
CPC分类号： H01L21/02532 , H01L21/0206 , H01L21/02115 , H01L21/02118 , H01L21/02282 , H01L21/3086 , H01L21/31111 , H01L21/31133 , H01L21/76224 , H01L21/76232 , H01L22/26 , H01L29/165 , Y02P80/30
摘要： A process is used to form a protective layer to cover a divot between two regions of a semiconductor material. During etching processes, the protective layer protects the divot to be etched away and reduces material loss of a Silicon (Si)-shallow trench isolation (STI) substrate. A selective coverage is provided to protect the height of the Si-STI substrate and an Si-STI interface. A desirable geometry can be obtained for forming a silicon germanium (SiGe)layer with uniform thickness near the divot.
摘要翻译：一种方法用于形成保护层以覆盖半导体材料的两个区域之间的凹陷。在蚀刻过程中，保护层保护纹理被蚀刻掉，并减少硅（Si） - 浅沟槽隔离（STI）衬底的材料损失。提供选择性覆盖以保护Si-STI衬底和Si-STI界面的高度。可以获得期望的几何形状，用于形成具有均匀厚度的硅锗（SiGe）层。

29. 发明授权

US09171731B2 Method of forming the gate with the LELE double pattern 有权
标题翻译：用LELE双重图案形成门的方法
公开(公告)号：US09171731B2
公开(公告)日：2015-10-27
申请号：US14085380
申请日：2013-11-20
申请人： Shanghai Huali Microelectronics Corporation
发明人： Jun Huang , ZhiBiao Mao , QuanBo Li , ZhiFeng Gan , RunLing Li
IPC分类号： H01L21/302 , H01L21/306 , H01L21/28 , H01L21/033 , H01L21/3213 , H01L21/308
CPC分类号： H01L21/306 , H01L21/0337 , H01L21/28123 , H01L21/3081 , H01L21/3086 , H01L21/32139
摘要： The invention relates to microelectronic technology and, more specifically, relates to a method of forming a gate with a LELE double pattern. The method adopts an ONO structure (Oxide-SiN-Oxide). The ONO structure is exposed twice, and the advanced patterning film is used as a mask in the processing of polysilicon etching. The ONO structure is used to replace the traditional hardmask of silicon oxide, and the substructure of ODL (Organic Under Layer) which is based on the spin-on, and the middle layer structure of SHB (Si-based hardmask). The method saves cost and improves the process of advanced patterning film as a mask with the nodes in 40 nm and above which is applied to the process with the nodes in 22/20 nm and below. Consequently, the maturity and stability of the process for poly gate with the nodes in 22/20 nm and below are improved.
摘要翻译：本发明涉及微电子技术，更具体地说，涉及一种用LELE双重图案形成门的方法。该方法采用ONO结构（Oxide-SiN-Oxide）。 ONO结构暴露两次，并且在多晶硅蚀刻的处理中使用先进的图案化膜作为掩模。 ONO结构用于替代传统的氧化硅硬掩模，以及基于旋涂的ODL（有机底层）的底层结构和SHB（Si基硬掩模）的中间层结构。该方法节省了成本，并改进了高级图案化膜作为掩模的过程，其中40nm及以上的节点被应用于具有22/20nm及以下的节点的过程。因此，22/20nm及以下节点的多晶硅栅极的成熟度和稳定性得到改善。

30. 发明授权

US09123619B2 Method for inhibiting the electric crosstalk of back illuminated CMOS image sensor 有权
标题翻译：抑制背照式CMOS图像传感器的电串扰的方法
公开(公告)号：US09123619B2
公开(公告)日：2015-09-01
申请号：US14098017
申请日：2013-12-05
申请人： SHANGHAI HUALI MICROELECTRONICS CORPORATION
发明人： Zhi Tian , QiuMin Jin
IPC分类号： H01L21/00 , H01L27/146
CPC分类号： H01L27/14689 , H01L27/14609
摘要： The present invention discloses a method for inhibiting the electric crosstalk of back illuminated CMOS image sensor. This invention comprises, two ion implanting layers are implanted at the different area of the backside of the pixel unit after the thickness of the backside of CMOS image sensor is reduced. The ion concentrations implanted into the two layers are controlled to decrease progressively from top to bottom. An electric field is formed from top to bottom inside the epitaxial layer. The said electric field absorbs the incident light which arrives at the substrate region outside of the space charge of the photodiode. It reduces the electron diffuses in different pixels. Consequently, it reduces the electric crosstalk of pixels, improves the manufacture process and improve the image quality of the of CMOS image sensor.
摘要翻译：本发明公开了一种抑制背照式CMOS图像传感器的电串扰的方法。本发明包括：在CMOS图像传感器的背面的厚度减小之后，将两个离子注入层注入到像素单元的背面的不同区域。控制注入两层的离子浓度从上到下逐渐降低。在外延层内部从上到下形成电场。所述电场吸收到达光电二极管的空间电荷之外的衬底区域的入射光。它可以减少不同像素的电子扩散。因此，它减少了像素的电串扰，改善了CMOS图像传感器的制造工艺和图像质量。

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