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21. 发明授权

US07936004B2 Nonvolatile semiconductor memory device and manufacturing method thereof 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US07936004B2
公开(公告)日：2011-05-03
申请号：US11654551
申请日：2007-01-18
申请人： Masaru Kito , Hideaki Aochi , Ryota Katsumata , Akihiro Nitayama , Masaru Kidoh , Hiroyasu Tanaka , Yoshiaki Fukuzumi , Yasuyuki Matsuoka , Mitsuru Sato
发明人： Masaru Kito , Hideaki Aochi , Ryota Katsumata , Akihiro Nitayama , Masaru Kidoh , Hiroyasu Tanaka , Yoshiaki Fukuzumi , Yasuyuki Matsuoka , Mitsuru Sato
IPC分类号： H01L27/115
CPC分类号： H01L27/11582 , G11C16/0483 , H01L21/8221 , H01L27/0688 , H01L27/105 , H01L27/115 , H01L27/11556 , H01L27/11573 , H01L27/11578
摘要： A nonvolatile semiconductor memory device includes a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; a second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory string and the first to nth electrodes of at least two other memory strings which are adjacent to the memory string in two directions are shared as first to nth conductor layers spread in two dimensions.
摘要翻译：非易失性半导体存储器件包括其中多个可电可编程存储器单元串联连接的多个存储器串。存储器串包括柱形半导体; 形成在柱状半导体周围的第一绝缘膜; 形成在所述第一绝缘膜周围的电荷存储层; 形成在电荷存储层周围的第二绝缘膜; 并且形成在第二绝缘膜周围的第一或第n电极（n是大于1的自然数）。存储器串的第一或第n电极以及在两个方向上与存储器串相邻的至少两个其它存储器串的第一至第n电极被共享为在二维上扩展的第一至第n导体层。

22. 发明申请

US20110051527A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20110051527A1
公开(公告)日：2011-03-03
申请号：US12725827
申请日：2010-03-17
申请人： Ryouhei Kirisawa , Masaru Kito , Shigeto Oota , Yoshimasa Mikajiri
发明人： Ryouhei Kirisawa , Masaru Kito , Shigeto Oota , Yoshimasa Mikajiri
IPC分类号： G11C16/04 , G11C16/02
CPC分类号： G11C16/14 , G11C16/0483 , G11C16/10 , G11C16/26 , H01L27/11582
摘要： A nonvolatile semiconductor memory device includes: a memory unit; and a control unit. The memory unit includes: first and second memory strings including first and second memory transistors with first and second select gates, respectively; and first and second wirings connected thereto. In a selective erase operation of a selected cell transistor of the first memory transistors, the control unit applies V1 voltage to the first wiring, applies V2 voltage lower than V1 to a selected cell gate of the selected cell transistor, applies V3 voltage not higher than V1 and higher than V2 to a non-selected cell gate of the first memory transistors, applies V1 or V4 voltage not higher than V1 and not lower than V3 to the first select gate, and applies V2 or V4 voltage higher than V2 and not higher than V3 to the second wiring or sets the second wiring in a floating state.
摘要翻译：非易失性半导体存储器件包括：存储器单元; 和控制单元。存储单元包括：第一和第二存储器串，分别包括具有第一和第二选择栅极的第一和第二存储器晶体管; 以及与其连接的第一和第二布线。在第一存储晶体管的所选单元晶体管的选择性擦除操作中，控制单元向第一布线施加V1电压，向所选单元晶体管的选定单元栅极施加低于V1的V2电压，施加不高于 V1并且高于V2到第一存储晶体管的未选择的单元栅极，向第一选择栅施加不高于V1且不低于V3的V1或V4电压，并且施加V2或V4电压高于V2而不是更高而不是V3到第二布线，或将第二布线置于浮置状态。

23. 发明申请

US20110018050A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20110018050A1
公开(公告)日：2011-01-27
申请号：US12727830
申请日：2010-03-19
申请人： Tomoko FUJIWARA , Ryota Katsumata , Masaru Kito , Yoshiaki Fukuzumi , Masaru Kidoh , Hiroyasu Tanaka , Yosuke Komori , Megumi Ishiduki , Junya Matsunami , Hideaki Aochi , Ryouhei Kirisawa , Yoshimasa Mikajiri , Shigeto Oota
发明人： Tomoko FUJIWARA , Ryota Katsumata , Masaru Kito , Yoshiaki Fukuzumi , Masaru Kidoh , Hiroyasu Tanaka , Yosuke Komori , Megumi Ishiduki , Junya Matsunami , Hideaki Aochi , Ryouhei Kirisawa , Yoshimasa Mikajiri , Shigeto Oota
IPC分类号： H01L29/51 , H01L21/4763
CPC分类号： H01L27/11551 , H01L27/11524 , H01L27/11526 , H01L27/11529 , H01L27/11556
摘要： A nonvolatile semiconductor memory device, includes: a stacked structural unit including electrode films alternately stacked with inter-electrode insulating films; first and second semiconductor pillars piercing the stacked structural unit; a connection portion semiconductor layer electrically connect the first and second semiconductor pillars; a connection portion conductive layer provided to oppose the connection portion semiconductor layer; a memory layer and an inner insulating film provided between the first and semiconductor pillars and each of the electrode films, and between the connection portion conductive layer and the connection portion semiconductor layer; an outer insulating film provided between the memory layer and each of the electrode films; and a connection portion outer insulating film provided between the memory layer and the connection portion conductive layer. The connection portion outer insulating film has a film thickness thicker than a film thickness of the outer insulating film.
摘要翻译：一种非易失性半导体存储器件，包括：堆叠结构单元，其包括交替层叠有电极间绝缘膜的电极膜; 第一和第二半导体柱刺穿堆叠结构单元; 连接部分半导体层电连接第一和第二半导体柱; 连接部分导电层，设置成与连接部分半导体层相对; 设置在所述第一半导体柱和所述半导体柱之间以及所述电极膜之间并且位于所述连接部分导电层和所述连接部半导体层之间的存储层和内部绝缘膜; 设置在所述存储层和每个所述电极膜之间的外部绝缘膜; 以及设置在存储层和连接部分导电层之间的连接部分外绝缘膜。连接部外绝缘膜的膜厚比外绝缘膜的膜厚厚。

24. 发明授权

US07838996B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07838996B2
公开(公告)日：2010-11-23
申请号：US11826709
申请日：2007-07-18
申请人： Mitsuru Sato , Masaru Kito , Yuzo Nagata
发明人： Mitsuru Sato , Masaru Kito , Yuzo Nagata
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76838 , H01L21/0337 , H01L21/32139 , H01L27/0203 , H01L27/115 , H01L27/11519 , H01L27/11565 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device comprises a wiring layer. The wiring layer is provided by forming a sidewall film having a closed-loop along a sidewall of a hard mask, etching off the hard mask to leave the sidewall film, and then etching a target material to be etched with a mask of the sidewall film. The wiring layer includes a folded wiring section formed along an end of the hard mask, and a parallel section composed of two parallel wires continued from the folded wiring section. The wiring layer has a closed-loop cut made in a portion except for the folded wiring section and the parallel section. The folded wiring section and the parallel section are used as a contact region for connection to another wire.
摘要翻译：半导体器件包括布线层。布线层通过沿着硬掩模的侧壁形成具有闭环的侧壁膜，蚀刻出硬掩模以离开侧壁膜，然后用侧壁膜的掩模蚀刻待蚀刻的目标材料来提供。布线层包括沿着硬掩模的端部形成的折叠布线部分和由折叠的布线部分连续的两条平行的线构成的平行部分。布线层具有除了折叠布线部分和平行部分之外的部分中的闭环切割。折叠的布线部分和平行部分用作用于连接到另一导线的接触区域。

25. 发明申请

US20100219465A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20100219465A1
公开(公告)日：2010-09-02
申请号：US12773038
申请日：2010-05-04
申请人： Hiroyasu TANAKA , Hideaki Aochi , Ryota Katsumata , Masaru Kidoh , Yoshiaki Fukuzumi , Masaru Kito , Yasuyuki Matsuoka
发明人： Hiroyasu TANAKA , Hideaki Aochi , Ryota Katsumata , Masaru Kidoh , Yoshiaki Fukuzumi , Masaru Kito , Yasuyuki Matsuoka
IPC分类号： H01L29/78
CPC分类号： H01L29/792 , H01L21/28282 , H01L27/11578 , H01L27/11582 , H01L29/0649 , H01L29/7923 , H01L29/7926
摘要： A semiconductor device has a substrate, a source region formed on the surface portion of the substrate, a first insulating layer formed on the substrate, a gate electrode formed on the first insulating layer, a second insulating layer formed on the gate electrode, a body section connected with the source region, penetrating through the first insulating layer, the gate electrode and the second insulating layer, and containing a void, a gate insulating film surrounding the body section, and formed between the body section and the gate electrode, and a drain region connected with the body section.
摘要翻译：半导体器件具有衬底，形成在衬底的表面部分上的源极区域，形成在衬底上的第一绝缘层，形成在第一绝缘层上的栅电极，形成在栅电极上的第二绝缘层，主体与源极区域连接，穿过第一绝缘层，栅电极和第二绝缘层，并且包含空隙，围绕主体部分的栅极绝缘膜，并且形成在主体部分和栅电极之间，并且漏极区域与主体部分连接。

26. 发明申请

US20100207190A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20100207190A1
公开(公告)日：2010-08-19
申请号：US12705231
申请日：2010-02-12
申请人： Ryota KATSUMATA , Masaru Kito , Masaru Kidoh , Hiroyasu Tanaka , Megumi Ishiduki , Yosuke Komori , Yoshiaki Fukuzumi , Hideaki Aochi
发明人： Ryota KATSUMATA , Masaru Kito , Masaru Kidoh , Hiroyasu Tanaka , Megumi Ishiduki , Yosuke Komori , Yoshiaki Fukuzumi , Hideaki Aochi
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L27/11578 , G11C16/0483 , H01L27/0688 , H01L27/11582 , H01L29/42344 , H01L29/66833 , H01L29/792 , H01L29/7926
摘要： A nonvolatile semiconductor memory device, includes: a stacked body including a plurality of insulating films alternately stacked with a plurality of electrode films, the electrode films being divided to form a plurality of control gate electrodes aligned in a first direction; a plurality of semiconductor pillars aligned in a stacking direction of the stacked body, the semiconductor pillars being arranged in a matrix configuration along the first direction and a second direction intersecting the first direction to pierce the control gate electrodes; and a connection member connecting a lower end portion of one of the semiconductor pillars to a lower end portion of one other of the semiconductor pillars, an upper end portion of the one of the semiconductor pillars being connected to a source line, an upper end portion of the one other of the semiconductor pillars being connected to a bit line. At least some of the control gate electrodes are pierced by two of the semiconductor pillars adjacent to each other in the second direction. Two of the semiconductor pillars being connected to each other by the connection member pierce mutually different control gate electrodes.
摘要翻译：一种非易失性半导体存储器件，包括：堆叠体，包括交替层叠有多个电极膜的多个绝缘膜，所述电极膜被分割以形成沿第一方向排列的多个控制栅电极; 多个半导体柱沿层叠体的堆叠方向排列，半导体柱沿着第一方向排列成矩阵构造，第二方向与第一方向相交以刺穿控制栅电极; 以及将所述半导体柱之一的下端部连接到所述半导体柱的另一个的下端部的连接部件，所述一个半导体柱的上端部与源极线连接，上端部另一个半导体柱被连接到位线。至少一些控制栅极电极在第二方向上被彼此相邻的两个半导体柱刺穿。通过连接构件彼此连接的两个半导体柱穿透相互不同的控制栅电极。

27. 发明申请

US20100052042A1 SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20100052042A1
公开(公告)日：2010-03-04
申请号：US12561451
申请日：2009-09-17
申请人： Hiroyasu TANAKA , Ryota KATSUMATA , Hideaki AOCHI , Masaru KIDO , Masaru KITO , Mitsuru SATO
发明人： Hiroyasu TANAKA , Ryota KATSUMATA , Hideaki AOCHI , Masaru KIDO , Masaru KITO , Mitsuru SATO
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/792 , H01L21/8221 , H01L27/0688 , H01L27/105 , H01L27/11548 , H01L27/11551 , H01L27/11556 , H01L27/11575 , H01L27/11578 , H01L27/11582 , H01L29/7881 , H01L29/7926
摘要： The semiconductor memory device of the present invention includes a plurality of memory strings having a plurality of electrically reprogrammable memory cells connected in series, the memory strings having a column shaped semiconductor, a first insulation film formed around the column shaped semiconductor, a charge accumulation layer formed around the first insulation film, a second insulation film formed around the charge accumulation film and a plurality of electrodes formed around the second insulation film, a bit line connected to one end of the memory strings via a plurality of selection transistors, and a conducting layer extending in two dimensions and in which the plurality of electrodes of the memory strings and the plurality of electrodes of different memory strings are shared respectively, wherein each end part of the conducting layer is formed in step shapes in a direction parallel with the bit line.
摘要翻译：本发明的半导体存储器件包括具有串联连接的多个电可再编程存储器单元的多个存储器串，具有列形半导体的存储器串，形成在柱状半导体周围的第一绝缘膜，电荷累积层形成在第一绝缘膜周围，形成在电荷累积膜周围的第二绝缘膜和围绕第二绝缘膜形成的多个电极，经由多个选择晶体管连接到存储器串的一端的位线，以及导电分别在存储器串的多个电极和不同的存储器串的多个电极中分别共享，其中导电层的每个端部在平行于位线的方向上形成为台阶形状。

28. 发明申请

US20100044776A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20100044776A1
公开(公告)日：2010-02-25
申请号：US12535847
申请日：2009-08-05
申请人： Megumi Ishiduki , Ryota Katsumata , Masaru Kidoh , Hiroyasu Tanaka , Yosuke Komori , Masaru Kito , Yoshiaki Fukuzumi , Hideaki Aochi
发明人： Megumi Ishiduki , Ryota Katsumata , Masaru Kidoh , Hiroyasu Tanaka , Yosuke Komori , Masaru Kito , Yoshiaki Fukuzumi , Hideaki Aochi
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L27/11578 , H01L27/11565 , H01L27/11582 , H01L29/792 , H01L29/7926
摘要： A multilayer body is formed by alternately stacking electrode films serving as control gates and dielectric films in a direction orthogonal to an upper surface of a silicon substrate. Trenches extending in the word line direction are formed in the multilayer body and a memory film is formed on an inner surface of the trench. Subsequently, a silicon body is buried inside the trench, and a charge storage film and the silicon body are divided in the word line direction to form silicon pillars. This simplifies the configuration of memory cells in the bit line direction, and hence can shorten the arrangement pitch of the silicon pillars, decreasing the area per memory cell.
摘要翻译：通过在与硅衬底的上表面正交的方向上交替堆叠用作控制栅极和电介质膜的电极膜来形成多层体。在多层体中形成在字线方向上延伸的沟槽，并且在沟槽的内表面上形成记忆膜。随后，将硅体埋在沟槽内，并且电荷存储膜和硅体在字线方向上分开以形成硅柱。这简化了位线方向上的存储单元的配置，因此可以缩短硅柱的排列间距，减小每个存储单元的面积。

29. 发明申请

US20090294844A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20090294844A1
公开(公告)日：2009-12-03
申请号：US12132181
申请日：2008-06-03
申请人： Hiroyasu TANAKA , Hideaki Aochi , Ryota Katsumata , Masaru Kidoh , Yoshiaki Fukuzumi , Masaru Kito , Yasuyuki Matsuoka
发明人： Hiroyasu TANAKA , Hideaki Aochi , Ryota Katsumata , Masaru Kidoh , Yoshiaki Fukuzumi , Masaru Kito , Yasuyuki Matsuoka
IPC分类号： H01L29/739
CPC分类号： H01L29/792 , H01L21/28282 , H01L27/11578 , H01L27/11582 , H01L29/0649 , H01L29/7923 , H01L29/7926
摘要： A semiconductor device has a substrate, a source region formed on the surface portion of the substrate, a first insulating layer formed on the substrate, a gate electrode formed on the first insulating layer, a second insulating layer formed on the gate electrode, a body section connected with the source region, penetrating through the first insulating layer, the gate electrode and the second insulating layer, and containing a void, a gate insulating film surrounding the body section, and formed between the body section and the gate electrode, and a drain region connected with the body section.
摘要翻译：半导体器件具有衬底，形成在衬底的表面部分上的源极区域，形成在衬底上的第一绝缘层，形成在第一绝缘层上的栅电极，形成在栅电极上的第二绝缘层，主体与源极区域连接，穿过第一绝缘层，栅电极和第二绝缘层，并且包含空隙，围绕主体部分的栅极绝缘膜，并且形成在主体部分和栅电极之间，并且漏极区域与主体部分连接。

30. 发明申请

US20090267135A1 NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：非挥发性半导体存储器件及其制造方法
公开(公告)号：US20090267135A1
公开(公告)日：2009-10-29
申请号：US12408249
申请日：2009-03-20
申请人： Hiroyasu Tanaka , Ryota Katsumata , Masaru Kito , Yoshiaki Fukuzumi , Masaru Kidoh , Yosuke Komori , Hideaki Aochi , Megumi Ishiduki , Yasuyuki Matsuoka
发明人： Hiroyasu Tanaka , Ryota Katsumata , Masaru Kito , Yoshiaki Fukuzumi , Masaru Kidoh , Yosuke Komori , Hideaki Aochi , Megumi Ishiduki , Yasuyuki Matsuoka
IPC分类号： H01L29/78 , H01L21/28
CPC分类号： H01L27/11578 , H01L27/105 , H01L27/115 , H01L27/11573 , H01L27/11582
摘要： A non-volatile semiconductor storage device includes a first layer and a second layer. The first layer includes: a plurality of first conductive layers extending in parallel to a substrate and laminated in a direction perpendicular to the substrate; a first insulation layer formed on an upper layer of the plurality of first conductive layers; a first semiconductor layer formed to penetrate the plurality of first conductive layers; and a charge accumulation layer formed between the first conductive layers and the first semiconductor layer. Respective ends of the first conductive layers are formed in a stepwise manner in relation to each other in a first direction. The second layer includes: a plurality of second conductive layers extending in parallel to the substrate and laminated in a direction perpendicular to the substrate, the second conductive layers being formed in the same layer as the plurality of first conductive layers; and a second insulation layer formed on an upper layer of the plurality of second conductive layers. Respective ends of the second conductive layers are formed to align along a straight line extending in a direction substantially perpendicular to the substrate at a predetermined area.
摘要翻译：非易失性半导体存储装置包括第一层和第二层。第一层包括：多个第一导电层，其平行于衬底延伸并且在垂直于衬底的方向上层压; 形成在所述多个第一导电层的上层上的第一绝缘层; 形成为穿透所述多个第一导电层的第一半导体层; 以及形成在第一导电层和第一半导体层之间的电荷累积层。第一导电层的相应端部在第一方向上相对于彼此以逐步的方式形成。第二层包括：多个第二导电层，其平行于衬底延伸并且在垂直于衬底的方向上层叠，第二导电层形成在与多个第一导电层相同的层中; 以及形成在所述多个第二导电层的上层上的第二绝缘层。形成第二导电层的相应端，沿着在预定区域上基本上垂直于衬底的方向延伸的直线对齐。

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