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21. 发明授权

US09825223B2 Fin selector with gated RRAM 有权
公开(公告)号：US09825223B2
公开(公告)日：2017-11-21
申请号：US14689654
申请日：2015-04-17
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Eng Huat Toh , Elgin Quek , Shyue Seng Tan
IPC分类号： H01L47/00 , H01L45/00 , H01L27/24
CPC分类号： H01L45/144 , H01L27/2409 , H01L27/2436 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/1206 , H01L45/1226 , H01L45/1233 , H01L45/126 , H01L45/1286 , H01L45/146 , H01L45/1666
摘要： A method of fabricating a fin selector with a gated RRAM and the resulting device are disclosed. Embodiments include forming a bottom electrode layer and a hardmask on a semiconductor substrate; etching the hardmask, bottom electrode layer, and semiconductor substrate to form a fin-like structure; forming first and second dummy gate stacks on first and second side surfaces of the fin-like structure, respectively; forming spacers on vertical surfaces of the first and second dummy gate stacks; forming an ILD surrounding the spacers; removing the first and second dummy gate stacks, forming first and second cavities on first and second sides of the fin-like structure; forming an RRAM layer on the first and second side surfaces of the fin-like structure in the first and second cavities, respectively; and filling each of the first and second cavities with a top electrode.

22. 发明授权

US09537092B2 Integrated circuits with memory cells and methods of manufacturing the same 有权
标题翻译：具有存储单元的集成电路及其制造方法
公开(公告)号：US09537092B2
公开(公告)日：2017-01-03
申请号：US14665013
申请日：2015-03-23
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Zheng Zou , Alex See , Shyue Seng Tan
IPC分类号： H01L45/00 , H01L27/24
CPC分类号： H01L45/06 , H01L27/2409 , H01L27/2463 , H01L45/1233 , H01L45/126 , H01L45/1286 , H01L45/1293 , H01L45/144 , H01L45/16 , H01L45/1616 , H01L45/1675
摘要： Integrated circuits and methods for manufacturing the same are provided. An integrated circuit includes a lower electrode overlying a substrate, an insulating layer overlying the lower electrode, and an upper electrode overlying the insulating layer. The lower electrode, the insulating layer, and the upper electrode form a stack having a side surface. A phase change spacer is adjacent to the side surface, where the phase change spacer is electrically connected to the lower electrode and the upper electrode.
摘要翻译：提供了集成电路及其制造方法。集成电路包括覆盖基板的下电极，覆盖在下电极上的绝缘层和覆盖绝缘层的上电极。下电极，绝缘层和上电极形成具有侧表面的叠层。相变间隔件与侧表面相邻，其中相变间隔件电连接到下电极和上电极。

23. 发明授权

US09431497B2 Transistor devices having an anti-fuse configuration and methods of forming the same 有权
标题翻译：具有反熔丝结构的晶体管器件及其形成方法
公开(公告)号：US09431497B2
公开(公告)日：2016-08-30
申请号：US13899150
申请日：2013-05-21
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Eng Huat Toh , Shyue Seng Tan , Elgin Quek
IPC分类号： H01L29/76 , H01L29/423 , H01L27/112 , G11C17/16 , H01L29/66 , H01L29/78 , H01L27/06 , H01L27/108 , H01L27/12 , H01L21/822 , H01L23/525
CPC分类号： H01L29/42364 , G11C17/16 , H01L21/8221 , H01L23/5252 , H01L27/0688 , H01L27/10826 , H01L27/10879 , H01L27/11206 , H01L27/1203 , H01L29/66795 , H01L29/785 , H01L2029/42388 , H01L2924/0002 , H01L2924/00
摘要： Transistor devices having an anti-fuse configuration and methods of forming the transistor devices are provided. An exemplary transistor device includes a semiconductor substrate including a first fin. A first insulator layer overlies the semiconductor substrate and has a thickness less than a height of the first fin. The first fin extends through and protrudes beyond the first insulator layer to provide a buried fin portion and an exposed fin portion. A gate electrode structure overlies the exposed fin portion. A gate insulating structure is disposed between the first fin and the gate electrode structure. The gate insulating structure includes a first dielectric layer overlying a first surface of the first fin. The gate insulating structure further includes a second dielectric layer overlying a second surface of the first fin. A potential breakdown path is defined between the first fin and the gate electrode structure through the first dielectric layer.
摘要翻译：提供具有反熔丝配置的晶体管器件和形成晶体管器件的方法。示例性晶体管器件包括包括第一鳍片的半导体衬底。第一绝缘体层覆盖半导体衬底并且具有小于第一鳍片的高度的厚度。第一鳍延伸穿过第一绝缘体层并突出超过第一绝缘体层以提供掩埋鳍部分和暴露的鳍部分。栅电极结构覆盖在暴露的鳍部上。栅绝缘结构设置在第一鳍和栅电极结构之间。栅极绝缘结构包括覆盖第一鳍片的第一表面的第一介电层。栅极绝缘结构还包括覆盖第一鳍片的第二表面的第二介电层。通过第一介电层在第一鳍片和栅极电极结构之间限定电势击穿路径。

24. 发明授权

US09397146B2 Vertical random access memory with selectors 有权
标题翻译：带选择器的垂直随机存取存储器
公开(公告)号：US09397146B2
公开(公告)日：2016-07-19
申请号：US14277808
申请日：2014-05-15
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Eng Huat Toh , Yuan Sun , Elgin Kiok Boone Quek , Shyue Seng Tan , Xuan Anh Tran
IPC分类号： H01L27/24 , H01L27/06
CPC分类号： H01L27/249 , H01L27/0688 , H01L27/2409 , H01L27/2445 , H01L45/04 , H01L45/06 , H01L45/1226 , H01L45/146 , H01L45/16
摘要： Devices and methods for manufacturing a device are presented. The device includes a substrate and a vertical structure disposed over the substrate. The vertical structure includes one or more memory cell stacks with a dielectric layer between every two adjacent cell stacks. Each of the one or more cell stacks includes first and second first type conductors on first and second sides of the cell stack, respectively; first and second electrodes, the first electrode adjacent the first first type conductor, the second electrode adjacent the second first type conductor; and first and second memory elements, the first memory element disposed between the first first type conductor and the first electrode, the second memory element disposed between the second first type conductor and the second electrode. The device also includes a selector element disposed over the substrate and vertically traversing through a middle portion of the vertical structure. The selector element includes respective first and second selector diodes for the first and second memory elements of each of the one or more cell stacks.
摘要翻译：介绍了用于制造设备的设备和方法。该器件包括衬底和设置在衬底上的垂直结构。垂直结构包括一个或多个存储单元堆叠，每个两个相邻单元堆叠之间具有介电层。一个或多个单元堆叠中的每一个分别包括在单元堆叠的第一和第二侧上的第一和第二第一类型导体; 第一和第二电极，与第一第一类型导体相邻的第一电极，与第二第一类型导体相邻的第二电极; 以及第一和第二存储元件，第一存储元件设置在第一第一型导体与第一电极之间，第二存储元件设置在第二第一型导体与第二电极之间。该装置还包括选择器元件，其设置在基板上并且垂直地穿过垂直结构的中间部分。选择器元件包括用于一个或多个单元堆叠中的每一个的第一和第二存储元件的相应的第一和第二选择二极管。

25. 发明授权

US09368386B2 Corner transistor suppression 有权
标题翻译：角晶体管抑制
公开(公告)号：US09368386B2
公开(公告)日：2016-06-14
申请号：US13927588
申请日：2013-06-26
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Shyue Seng Tan , Ying Keung Leung , Elgin Quek
IPC分类号： H01L21/70 , H01L21/336 , H01L21/76 , H01L21/762 , H01L21/8234
CPC分类号： H01L29/0653 , H01L21/76224 , H01L21/76232 , H01L21/823481 , H01L27/088
摘要： The threshold voltage of parasitic transistors formed at corners of shallow trench isolation regions is increased and mobility decreased by employing a high-K dielectric material. Embodiments include STI regions comprising a liner of a high-K dielectric material extending proximate trench corners. Embodiments also include STI regions having a recess formed in the trench, wherein the recess contains a high-K dielectric material, in the form of a layer or spacer, extending proximate trench corners.
摘要翻译：形成在浅沟槽隔离区域的角落处的寄生晶体管的阈值电压增加，并且通过使用高K介电材料使迁移率降低。实施例包括STI区域，其包括在沟槽角附近延伸的高K电介质材料的衬垫。实施例还包括具有形成在沟槽中的凹部的STI区域，其中凹部包含在沟槽角附近延伸的层或间隔物形式的高K电介质材料。

26. 发明申请

US20230127768A1 TRANSISTOR WITH WRAP-AROUND EXTRINSIC BASE 有权
公开(公告)号：US20230127768A1
公开(公告)日：2023-04-27
申请号：US17509604
申请日：2021-10-25
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Xinshu Cai , Shyue Seng Tan , Vibhor Jain , John J. Pekarik , Kien Seen Daniel Chong , Yung Fu Chong , Judson R. Holt , Qizhi Liu , Kenneth J. Stein
IPC分类号： H01L29/737 , H01L29/10 , H01L29/45 , H01L29/66
摘要： The present disclosure relates to semiconductor structures and, more particularly, to transistor with wrap-around extrinsic base and methods of manufacture. The structure includes: a substrate; a collector region within the substrate; an emitter region over the substrate and which comprises mono-crystal silicon based material; an intrinsic base under the emitter region and comprising semiconductor material; and an extrinsic base surrounding the emitter and over the intrinsic base.

27. 发明授权

US11476303B2 Multi-level cell configurations for non-volatile memory elements in a bitcell 有权
公开(公告)号：US11476303B2
公开(公告)日：2022-10-18
申请号：US17111996
申请日：2020-12-04
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Desmond Jia Jun Loy , Eng Huat Toh , Shyue Seng Tan
IPC分类号： H01L27/24 , H01L45/00
摘要： Structures including non-volatile memory elements and methods of fabricating a structure including non-volatile memory elements. First, second, and third non-volatile memory elements each include a first electrode, a second electrode, and a switching layer between the first electrode and the second electrode. A first bit line is coupled to the first electrode of the first non-volatile memory element and to the first electrode of the second non-volatile memory element. A second bit line is coupled to the first electrode of the third non-volatile memory element.

28. 发明授权

US11462552B2 Semiconductor devices with memory cells 有权
公开(公告)号：US11462552B2
公开(公告)日：2022-10-04
申请号：US17146439
申请日：2021-01-11
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Desmond Jia Jun Loy , Wei Chang , Eng Huat Toh , Shyue Seng Tan
IPC分类号： H01L23/528 , H01L45/00 , H01L27/112
摘要： The present disclosure generally relates to semiconductor devices, and more particularly, to semiconductor devices having memory cells for multi-bit programming and methods of forming the same. The present disclosure also relates to a method of forming such semiconductor devices. The disclosed semiconductor devices may achieve a smaller cell size as compared to conventional devices, and therefore increases the packing density of the disclosed devices.

29. 发明授权

US11450677B2 Partially silicided nonvolatile memory devices and integration schemes 有权
公开(公告)号：US11450677B2
公开(公告)日：2022-09-20
申请号：US17093602
申请日：2020-11-09
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Lanxiang Wang , Shyue Seng Tan , Xinshu Cai , Eng Huat Toh , Yongshun Sun
IPC分类号： H01L27/11521 , H01L27/11558 , H01L27/11519
摘要： A nonvolatile memory device may be provided. The nonvolatile memory device comprises an active region, an n-well region and an isolation region separating the active region and the n-well region. A floating gate may be provided. The floating gate may be arranged over a portion of the active region and over a first portion of the n-well region. A first doped region in the active region may be laterally displaced from the floating gate on a first side and a second doped region in the active region may be laterally displaced from the floating gate on a second side opposite to the first side. A contact may be arranged over the n-well region, whereby the contact may be laterally displaced from a first corner of the floating gate over the first portion of the n-well region. A silicide exclusion layer may be arranged at least partially over the floating gate.

30. 发明授权

US11444125B2 Memory devices and methods of forming memory devices 有权
公开(公告)号：US11444125B2
公开(公告)日：2022-09-13
申请号：US16903503
申请日：2020-06-17
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Desmond Jia Jun Loy , Eng Huat Toh , Shyue Seng Tan
IPC分类号： H01L27/24 , H01L45/00 , G11C11/56 , G11C13/00
摘要： A memory device may be provided, including first, second and third electrodes, first and second mask elements and a switching layer. The first mask element may be arranged over a portion of and laterally offset from the first electrode. The second electrode may be arranged over the first mask element. The second mask element may be arranged over the second electrode. The third electrode may be arranged over a portion of and laterally offset from the second mask element. The switching layer may be arranged between the first electrode and the third electrode, along a first side surface of the first mask element, a first side surface of the second electrode and a first side surface of the second mask element.

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